CN101902321B - Clock management method and system - Google Patents
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- CN101902321B CN101902321B CN201010256032.XA CN201010256032A CN101902321B CN 101902321 B CN101902321 B CN 101902321B CN 201010256032 A CN201010256032 A CN 201010256032A CN 101902321 B CN101902321 B CN 101902321B
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Abstract
The invention provides a clock management method and system, relating to the communication field. The invention solves the problem that the typical clock schemes in the isochronous Ethernet can not meet the current operational needs of the systems. The method comprises the following steps: configuring a programmable PLL according to a destination clock source when a veneer clock source needs switching; and after configuration, indicating the programmable PLL to switch to the destination clock source and outputting reference clock according to the destination clock source. The technical scheme provided by the invention is applicable to the Ethernet.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of clock management method and system of ethernet device middle-high density veneer.
Background technology
Ethernet technology, as the basic medium access technology of a kind of local area network (LAN), due to the flexibility of its height and the simplicity of realization, has become important network technology and has been widely used.Constantly perfect along with IEEE1588 and synchronous ethernet technology, simultaneous techniques has obtained develop rapidly in ethernet device, at electric power, widely applies synchronous ethernet technology on the bearer network in industry control, metropolitan area network and wide area network.
The simultaneous techniques of Ethernet mainly comprises that protocol layer carries out the clock synchronous of the hardware circuit of synchronous and physical layer by packet.
For the hardware circuit of physical layer, along with the port density of ethernet device is increasing, on veneer, network control chip quantity is also more and more, in order to guarantee that each port can accomplish the synchronous of clock, this just requires the reference clock that offers each network control chip on this veneer in frequency or even phase place, can accomplish unanimously.Meanwhile, in order to guarantee the reliability of veneer work, on whole veneer, also need active and standby two clock sources for veneer provides the reference clock of veneer work, guarantee the normal operation of veneer under synchronous ethernet and two kinds of mode of operations of asynchronous Ethernet.
The board clock scheme of the ethernet device of typical support synchronous ethernet function realizes as shown in Figure 1, on veneer, there are active and standby two input clock sources, after one-level, secondary, stratum-3 clock processing of circuit, finally to each network control chip on veneer, provide required reference clock.
One-level clock circuit: synchronous ethernet synchronous clock source arrives the required frequency of veneer by phase-locked loop (PLL) frequency multiplication, together be input to alternative clock selecting chip with the identical local backup clock source of frequency after output frequency and PLL frequency multiplication, main control unit selects wherein Yi road clock as the clock source of veneer;
Secondary clock circuit: the clock of selecting through alternative clock selecting chip is by the clock of clock fan-out chip fan-out multichannel same frequency, to provide reference clock for network control chips all on veneer;
Stratum-3 clock circuit: the clock of fan-out is carried out level conversion processing or drive processing, finally use as offer veneer with reference to clock, to adapt to the varying level requirement of the required reference clock of diverse network control chip on veneer.
As can be seen from the above description, there is following problem in typical clock scheme:
1, the alternative clock selecting chip in one-level clock circuit cannot reach and take over seamlessly when carrying out the selection of input clock source, switching this constantly, easily cause the reference clock that offers veneer in a unsteady state, occur shake, have the risk of the fluctuation of clock performance.
2, the reference clock of being exported by clock selecting chip need pass through the output requirement of the multichannel reference clock that secondary, three grades or even more multistage clock fan-out chip or level transferring chip realize veneer, the clock chip quantity of process is many and there are differences, thereby cause each road reference clock to introduce cumulative bad difference, the consistency of each road clock is not easy to guarantee.
3, two, the introducing of stratum-3 clock chip, tend to take more veneer arrangement space.
4, the clock frequency of the clock source of local backup need to be strict consistent with the overall reference clock frequency of whole veneer, and this local backup clock source frequency is selected dumb.
To sum up, typical synchronous Ethernet clock scheme has been subject to severely restricts in performance and flexibility, is difficult to adapt to current system need of work.
Summary of the invention
The invention provides a kind of clock management method and system, solved the problem that typical synchronous Ethernet clock scheme can not adapt to current system need of work.
A clock management method, comprising:
When board clock source need to be switched, according to object clock source, PLL able to programme is configured;
After configuration, indicate described PLL able to programme to switch to described object clock source, according to this object clock source output reference clock.
Further, describedly according to this object clock source output reference clock, be specially:
According to described object clock source, export at least one road reference clock, described at least one road reference clock has one or more output levels.
Further, described need to switch in board clock source time, before step PLL able to programme being configured according to object clock source, also comprise:
From two or more available clock sources, select a clock source that priority is the highest as object clock source.
Further, above-mentioned clock management method also comprises:
When Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode;
PLL able to programme described in initialization;
In described PLL initialization success able to programme and export after effective reference clock, remove the reset mode of described Ethernet data process chip.
Further, after configuration, indicate described PLL able to programme to switch to described object clock source, after the step of this object clock source output reference clock, also comprise:
After described object clock source lost efficacy, main control unit starts timing;
At described object clock source inefficacy duration, reach the longest maintenance (Holdover) after the time, switch go back to local clock source.
The present invention also provides a kind of Clock management system, comprises main control unit and PLL able to programme;
Described main control unit, while being used for need to switching in board clock source, according to object clock source, described PLL able to programme is configured, after configuration, indicate described PLL able to programme to switch to described object clock source, according to this object clock source output reference clock;
Described PLL able to programme, for accepting the indication of described main control unit, switches to described object clock source, according to this object clock source output reference clock.
Further, described main control unit comprises central processing unit (CPU) and/or programmable logic device, and described programmable logic device is specially field programmable gate array (FPGA) or complicated Programmadle logic element (CPLD).
Further, described main control unit, also for from two or more available clock sources, selects a clock source that priority is the highest as object clock source.
Further, described main control unit, also for when the Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode, PLL able to programme described in initialization, in described PLL initialization success able to programme and export after effective reference clock, remove the reset mode of described Ethernet data process chip.
Further, described main control unit, also, for after losing efficacy at described object clock source, starts timing, reaches the longest Holdover, during the time, switch go back to local clock source at described object clock source inefficacy duration.
The invention provides a kind of clock management method and system, when board clock source need to be switched, according to object clock source, PLL able to programme is configured, after configuration, indicate PLL able to programme to switch to described object clock source, according to this object clock source output reference clock, realized balance switching, solved the problem that typical synchronous Ethernet clock scheme can not meet current system need of work.
Accompanying drawing explanation
Fig. 1 is typical board clock scheme theory diagram;
Fig. 2 is the clock circuit structural representation that embodiments of the invention are used;
The theory diagram of a kind of clock management method that Fig. 3 provides for embodiments of the invention;
Fig. 4 is for being used a kind of clock management method that embodiments of the invention provide to complete the initialized flow chart of veneer;
A kind of clock management method that Fig. 5 provides for use embodiments of the invention completes the flow chart of clock source switching.
Embodiment
There are the following problems for the clock scheme of typical synchronous ethernet:
1, the alternative clock selecting chip in one-level clock circuit cannot reach and take over seamlessly when carrying out the selection of input clock source, switching this constantly, easily cause the reference clock that offers veneer in a unsteady state, occur shake, have the risk of the fluctuation of clock performance.
2, the reference clock of being exported by clock selecting chip need pass through the output requirement of the multichannel reference clock that secondary, three grades or even more multistage clock fan-out chip or level transferring chip realize veneer, the clock chip quantity of process is many and there are differences, thereby cause each road reference clock to introduce cumulative bad difference, the consistency of each road clock is not easy to guarantee.
3, two, the introducing of stratum-3 clock chip, tend to take more veneer arrangement space.
4, the clock frequency of the clock source of local backup need to be strict consistent with the overall reference clock frequency of whole veneer, and this local backup clock source frequency is selected dumb.
In order to address the above problem, embodiments of the invention provide a kind of clock management method, by the main control unit on the PLL able to programme of multichannel input and output and veneer, the two is combined closely, and the working condition different according to veneer, realizes the management of overall reference clock.Adopt multichannel output and the PLL able to programme of multichannel output and main control unit close coordination and the control on veneer, complete that clock after Board Power up is realized and synchronous ethernet/asynchronous Ethernet mode of operation under the taking over seamlessly of clock, realize the management of overall reference clock on veneer.
The PLL able to programme that embodiments of the invention are used has following three functional characteristics:
1, PLL able to programme can realize the input in a plurality of different clocks source, and the main control unit on veneer is combined, can realize taking over seamlessly between a plurality of input clocks source, when clock source is switched, the parameter (comprising frequency, phase place and duty ratio etc.) of the reference clock of PLL output able to programme does not produce fluctuation and changes because clock source switches, thereby has reduced in typical scenario because clock source switches the unsettled risk of the unsmooth system of bringing.
2, the clock frequency of multichannel input can be optional frequency, and the incoming frequency on each road can be identical, also can be different, and the corresponding configuration by main control unit to this PLL able to programme, realizes the output of same clock frequency.Reduce the clock request in input clock source, improved the flexibility in input clock source.
3, this PLL able to programme can realize the multichannel output of the reference clock after frequency multiplication, and can export the clock of various clock level requirements, avoided in typical clock scheme the introducing of more fan-out and clock level conversion chip, the consistency that improves Liao Ge road reference clock, has also saved more veneer arrangement space.
The main control unit that embodiments of the invention are used, mainly by CPU and programmable logic device (FPGA or CPLD) in the two any one or the two combine to realize, main control unit, for whole clock scheme, is mainly used to realize following three functions:
(1) when Board Power up, PLL able to programme is carried out to initialization, and the clock source obtaining according to feedback after powering on and the state information of reference clock, coordinate to control the initialize process of whole veneer, the correct initial configuration of realization to other devices, bus and interface on veneer, finally guarantees the normal operation of veneer.
(2) when veneer normally moves, can come according to demand PLL able to programme to be configured, realize the switching under synchronous ethernet and asynchronous Ethernet mode of operation.
(3) according to the different frequency compound mode in the multichannel input clock source of PLL able to programme, PLL able to programme is carried out to programmable configuration targetedly, guarantee the in the situation that of different input clock source frequency combination, can the consistent veneer overall situation reference clock of output frequency.
Below in conjunction with accompanying drawing, embodiments of the invention are elaborated.
The clock circuit that the embodiment of the present invention is used as shown in Figure 2, mainly comprises two unit: main control unit 201 and clock unit 202.Wherein, main control unit 201 comprises again CPU2011 and programmable logic cells device 2012 (FPGA or CPLD), by the two any one or the two combined control.The control realizing board clock scheme by main control unit 201, coordinate the process of the whole power-up initializing of veneer, and switch between synchronous ethernet synchronous clock source and local backup clock source, and according to the different frequency compound mode in input clock source, PLLGe able to programme road, realize the different programmable configuration in different input clocks source, guarantee that PLL able to programme is the in the situation that of different input clock source frequency combination, can output frequency consistent veneer overall situation reference clock, thus guarantee the normal operation of veneer.
Clock unit 202 mainly comprises PLL2021 able to programme, and the Main Function of this PLL able to programme comprises:
1, this PLL able to programme can realize the input in a plurality of different clocks source, and the frequency in this input clock source can combination in any, and main control unit can carry out the programmable configuration of different parameters according to the different frequency of input to PLL able to programme.
2, can realize taking over seamlessly between a plurality of input clocks source, any road that main control unit is controlled the multichannel input clock source of switching PLL able to programme according to actual conditions is as the effective input clock of PLL able to programme source.When clock source is switched, the parameter (comprising frequency, phase place and duty ratio etc.) of the reference clock of PLL output able to programme does not produce fluctuation and changes because clock source switches.
The frequency in the two-way input clock source before and after switching is identical, and main control unit sends and orders control PLL able to programme to carry out clock switching, without the inner parameter that reconfigures again PLL able to programme, can realize taking over seamlessly of clock.
The frequency in the two-way input clock source before and after switching is different, main control unit need to be when sending switching command, the relevant parameter of PLL able to programme inside (as module parameters such as Divider, VCO) is reconfigured, guarantee that inner PLL can be operated under the clock frequency in new input clock source.
3, this PLL able to programme can realize the multichannel output of the reference clock after frequency multiplication, and can the requirement to the reference clock level of input according to heterogeneous networks managing chip, is adjusted into different clock levels.
4, this PLL able to programme has Holdover function, at input source, occur changing, when causing the inside phase-locked loop of this PLL able to programme normally frequency locking is phase-locked, within a period of time, can pass through Holdover function, realize effective output of veneer overall situation reference clock.
In addition, according to veneer to the number of channels of reference clock and clock level demand, can also be in the situation that the reference clock of PLL able to programme output cannot meet the demand when as larger in the reference clock quantity of needs output (), reference clock Zhong mono-tunnel, N road or a few road of PLL output able to programme can be connected to secondary clock chip circuit (secondary clock fan-out chip, secondary clock level conversion chip etc.), reference clock after secondary clock chip circuit conversion is offered to veneer, in clock scheme of the present invention, generally can not use stratum-3 clock fan-out chip or stratum-3 clock and drive chip.
In the embodiment of the present invention, by main control unit 201 and the mutual cooperation of clock unit 202, a kind of clock management method is provided, its schematic diagram block diagram is as shown in Figure 3, except the clock circuit shown in Fig. 2, also comprise other devices of veneer, interface, bus 203 and Ethernet data process chip 204.
Main control unit 201 mainly comprises CPU2011 and CPLD/FPGA2022 any one or the two the combination in the two, and 201 pairs of whole veneers of main control unit carry out initialization and configuration, and according to the situation of actual veneer, coordinate initialized process.For CPU2011 and CPLD/FPGA2022, the two combination realizes for the mode of main control unit, realizes the read-write communication of data between CPU2011 and CPLD/FPGA2022 by bus interface.
The core of clock unit is PLL2021 able to programme, for realizing taking over seamlessly of synchronous ethernet synchronous clock source and backup clock source, for whole veneer provides reference clock.
The initial configuration object that other devices of veneer, interface, bus 203 and Ethernet data process chip 204 are whole veneer, main control unit is coordinated the initialize process to other devices of veneer, interface, bus 203 and MAC and PHY chip 204, guarantee the correct initialization of veneer, guarantee that veneer normally moves.
Below in conjunction with accompanying drawing, the flow process that the clock management method that uses embodiments of the invention to provide is realized to Clock management is elaborated.
Idiographic flow as shown in Figure 4, comprising:
Step 401, Board Power up, without external synchronous ethernet synchronous clock source in the situation that, whole veneer only has local backup clock source available, as effective input clock source of PLL able to programme.
Each output pin of PLL able to programme is connected from the different chips on veneer respectively, for each chip provides its needed reference clock.
Veneer now just power supply is normal, but because reference clock is produced by PLL able to programme, not yet PLL able to programme is carried out to initialization, and therefore whole veneer does not have reference clock, and each chip on veneer is in an abnormal running state.
Step 402, CPU, interface, bus are carried out to initialization;
Step 403, when Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode, described Ethernet data process chip is specially MAC and PHY chip;
In this step, by main control unit (CPU, FPGA or CPLD), enable MAC chip and the PHY chip reset signal on veneer, because the chip (being mainly MAC chip and PHY chip) on veneer is now in an abnormal running state, in order to prevent that chip operation lost efficacy, need to allow chip before entering normal operating condition, long-time hold reset state.
Before completing steps 408, make MAC chip and PHY chip hold reset state always.In the embodiment of the present invention, after veneer just powers on, not directly for each chip on veneer provides reference clock, and MAC chip and PHY chip in the situation that inputting without clock, work can cause abnormal, therefore in this step, MAC chip and PHY chip are placed in to reset mode, it wouldn't be started working, to guarantee that subsequent configuration can complete smoothly.
Step 402 is carried out with step 403 is parallel.
PLL able to programme described in step 404, main control unit initialization;
In this step, PLL able to programme is carried out to initialization, during due to Board Power up, only having local clock source is effective input clock source of PLL able to programme, therefore when PLL initialization able to programme, need to PLL able to programme, carry out corresponding parameter configuration according to the frequency in local clock source, mainly comprise: according to the frequency in local clock source, the VCO parameter of PLL able to programme is configured; Frequency division parameter to PLL able to programme inside is configured; Clock level and passage to PLL output able to programme are configured; Holdover function is configured and is enabled etc.
In this step, main control unit carries out initialization to PLL able to programme, and the control program of this PLL able to programme is loaded on this PLL able to programme.The control program of PLL able to programme can be set according to actual needs, corresponding program is input to main control unit or corresponding program is stored in the memory cell such as FLASH, main control unit calls out from memory cell again, then by main control unit, is completed the loading of program.
Step 405, configurating programmable PLL are usingd local backup clock source as input clock source, by main control unit, issued an order, PLL able to programme is switched to the input of valid clock source on local clock source, now, PLL able to programme starts working, this clock source is carried out to frequency multiplication, and export the needed reference clock of veneer;
In this step, the input in the parameter configuration of PLL integrating step 404 able to programme and local clock source starts normal work, and PLL able to programme carries out frequency locking and phase-locked to the clock source of input, and frequency multiplication is to the desired high-frequency clock CLK of main control unit
high, PLL able to programme is the parameter to its configuration according to main control unit, by this high frequency clock CLK
highcarry out frequency division, frequency division is to the required frequency of veneer reference clock, and is finally converted to corresponding level formal output to whole veneer.
Step 406, judge whether PLL able to programme has exported effective reference clock;
When input clock being carried out to frequency locking when phase-locked, if the phase place of clock and frequency are pinned, represent lock, now the effective clock of PLL able to programme; Otherwise be unlock, now output clock is invalid, PLL able to programme can start Holdover function, guarantees the frequency of clock output and the state consistency of previous lock.
But for the situation of Board Power up, do not carry out initialization while just having powered on due to PLL able to programme, cannot normally work, there is no the state of said previous lock above, therefore if there is unlock state, Holdover function cannot normally be worked.
If be now still unlock state after certain hour is waited in time delay, PLL able to programme cannot export efficient clock, must re-start initial configuration to PLL able to programme.
Lock state if, effective reference clock output, jumps to step 407.
Step 407, after described PLL initialization able to programme success, remove the reset mode of described MAC and PHY chip;
In this step, main control unit carries out after certain time-delay finishing the reset of MAC chip and PHY chip to control.
Step 408, main control unit carry out initialization operation to Ethernet data process chip (being MAC chip and PHY chip).
Step 409, whether initialization is complete to judge CPU, interface, bus; If do not completed, continued corresponding initial work.
Step 410, whether initialization is complete to judge MAC chip and PHY chip; If do not completed, continued corresponding initial work.
Whether the corresponding initialization of step 411, determining step 409 and step 410 all completes; If had, continue to wait for.If all completed, veneer now can normally be worked, and operates under the mode of operation of asynchronous Ethernet.
So far, the initialized process of device power finishes.
In the equipment course of work, while being switched to object clock source by present clock source, need to the configuration of PLL able to programme, adjust according to the frequency in object clock source and present clock source etc., to realize, take over seamlessly, concrete steps as shown in Figure 5, comprising:
Step 501, judge whether available synchronous clock source;
If there is no available synchronous clock source, veneer remains running under the mode of operation of asynchronous Ethernet; If there is available synchronous clock source,, using this synchronous clock source as object clock source, jump to step 502.
If there are a plurality of available clock sources, by user, specified the priority of each clock source, or by main control unit, according to certain rule, determined the priority (as the order according to clock source being detected) of each clock source, then main control unit is according to the clock source priority of user or main control unit formulation, using the highest clock source of available clock source medium priority as object clock source, jump to step 502.
Step 502, judge that whether this object clock source is identical with local clock source frequency;
If identical, jump to step 503; If frequency is not identical, jump to step 504.
Step 503, because the frequency of object clock source is identical with the frequency in local clock source, the relevant parameter of PLL able to programme inside is without changing, by main control unit, controlled, directly effective input clock source of PLL able to programme is switched on synchronous clock source, now, veneer operates under synchronous ethernet mode of operation, and jumps to step 506;
Step 504, need to switch in board clock source time, according to object clock source, be configured;
In this step, because the frequency of object clock source is different from the frequency in local clock source, main control unit need to be adjusted the relevant parameter of PLL able to programme according to the frequency of synchronisation source.
Step 505, after configuration, indicate PLL able to programme to switch to described object clock source, according to this object clock source output reference clock;
In this step, main control unit is switched to the present clock source of effective input of PLL able to programme (being local clock source) on object clock source.
Step 506, judge whether object clock source lost efficacy;
If effectively, jump to step 507; If lost efficacy, jumped to step 508.
Step 507, because veneer has operated in (being application target clock source) under synchronous ethernet pattern, main control unit is left intact, and continues to operate under this pattern, and rebound step 506;
Step 508, owing to there is no synchronous clock source, now PLL able to programme enters Holdover function, main control unit starts timing;
Step 509, at main control unit, start after timing, judged whether to surpass the maintenance Holdover maximum duration of predetermining;
If do not have overtimely, continue to keep Holdover function, wait for the appearance of effective object synchronous clock source; If overtime, jump to step 510.
Step 510, when keeping the time of Holdover function to exceed that predetermined the longest Handover is during the time, in order to guarantee the normal work of clock accuracy and veneer, main control unit need to switch back to effective input clock source of PLL able to programme on local clock source.
If local clock source is identical with previous synchronised clock source frequency, main control unit is directly controlled the switching that PLL able to programme completes valid clock source;
If local clock source is different from previous synchronised clock source frequency, main control unit needs to reconfigure PLL relevant parameter able to programme, and completes the switching of valid clock source.
Complete after switching, enter asynchronous Ethernet mode of operation.Now, jump to step 501.
It should be noted that, in step 501 and step 506, judge whether clock source effectively can be realized with losing efficacy by the following method:
(1) when synchronous clock source is effective or lost efficacy, provide the equipment of this synchronous clock source to report an interrupt signal to main control unit, to inform the state variation of this synchronous clock source of main control unit; Or main control unit is just accessed on the equipment that this synchronous clock source is provided by the mode of poll, about the register of this clock status.
(2) by PLL able to programme, monitored the state in each output clock source, road, main control unit can pass through this mode bit of poll PLL able to programme at the state of determining clock source; Or PLL able to programme is set to the pattern that interruption reports, once state variation effective or that lost efficacy appears in the clock source of input, to main control unit reporting interruption signal.
Embodiments of the invention provide a kind of clock management method, when board clock source need to be switched, according to object clock source, be configured, after configuration, indicate PLL able to programme to switch to described object clock source, according to this object clock source output reference clock, realized balance switching, solved the problem that typical synchronous Ethernet clock scheme can not meet current system need of work.PLL able to programme can realize the input in a plurality of different clocks source, and can realize taking over seamlessly between a plurality of input clocks source, when clock source is switched, the parameter (comprising frequency, phase place and duty ratio etc.) of the reference clock of PLL output able to programme does not produce fluctuation and changes because clock source switches, thereby has reduced in typical scenario because clock source switches the unsettled risk of the unsmooth system of bringing.
This PLL able to programme can, according to level requirement, realize the multichannel output of the reference clock after frequency multiplication.Avoid in typical clock scheme the introducing of more fan-out and clock chip, improved the consistency of Liao Ge road reference clock, also saved more veneer arrangement space.
When Board Power up, main control unit carries out initialization to PLL able to programme, and the clock source obtaining according to feedback after powering on and the state information of reference clock, coordinate to control the initialize process of whole veneer, the correct initial configuration of realization to other devices, bus and interface on veneer, finally guarantees the normal operation of veneer.
When veneer normally moves, can come according to demand PLL able to programme to be configured, realize the switching under synchronous ethernet and asynchronous Ethernet mode of operation.
Embodiments of the invention also provide a kind of Clock management system, comprise main control unit and PLL able to programme;
Described main control unit, while being used for need to switching in board clock source, according to object clock source, described PLL able to programme is configured, after configuration, indicate described PLL able to programme to switch to described object clock source, according to this object clock source output reference clock;
Described PLL able to programme, for accepting the indication of described main control unit, switches to described object clock source, according to this object clock source output reference clock.
Further, described main control unit comprises CPU and/or programmable logic device, and described programmable logic device is specially FPGA or CPLD.
Further, described main control unit, also for from two or more available clock sources, selects a clock source that priority is the highest as object clock source.
Further, described main control unit, also for when the Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode, PLL able to programme described in initialization, in described PLL initialization success able to programme and export after effective reference clock, remove the reset mode of described Ethernet data process chip.
Further, described main control unit, also, for after losing efficacy at described object clock source, starts timing, reaches the longest Holdover, after the time, switch go back to local clock source at described object clock source inefficacy duration.
Above-mentioned Clock management system, a kind of clock management method that can provide with embodiments of the invention combines, when board clock source need to be switched, according to object clock source, be configured, after configuration, indicate PLL able to programme to switch to described object clock source, according to this object clock source output reference clock, realize balance switching, solved the problem that typical synchronous Ethernet clock scheme can not meet current system need of work.
The all or part of step that one of ordinary skill in the art will appreciate that above-described embodiment can realize by computer program flow process, described computer program can be stored in a computer-readable recording medium, described computer program (as system, unit, device etc.) on corresponding hardware platform is carried out, when carrying out, comprise step of embodiment of the method one or a combination set of.
Alternatively, all or part of step of above-described embodiment also can realize with integrated circuit, and these steps can be made into respectively integrated circuit modules one by one, or a plurality of modules in them or step are made into single integrated circuit module realize.Like this, the present invention is not restricted to any specific hardware and software combination.
Each device/functional module/functional unit in above-described embodiment can adopt general calculation element to realize, and they can concentrate on single calculation element, also can be distributed on the network that a plurality of calculation elements form.
The form of software function module of usining each device/functional module/functional unit in above-described embodiment realizes and during as production marketing independently or use, can be stored in a computer read/write memory medium.The above-mentioned computer read/write memory medium of mentioning can be read-only memory, disk or CD etc.
Claims (6)
1. a clock management method, is characterized in that, comprising:
When board clock source need to be switched, according to object clock source, programmable phase-locked loop (PLL) is configured;
After configuration, indicate described PLL able to programme to switch to described object clock source, according to this object clock source output reference clock;
When Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode;
PLL able to programme described in initialization;
In described PLL initialization success able to programme and export after effective reference clock, remove the reset mode of described Ethernet data process chip;
After configuration, indicate described PLL able to programme to switch to described object clock source, after the step of this object clock source output reference clock, also comprise:
After described object clock source lost efficacy, main control unit starts timing;
At described object clock source inefficacy duration, reach the longest maintenance (Holdover) after the time, switch go back to local clock source.
2. clock management method according to claim 1, is characterized in that, describedly according to this object clock source output reference clock, is specially:
According to described object clock source, export at least one road reference clock, described at least one road reference clock has one or more output levels.
3. clock management method according to claim 1, is characterized in that, described need to switch in board clock source time, before step PLL able to programme being configured according to object clock source, also comprises:
From two or more available clock sources, select a clock source that priority is the highest as object clock source.
4. a Clock management system, is characterized in that, comprises main control unit and PLL able to programme;
Described main control unit, while being used for need to switching in board clock source, according to object clock source, described PLL able to programme is configured, after configuration, indicate described PLL able to programme to switch to described object clock source, according to this object clock source output reference clock;
Described PLL able to programme, for accepting the indication of described main control unit, switches to described object clock source, according to this object clock source output reference clock;
Described main control unit, also for when the Board Power up initialization, the Ethernet data process chip of described veneer is placed in to reset mode, PLL able to programme described in initialization, in described PLL initialization success able to programme and export after effective reference clock, remove the reset mode of described Ethernet data process chip;
Described main control unit, also, for after losing efficacy at described object clock source, starts timing, reaches the longest Holdover, during the time, switch go back to local clock source at described object clock source inefficacy duration.
5. Clock management system according to claim 4, it is characterized in that, described main control unit comprises central processing unit (CPU) and/or programmable logic device, and described programmable logic device is specially field programmable gate array (FPGA) or complicated Programmadle logic element (CPLD).
6. Clock management system according to claim 4, is characterized in that,
Described main control unit, also for from two or more available clock sources, selects a clock source that priority is the highest as object clock source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN102591404A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Switching method of SoC (system on chip) system dynamic clock |
| CN102857222B (en) * | 2012-07-03 | 2015-09-16 | 山东华芯半导体有限公司 | A kind of dynamic adjusting method of system clock and circuit |
| US9471537B2 (en) | 2013-03-14 | 2016-10-18 | Altera Corporation | Hybrid programmable many-core device with on-chip interconnect |
| CN103412615B (en) * | 2013-08-22 | 2018-02-09 | 中国航天科工集团第三研究院第八三五七研究所 | A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip |
| CN106160908B (en) * | 2015-04-23 | 2018-09-11 | 深圳市恒扬数据股份有限公司 | Two rank programmatic telecommunication grade clock tree circuits |
| CN106155973B (en) * | 2016-07-26 | 2019-04-02 | 中国科学院上海应用物理研究所 | The digital low control processor of energy flexible configuration clock frequency |
| CN109857191A (en) * | 2019-01-31 | 2019-06-07 | 郑州云海信息技术有限公司 | A kind of redundancy clock plate and server that frequency is controllable |
| CN112445269B (en) * | 2020-11-02 | 2024-04-09 | 鹏城实验室 | Clock switching method, complex programmable logic device and FPGA board card |
| CN113904748A (en) * | 2021-09-24 | 2022-01-07 | 济南浪潮数据技术有限公司 | Clock synchronization method, system, device and medium |
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| DE102004062210B3 (en) * | 2004-12-23 | 2006-05-24 | Texas Instruments Deutschland Gmbh | Controller area network communication module for motor vehicle, has protocol kernel with clock signal having small frequency jitter, and logic block having message handler and supplied with clock signal having modulated clock frequency |
| CN1953332B (en) * | 2005-10-17 | 2011-01-12 | 联芯科技有限公司 | Clock generator and communication terminal using the same |
| US8526559B2 (en) * | 2008-05-30 | 2013-09-03 | Mediatek Inc. | Communication systems and clock generation circuits thereof with reference source switching |
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