CN100571114C - A kind of synchronised clock providing device and implementation method - Google Patents
A kind of synchronised clock providing device and implementation method Download PDFInfo
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Abstract
A kind of synchronised clock providing device comprises primary and backup unit, and each unit comprises the E1/T1 LIU link interface unit, and the interface with outside BITS/SSU is provided, and possesses the SSM information extraction and inserts function, exports synchronous refernce clocks and SSM message simultaneously; Digital phase-locked loop and local crystal oscillator are used for to the monitoring of the signal quality of input reference clock, to the tracking lock of selected reference clock source, and the generation of output clock frequency; Microprocessor is used for control and management to this master usefulness/stand-by unit; Distribute and driver module, be used for distribution and driving the output clock.The synchronization solutions that the invention provides a kind of complete function, possess synchronous chain extended attribute, precision satisfies and surpass Stratum-4/4E and Stratum-3 corresponding requirements, with its low cost, simple compact structure and the perfect active and standby switching capability of using, can be widely used in the telecommunication apparatus such as TDM far-end crosspoint or IAD.This scheme is relatively independent, can be used as circuit module or daughter board and combines with the master control borad circuit of device systems, and applying flexible perhaps is provided regularly as independent system board.
Description
Technical field
The present invention relates to a kind of synchronised clock providing device and implementation method that is applicable to far-end crosspoint, IAD and low capacity end office (EO).
Technical background
In digital communication network, the signal that transmits and exchange is that information is carried out bit stream coded, thereby has a specific transmission bit rate, if require the various digital devices on the communication network can both carry out exchanges data like clockwork each other, just need various numerals in the net to send out the clock signal that is equipped with (or network element) and handle bit stream with identical phase place, the stationary problem of Here it is digital communication network with identical frequency.
For among the ZL 99127042.8 a kind of synchronised clock providing device is disclosed at Chinese invention patent number, as shown in Figure 1, this synchronised clock providing device comprises primary and backup two modules that are operated under the Hot Spare state, each module comprise input clock processing unit 1 ', phase locking unit 3 ', CPU 2 ', output clock processing unit 6 ', memory cell 5 ' and communication unit 4 '.Output clock processing unit 6 ' adopt delay line technique to reduce phase hit.
Clock signal and other state information of above-mentioned primary and backup two modules by self producing alternately each other, thereby guaranteed the reliability of clock signal, each module can correctly be determined self active and standby state of using independently according to oneself state and matching module state simultaneously, to have strengthened the maintainability of device.It both can be used for the synchronization node in the communication network, also can be used for independent digital device, made between the online various digital devices of digital communication to carry out exchanges data mutually like clockwork.But there is following point in it:
1) causes complex interfaces cutting apart of each Elementary Function, for example: the processing of input clock will be with reference to the feedback from phase locking unit, result will be delivered to the CPU judge, produce relevant information according to result of determination again and give the input clock processing unit, select one road reference clock, be fed to the phase locking unit tracking lock at last.Like this, the signal kinds of each unit interface and quantity are all a lot, cause the structure of device and control too complicated.This shortcoming makes this invention independently to provide, and its expansion and transfer ability are poor, are difficult to be integrated in other the product;
2) set up from its function, this device device utilization quantity is very big, and cost is higher.
3) can only receive the reference clock signal of 2.048MHz or 8KHz, E1 or T1 synchronization link interface are not provided, can't receive and extract SSM (Synchronication status message) message that is inserted in the E1/T1 bit stream, so reception and the transmitting capacity of SSM can not be provided, also i.e. this design can only be when being subjected to synchronously equipment, the state information of clock synchronization chain can not be provided to other equipment:
4) although the output clock processing unit of above-mentioned synchronised clock providing device adopts delay line technique to reduce phase hit, can't thoroughly eliminate the phase hit problem of output clock when still having active and standby the switching.
Summary of the invention
In order to overcome the defective of above-mentioned prior art, the present invention aims to provide a kind of structure and simple synchronised clock providing device of control and implementation method, realizes demand cheaply when satisfying high accuracy, high reliability.
A kind of synchronised clock providing device provided by the present invention, comprise primary and backup two unit, it is characterized in that: each unit comprises digital phase-locked loop, coupled local crystal oscillator, E1/T1 LIU link interface unit, distribution and driver module and the microprocessor of difference, this microprocessor also links to each other with described E1/T1 LIU link interface unit, and: main two microprocessors with unit and stand-by unit interconnect, and two digital phase-locked loop output crossfeed to digital phase-locked loops of opposite end are imported; Wherein: the E1/T1 LIU link interface unit, the interface with outside BITS/SSU is provided, possess the SSM information extraction and insert function, export synchronous refernce clocks and SSM message simultaneously; Digital phase-locked loop and local crystal oscillator are used for to the monitoring of the signal quality of input reference clock, to the tracking lock of selected reference clock source, and the generation of output clock frequency; Microprocessor is used for described digital phase-locked loop, LIU link interface unit are carried out parameter setting, operation control and management, and the main switching controls of using with stand-by unit, and with another microprocessor interaction mode and control information; Distribute and driver module, be used for distribution and driving the output clock.
In above-mentioned synchronised clock providing device, microprocessor comprises initial condition setting, running state monitoring to the parameter setting and the operation control of digital phase-locked loop, and the alarming processing of reference clock quality decline, extraction and the insertion that comprises initial parameter setting, loss of signal alarm processing, SSM message controlled in the parameter setting and the operation of described LIU link interface unit.
In above-mentioned synchronised clock providing device, the master is lower than the cut-off frequency of the pll low pass filter of stand-by unit with the cut-off frequency of the pll low pass filter of unit.
In above-mentioned synchronised clock providing device, digital phase-locked loop and local crystal oscillator adopt compatible other phase-locked loop of different accuracy level of energy and crystal oscillator to assemble encapsulation.
In above-mentioned synchronised clock providing device, the main units synchronization of using is in the external reference clock, and stand-by unit is synchronized with the main output clock of using the digital phase-locked loop of unit.
In above-mentioned synchronised clock providing device, lead when microprocessor control and to use when switching with stand-by unit, the microprocessor of stand-by unit will be configured to main microprocessor parameter setting with the unit, and the main microprocessor parameter setting that will be configured to stand-by unit with the microprocessor of unit.
The present invention also provides a kind of implementation method of synchronised clock, is undertaken by main using with the changeable mode of stand-by unit, comprises the following steps: 1) the parameter step is set: system parameters is provided with; 2) extract also recovered clock step: E1 or T1 synchronous digital link signal to outside BITS/SSU presents, therefrom extract and the recovered clock waveform, the reference clock as input extracts SSM message simultaneously; 3) tracking lock step: to multichannel External Reference clock, select a tunnel to carry out tracking lock, generate the clock signal of multichannel Phase synchronization in selected reference clock according to preestablishing; General's road output clock wherein is fed to end unit is imported as one road reference clock simultaneously; 4) monitoring step: the quality of monitoring reference clock, when the clock quality dropped to threshold value, the generation alarm signal also reported, and stops simultaneously with reference to this road clock, and carries out tracking lock according to the other reference clock of predefined selective sequential; 5) produce step: according to the reference clock of current selected, in conjunction with from step 2) the SSM message of extraction, produce new SSM message; 6) distribute, drive and the output step: distribute and actuation step 3) in the clock signal that generates to the time receiving unit of system, and by LIU link interface unit to outside output synchronous refernce clocks signal, and the SSM message that from step 5), generates.
In the step 1) of the implementation method of above-mentioned synchronised clock, system parameter setting comprises initial condition setting, the setting of reference clock quality gate limit value, and main setting with, stand-by unit switching condition.
In the step 4) of the implementation method of above-mentioned synchronised clock, when the reference clock of alarm recover normal after, remove alarm, as standby reference clock source.
In the implementation method of above-mentioned synchronised clock, to use when switching when main with stand-by unit, stand-by unit will be configured to main with the parameter setting under the unit, will be configured to parameter setting under the stand-by unit and lead with the unit.
In the implementation method of above-mentioned synchronised clock, the main units synchronization of using is in the external reference clock, and stand-by unit is synchronized with main output clock with the unit.
Owing to adopted above-mentioned technical solution, the present invention has following advantage:
1) same hardware platform possesses general precision to the high-precision ability of seamlessly transitting, and can specifically dispose rank according to equipment and determine the precision configuration;
2) leading the digital phase-locked loop low pass filter cut-off frequency of usefulness/stand-by unit can software setting, realizes that main, stand-by unit stable with the unit catch fast;
3) switching of leading usefulness/stand-by unit is seamless, the phase hit problem when eliminating master/backup clock and switching, thus system works is stable when guaranteeing that clock switches;
4) reception, processing and the transmitting capacity of SSM information have been increased, can know the synchronous topology chain information that the External Reference clock is experienced when arriving local system from the SSM message that receives, then according to the position of local system, produce the SSM message of upgrading, export the equipment of next stage to, thereby strengthen the robustness and the cascade extended capability of whole synchronizing network;
5) structure and control are simple, and function is independent, can realize flexibly or integrated, realize low-costly when satisfying high accuracy, high reliability, are applicable to far-end crosspoint, IAD and low capacity end office (EO).
Description of drawings
Fig. 1 is the structural representation of existing synchronised clock providing device;
Fig. 2 is the structural representation of synchronised clock providing device of the present invention.
Embodiment
One of the present invention: synchronised clock providing device
As shown in Figure 2, the present invention, it is synchronised clock providing device, comprise primary and backup two unit, local crystal oscillator 2, E1/T1 LIU link interface unit 3, distribution and driver module 4 and microprocessor 5 that this master uses, stand-by unit includes digital phase-locked loop 1, difference is coupled, this microprocessor 5 also links to each other with LIU link interface unit 3, and: two digital phase-locked loop 1,1 ' output crossfeed to the digital phase-locked loop 1 of opposite end ', 1 input; Two microprocessors 5,5 ' interconnect.
Digital phase-locked loop 1 and local crystal oscillator 2 adopt existing commercial integrated digital phase-locked loop (DPLL) and crystal oscillator to form phase-locked functional module, are used for the tracking lock of external reference clock, and produce phase locked clock output.The monitoring and the selection function of reference clock that DPLL is integrated, the signal quality of the input reference clock of energy monitoring maximum four tunnel, when a certain road just when the input clock generation quality of tracking lock descends, can produce alarm, simultaneously according to another road of selective sequential of setting as new reference source.The quality decline of arbitrary reference source all can produce alarm and report.Local crystal oscillator is the work clock as DPLL, and when all External Reference clocks were all lost, DPLL can be operated in hold-over (maintenance) pattern or free-run mode, and the precision of the clock of device output at this moment then depends on the precision of local crystal oscillator.Under normal mode of operation, DPLL follows the tracks of in a certain External Reference clock like this, generates the output clock that meets Stratum-4/4E (level Four and level Four strengthen clock) or Stratum-3 (three grades of clocks) precision grade; And under hold-over or free-run mode, guarantee that by the local crystal oscillator that meets Stratum-4/4E or Stratum-3 precision grade the output clock of DPLL satisfies corresponding required precision.The design's a main thought is phase-locked loop and the local crystal oscillator of same hardware platform by the compatible different accuracy grade of encapsulation, can make same device that different precision grades is provided, be applied to corresponding occasion, the three grade clocks high as required precision, or require lower level Four or level Four to strengthen clock.Also promptly, under the current techniques condition, same package and different DPLL and the local crystal oscillators of precision can be chosen easily.Like this, the present invention is on same hardware designs, and the DPLL and the local crystal oscillator of assembling different accuracy just can provide different precision grades in different application scenarios.
The E1/T1 LIU link interface unit is used for receiving outside from BITS/SSU (building is comprehensive, and unit, unit/provide synchronously regularly is provided) 2.048Mbps of equipment or the synchronization link signal of 1.544Mbps.What design was adopted is special-purpose E1/T1 LIU link interface unit, and for example: the DS2155 interface chip of Maxim company, inside are integrated with the extraction of SSM message and insert function, make things convenient for microprocessor reading and writing SSM message.Like this, the present invention can be via this LIU link interface unit, read the SSM message that is embedded in the E1/T1 bit stream by microprocessor, thereby know the topology information of synchro system, before this equipment of arrival, passed through which synchronous approach as this reference clock, or the like, then according to the position of local system, produce new SSM message,, be fed to the outside with the output reference clock by this LIU link interface unit.Synchronizing function when the present invention not only possesses traditional being subjected to so also has both the function of synchronous driving equipment, can effectively expand the scope of synchro system, and strengthen the availability and the stability of existing synchro system.
Distribute and driver module 4, the driving of output clock distributes.By meeting the difference transmission lines of RS-422 standard, drive the time receiving unit 6 of output clock to system.
The present invention is based on main usefulness/standby framework, the master is fed to the other side's digital phase-locked loop reference clock input respectively with the clock output of the digital phase-locked loop of unit and stand-by unit, utilize the input signal monitoring function of digital phase-locked loop, automatically realize monitoring, improved the reliability of system the stand-by unit digital phase-locked loop.The down main phase-locked loop tracking lock with the unit of normal operating condition is to external reference clock, and stand-by unit is followed the tracks of and is synchronized with main input with the unit phase-locked loop, and the master is synchronized with the External Reference clock with, stand-by unit like this.When main with Elementary Function unusual or software according to the default needs lead usefulness, when stand-by unit switches; because phase-locked loop possesses memory function; although at this moment main output clock with the unit lost efficacy; but the output of stand-by unit phase-locked loop still is synchronized with master before the inefficacy that it remembers with on the unit output clock, leads the smooth and seamless of usefulness/standby switching like this.The software setting stand-by unit is main during switching, is synchronized with the External Reference clock, will lead with the unit and be made as stand-by unit, is synchronized with the phase-locked loop output clock of former stand-by unit.
The master uses, the cut-off frequency software set of the low pass filter of the DPLL of stand-by unit is main narrow with the unit, and stand-by unit is wide, and the main like this DPLL working stability of using the unit is not subject to the influence that the External Reference clock happens suddenly and jumps mutually; Stand-by unit then capturing ability is stronger, and the tracking lock master uses the output clock of unit phase-locked loop better.
The present invention design simple and compact for structure can be used as independently timing unit (veneer) and uses, and also can be integrated in the master control veneer of redundancy backup of equipment such as far-end crosspoint, IAD applying flexible.
The present invention's two: synchronised clock implementation method
A kind of implementation method of synchronised clock is undertaken by main using with standby switchable unit, comprises the following steps:
1) the parameter step is set: system parameters is provided with, comprises initial condition setting, the setting of reference clock quality gate limit value, and the master uses, the setting of stand-by unit switching condition;
2) extract also recovered clock step: E1 or T1 synchronous digital link signal to outside BITS/SSU presents, therefrom extract and the recovered clock waveform, the reference clock as input extracts SSM message simultaneously;
3) tracking lock step: to multichannel External Reference clock, select a tunnel to carry out tracking lock, generate the clock signal of multichannel Phase synchronization in selected reference clock according to preestablishing; General's road output clock wherein is fed to end unit is imported as one road reference clock simultaneously;
4) monitoring step: the quality of monitoring reference clock, when the clock quality dropped to threshold value, the generation alarm signal also reported, and stops simultaneously with reference to this road clock, and carries out tracking lock according to the other reference clock of predefined selective sequential; After the reference clock of alarm recovers normally, remove alarm, as standby reference clock source.
5) produce step: according to the reference clock of current selected, in conjunction with from step 2) the SSM message of extraction, produce new SSM message;
6) distribute, drive and the output step: distribute and actuation step 3) in the clock signal that generates to the time receiving unit of system, and by LIU link interface unit to outside output synchronous refernce clocks signal, and the SSM message that from step 5), generates.
The main units synchronization of using is in the external reference clock, and stand-by unit is synchronized with main output clock with the unit.
Break down or system when specific demand is arranged with the unit when main, control is main switches with, stand-by unit, at this moment original stand-by unit will be configured to main with the parameter setting under the unit, and original master will be configured to parameter under the stand-by unit with the unit, or under situation about breaking down, safeguard processing accordingly by system.
In sum, the invention provides that a kind of cost is low, complete function, possess synchronous chain extended attribute, precision satisfies and surpass synchronously and the regularly solution of Stratum-4/4E and Stratum-3 corresponding requirements, than expensive and local side apparatus time block labyrinth, this scheme can be widely used in TDM far-end crosspoint, IAD or other telecommunication apparatus with its low cost, simple compact structure and active and standby part of perfect switching capability.This scheme is relatively independent, can be used as circuit module or daughter board and combines with the master control borad circuit of device systems, and applying flexible perhaps is provided regularly as independent system board.
More than all embodiment only for the explanation the present invention usefulness, but not limitation of the present invention, person skilled in the relevant technique, under the situation that does not break away from the spirit and scope of the present invention, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong within the category of the present invention, should be limited by each claim.And include within the scope of claim.
Claims (11)
1. synchronised clock providing device, comprise primary and backup two unit, it is characterized in that: each unit comprises digital phase-locked loop, coupled local crystal oscillator, E1/T1 LIU link interface unit, distribution and driver module and the microprocessor of difference, this microprocessor also links to each other with described E1/T1 LIU link interface unit, and: main two microprocessors with unit and stand-by unit interconnect, and two digital phase-locked loop output crossfeed to digital phase-locked loops of opposite end are imported; Wherein:
The E1/T1 LIU link interface unit provides and the comprehensive unit/interface of unit B ITS/SSU is provided synchronously of regularly providing, outside building, possesses Synchronication status message SSM information extraction and inserts function, exports synchronous refernce clocks and SSM message simultaneously;
Digital phase-locked loop and local crystal oscillator are used for to the monitoring of the signal quality of input reference clock, to the tracking lock of selected reference clock source, and the generation of output clock frequency;
Microprocessor is used for described digital phase-locked loop, LIU link interface unit are carried out parameter setting, operation control and management, and the main switching controls of using with stand-by unit, and with another microprocessor interaction mode and control information;
Distribute and driver module, be used for distribution and driving the output clock.
2. synchronised clock providing device according to claim 1, it is characterized in that: described microprocessor comprises initial condition setting, running state monitoring to the parameter setting and the operation control of described digital phase-locked loop, and the alarming processing of reference clock quality decline, extraction and the insertion that comprises initial parameter setting, loss of signal alarm processing, SSM message controlled in the parameter setting and the operation of described LIU link interface unit.
3. synchronised clock providing device according to claim 1 and 2 is characterized in that: the cut-off frequency of the low pass filter of described main phase-locked loop with the unit is lower than the cut-off frequency of low pass filter of the phase-locked loop of stand-by unit.
4. synchronised clock providing device according to claim 1 and 2 is characterized in that: described digital phase-locked loop and local crystal oscillator adopt compatible other phase-locked loop of different accuracy level of energy and crystal oscillator to assemble encapsulation.
5. synchronised clock providing device according to claim 1 is characterized in that: the described main units synchronization of using is in the external reference clock, and stand-by unit is synchronized with the main output clock of using the digital phase-locked loop of unit.
6. synchronised clock providing device according to claim 1, it is characterized in that: lead when the control of described microprocessor and use when switching with stand-by unit, the microprocessor of stand-by unit will be configured to main microprocessor parameter setting with the unit, and the main microprocessor parameter setting that will be configured to stand-by unit with the microprocessor of unit.
7. the implementation method of a synchronised clock is undertaken by main using with the changeable mode of stand-by unit, comprises the following steps:
1) the parameter step is set: system parameters is provided with;
2) extract and the recovered clock step: comprehensive E1 or the T1 synchronous digital link signal that unit/provide unit B ITS/SSU to present synchronously regularly is provided in outside building is provided, therefrom extract and the recovered clock waveform, reference clock as input extracts Synchronication status message SSM message simultaneously;
3) tracking lock step: to multichannel External Reference clock, select a tunnel to carry out tracking lock, generate the clock signal of multichannel Phase synchronization in selected reference clock according to preestablishing; General's road clock signal wherein is fed to end unit is imported as one road reference clock simultaneously;
4) monitoring step: the quality of monitoring reference clock, when the clock quality dropped to threshold value, the generation alarm signal also reported, and stops simultaneously with reference to this road clock, and carries out tracking lock according to the other reference clock of predefined selective sequential;
5) produce step: according to the reference clock of current selected, in conjunction with from step 2) the SSM message of extraction, produce new SSM message;
6) distribute, drive and the output step: distribute and actuation step 3) in the clock signal that generates to the time receiving unit of system, and by LIU link interface unit to outside output synchronous refernce clocks signal, and the SSM message that from step 5), generates.
8. the implementation method of synchronised clock according to claim 7, it is characterized in that: the system parameter setting in the step 1) comprises initial condition setting, the setting of reference clock quality gate limit value, and main setting with, stand-by unit switching condition.
9. the implementation method of synchronised clock according to claim 7 is characterized in that: in the described step 4), after the reference clock of alarm recovers normally, remove alarm, as standby reference clock source.
10. the implementation method of synchronised clock according to claim 7 is characterized in that: use when switching with stand-by unit when main, stand-by unit will be configured to main with the parameter setting under the unit, will be configured to parameter setting under the stand-by unit and lead with the unit.
11. the implementation method of synchronised clock according to claim 7 is characterized in that: the described main units synchronization of using is in the external reference clock, and stand-by unit is synchronized with main output clock with the unit.
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| CN101247573B (en) * | 2007-02-16 | 2011-06-15 | 大唐移动通信设备有限公司 | Clock and on-condition maintenance monitoring panel and master-slave switching method |
| CN101159533A (en) * | 2007-11-06 | 2008-04-09 | 中兴通讯股份有限公司 | Clock chain circuit automatic protection method in packet transmission network |
| CN101404570B (en) * | 2007-11-23 | 2011-01-12 | 硅谷数模半导体（北京）有限公司 | System and method for removing spread spectrum of reference clock signal |
| CN101404569B (en) * | 2007-11-23 | 2011-04-27 | 硅谷数模半导体（北京）有限公司 | Apparatus and method for frequency expansion of reference clock signal |
| CN101621372B (en) * | 2008-06-30 | 2013-01-30 | 华为技术有限公司 | Method for transmitting network asynchronous backplane active/standby changeover and device thereof |
| CN101621371B (en) * | 2008-07-04 | 2015-03-04 | 大唐移动通信设备有限公司 | Clock design method and clock device |
| CN101895360B (en) * | 2010-07-23 | 2015-06-10 | 中兴通讯股份有限公司 | Structured circuit simulation system, selection method and device of clock reference thereof |
| CN102006158B (en) * | 2010-11-29 | 2016-03-30 | 中兴通讯股份有限公司 | Clock synchronizing method and system |
| CN104092529B (en) * | 2014-07-24 | 2018-05-01 | 上海寰视网络科技有限公司 | A kind of clock is adjusted in synchronism system and its adjusting method |
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