CN1151627C

CN1151627C - Synchronous clock supply device

Info

Publication number: CN1151627C
Application number: CNB991270428A
Authority: CN
Inventors: 潘炳松; 张文; 尹朝晖; 陈晗颖
Original assignee: Alcatel Lucent Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 1999-12-29
Filing date: 1999-12-29
Publication date: 2004-05-26
Anticipated expiration: 2019-12-29
Also published as: CN1302133A

Abstract

The present invention relates to a synchronous clock supply device which comprises a main module and a spare module. The main module and the spare module are the same, and the whole device works under a warm backup state. The main module and the spare module respectively comprise an input clock processing unit, a phase locking unit which is bidirectionally connected with the input clock processing unit, output clock processing units which are unidirectionally connected with the phase locking unit, a storage unit, communication units and a central processing unit which is bidirectionally connected with each unit. The main module and the spare module have the following connection method: all the communication units are interconnected; all the output clock processing unit are interconnected, and the output clock processing units of one module interact to connect with the phase locking unit of the other module. The present invention guarantees the precision and the reliability of output clock signals.

Description

A kind of synchronised clock providing device

The present invention relates to a kind of synchronised clock providing device.

In digital communication network, the signal that transmits and exchange is that information is carried out bit stream coded, thereby has a specific transmission bit rate, if require the various digital devices on the communication network can both carry out exchanges data like clockwork mutually, just need the clock signal of the various digital devices (or network element) in the net to handle bit stream with identical phase place, the stationary problem of Here it is digital communication network with identical frequency.What the digital synchronous network in China's digital communication network adopted is principal and subordinate's method of synchronization, the internal clocking module of promptly using digital device is as nodal clock, make it can be synchronized with the clock signal of upper level, realize data communication, independently exist but this nodal clock can not break away from digital synchronous network.Along with the application of new digital equipment, as the signalling point and the Signalling Transfer Point of step number word series (SDH), signalling system No.7, digital crossover chained device (DACS) etc., all the short-term stability to clock has proposed more strict requirement.What is more important is along with the develop rapidly of mechanics of communication, a lot of new Digital equipment also all need to satisfy the clock signal of the various frequencies of International Telecommunications Union (ITU-T) suggestion, therefore press for a kind of independent synchronised clock providing device, so that satisfied synchronizing datum signal to be provided.

The object of the present invention is to provide a kind of synchronised clock providing device, it can provide the stratum-3 clock that independently satisfies ITU-T standard signal, promptly can be used for the synchronization node in the communication network, also can be used for independent digital device, make between the online various digital devices of digital communication and can carry out exchanges data mutually like clockwork.

The object of the present invention is achieved like this, that is: a kind of synchronised clock providing device, it comprises two identical modules, one of them is the main module of using, another is a spare module, whole device is operated under the Hot Spare state, this is main, spare module includes an input clock processing unit, one with the two-way phase locking unit that connects of this input clock processing unit, one with the unidirectional output clock processing unit that connects of this phase locking unit, one memory cell, one communication unit, and one with the two-way CPU that connects in above-mentioned each unit, described main connecting mode with module and spare module is: the communication unit of main usefulness module and the communication unit of spare module are interconnected; Main output clock processing unit with module is interconnected with the output clock processing unit of spare module, and the phase locking unit of main output clock processing unit and spare module with module links and the output clock processing unit of spare module and master link with the phase locking unit of module.Wherein: described each input clock processing unit, receive identical outside a plurality of input reference clock signals respectively, be used for three kinds of processing: first handles, carry out frequency division and signal quality alarming decrease and detect, and from a plurality of input reference clock signals, select road signal output the best in quality according to testing result; Second handles, selected for output signal automaticallyes switch to the input reference clock signal that a detected quality descends, and switches to the normal input reference clock signal in another road; The 3rd handles, and the use of the input reference clock signal that the inhibit signal quality descends has only forbidden input reference clock signal to recover just often, just cancels the warning of this signal automatically; Described each phase locking unit, the input clock processing unit from this module obtains signal respectively, carries out frequency multiplication, and the signal after the frequency multiplication is back to this input clock processing unit; The described clock processing unit of respectively exporting, be respectively applied for and receive two signals of exporting from the phase locking unit of this module and another module, be used to adjust in the very little scope of the phase difference to of these two output signals, this method of adjustment adopts delay line technique, and from adjusted two signals, select a signal to carry out signal regeneration and handle, export behind the signal frequency split with regeneration; In addition, each is exported between the clock processing unit, also carries out information exchange, so that the consistency of output signal; Described each communication unit, they are except carrying out each other the information exchange, also communicate with external system, and has a primary, spare automatic switching function, be to have only main communication unit and external system communication under the normal condition with module, when primary, spare switching takes place two modules, just automatically switch to the communication unit and the external system communication of spare module; Described each memory cell is respectively applied for stored information; Described each CPU is respectively applied for control and manages the operation of this module.

Owing to adopted above-mentioned technical solution, be that whole device (primary, spare module) is operated under the Hot Spare state, two mutual each other clock signal and other state informations that self produce of module, thereby guaranteed the reliability of clock signal, each module can correctly be determined self active and standby state of using independently according to oneself state and matching module state simultaneously, has strengthened the maintainability of device.Output signal of the present invention can also offer the various communication apparatus that need precision not to be higher than the stratum-3 clock signal, as uses such as Access Networks.

The present invention is further illustrated below in conjunction with embodiment and accompanying drawing.

Fig. 1 is a circuit structure functional block diagram of the present invention.

As seen from Figure 1, a kind of synchronised clock providing device of the present invention, comprise two identical modules, one of them is main with module 11, another is a spare module 22, whole device is operated under the Hot Spare state, this primary, spare module 11,22 include input clock processing unit 1, with the two-way phase locking unit that connects 3 of this input clock processing unit, with the unidirectional output clock processing unit 6 that connects of this phase locking unit, memory cell 5, communication unit 4 and and the CPU 2 of above-mentioned each two-way connection in unit.

Main connecting mode with module and spare module is: main communication unit 4 with module is interconnected with the communication unit 4 of spare module; Main output clock processing unit 6 with module is interconnected with the output clock processing unit 6 of spare module, and the phase locking unit 3 of main output clock processing unit 6 and spare module with module links and the output clock processing unit 6 of spare module links with the phase locking unit 3 of module with the master.

Each input clock processing unit 1 in the above-mentioned synchronised clock providing device, receive four road identical 2.048MHz and the outside input reference clock signal of four road 8KHz respectively, also receive central clock signal simultaneously from this module phase locking unit 3 feedbacks, external reference clock signal is through its alarm detection, judge whether input signal is effective, result of determination is delivered to described CPU 2, simultaneously also with this eight road external reference clock signal all frequency division be 4KHz, carry out bit comparison mutually one by one with the 4KHz signal behind the central clock signal frequency split, comparative result is also sent into the CPU 2 of this module, this CPU 2 is analyzed comparative result, judge whether external reference clock signal quality takes place descend, CPU 2 is according to quality decline result of determination and alarm detection result, and control input clock processing unit selects a top-quality external reference clock signal to output to phase locking unit 3 from eight external reference clock signals.In case CPU 2 finds that certain external reference clock signal has warning, just control input clock processing unit 1 and ban use of this external reference clock signal, if this external reference clock signal is the output signal of current selected, input clock processing unit 1 also will select another normal external reference clock signal as output signal at once automatically so, guarantees whole device operate as normal; After if the external reference clock signal of reporting to the police recovers normally, CPU 2 is just cancelled the warning of this signal automatically.

Phase locking unit 3 receives the output signal of input clock processing unit 1, is the central clock signal of 8.192MHz with its frequency multiplication, is back to input clock processing unit 1, also delivers to the output clock processing unit 6 of primary, spare module simultaneously respectively.

Output clock processing unit 6 receives two central clock signals from the phase locking unit in the primary and backup module 3.Under the normal condition, active and standby with having only the master to use the module clock signal in the module, standby with regard to original master being become with module when the master is taken place with module generation problem or other special circumstances, original spare module of while becomes the master and uses.Very big SPA sudden phase anomalies takes place to tend to when such switching is selected produce in handoff procedure, even lose clock signal in a flash at certain, perhaps two clock signals occur in following period of time and export simultaneously or export without any a signal, these situations all can have a strong impact on the operate as normal of whole communication system.Export for this reason clock processing unit 6 adopt phase difference to that delay line techniques adjust two central clock signals very among a small circle in, guarantee that phase difference when primary, spare module clock signal switches is less than 1/8 clock cycle, export clock processing unit 6 simultaneously and also monitor the quality of central clock signal, when quality worsens, produce alarm signal.In order to ensure unique signal output of system, output clock processing unit 6 is also selected the output clock according to the state and the clock alarm signal of primary, spare module, also can artificial selection output clock.The road clock signal that output clock processing unit 6 will choose is regenerated, and frequency multiplication is 16.384MHz, and output frequency division is 16M, 8M, 2M and 8KHz signal again, uses for external system.

Communication unit 4, on the one hand and another communication unit 4 that links with it carry out information exchange, on the other hand also and external system communicate, the operating state of oneself is sent to external system, and the control command of reception external system.This communication unit 4 also has primary, spare automatic switching function, be to have only main communication unit 4 and external system communication under the normal condition with module, when primary, spare switching takes place two modules, just automatically switch to the communication unit 4 and external system communication of spare module

CPU 2 is controlled and is managed whole device, guarantees whole device operate as normal.

All data that produce in memory cell 5 storage CPU 2 courses of work.

The present invention has also used a kind of advanced person's programmable logic device technology (CPLD), main number circuit in the whole device is integrated in a slice chip, so not only reduced the complexity of hardware circuit greatly, improved reliability, but also reduced overall volume, reduced cost, and easily in whole device is upgraded.

Claims

1. synchronised clock providing device, it is characterized in that: it comprises two identical modules, and one of them is mainly to use module, and another is a spare module, and whole device is operated under the Hot Spare state,

This primary, spare module include an input clock processing unit, one with the two-way phase locking unit that connects of this input clock processing unit, one with the unidirectional output clock processing unit that connects of this phase locking unit, a memory cell, a communication unit and one with the two-way CPU that connects in above-mentioned each unit

The described connecting mode of leading with module and spare module is: the communication unit of main usefulness module and the communication unit of spare module are interconnected; The output clock processing unit of main usefulness module and the output clock processing unit of spare module are interconnected, and the phase locking unit of main output clock processing unit with module and spare module links and the output clock processing unit of spare module and the phase locking unit of leading with module link, wherein:

Described each input clock processing unit, receive identical outside a plurality of input reference clock signals respectively, be used for three kinds of processing: first handles, carry out frequency division and signal quality alarming decrease and detect, and from a plurality of input reference clock signals, select road signal output the best in quality according to testing result; Second handles, selected for output signal automaticallyes switch to the input reference clock signal that a detected quality descends, and switches to the normal input reference clock signal in another road; The 3rd handles, and the use of the input reference clock signal that the inhibit signal quality descends has only forbidden input reference clock signal to recover just often, just cancels the warning of this signal automatically;

Described each phase locking unit, the input clock processing unit from this module obtains signal respectively, carries out frequency multiplication, and the signal after the frequency multiplication is back to this input clock processing unit;

The described clock processing unit of respectively exporting, be respectively applied for and receive two signals of exporting from the phase locking unit of this module and another module, be used to adjust in the very little scope of the phase difference to of these two output signals, this method of adjustment adopts delay line technique, and from adjusted two signals, select a signal to carry out signal regeneration and handle, export behind the signal frequency split with regeneration; In addition, each is exported between the clock processing unit, also carries out information exchange, so that the consistency of output signal;

Described each communication unit, they are except carrying out each other the information exchange, also communicate with external system, and has a primary, spare automatic switching function, be to have only main communication unit and external system communication under the normal condition with module, when primary, spare switching takes place two modules, just automatically switch to the communication unit and the external system communication of spare module;

Described each memory cell is respectively applied for stored information;

Described each CPU is respectively applied for control and manages the operation of this module.