CN108111293B - Clock synchronization method and data transmission system - Google Patents

Abstract

The embodiment of the invention provides a clock synchronization method and a data transmission system, which relate to the technical field of ultrasonic systems, and the method comprises the following steps: distributing the first-level clock to each second-level node respectively; receiving a second-level clock fed back after each second-level node processes the first-level clock; determining a phase correction amount of each second-stage clock according to the phase difference amount between each second-stage clock and the first-stage clock and a preset phase shifting parameter, wherein the phase correction amount of each second-stage clock represents a value of a phase which needs to be shifted of each second-stage clock; and respectively sending the phase correction quantity of each second-stage clock to each corresponding second-stage node to correct each second-stage clock. The clock synchronization method and the data transmission system provided by the embodiment of the invention can complete clock synchronization on one data transmission path.

Description

Clock synchronization method and data transmission system

Technical Field

The invention relates to the technical field of ultrasonic systems, in particular to a clock synchronization method and a data transmission system.

Background

The large-scale array ultrasonic system needs to be realized by cascading a plurality of subsystems, and the subsystems which are mutually cascaded need to be accurately triggered and controlled by timing signals as well as data communication, so that the subsystems can work cooperatively according to a certain time sequence.

However, the timing signals of the subsystems are generated by high-precision time delay relative to the synchronous signals or the reference timing points, and all of the time delay depends on a high-precision clock system. The timing signal and the high-precision clock system jointly form a clock synchronization system.

Disclosure of Invention

The invention aims to provide a clock synchronization method and a data transmission system, which can complete clock synchronization on one data transmission path.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:

in a first aspect, an embodiment of the present invention provides a clock synchronization method, which is applied to a first-level node, where the first-level node establishes communication with multiple second-level nodes, and the method includes: distributing a first-level clock to each second-level node respectively; receiving a second-stage clock fed back after each second-stage node processes the first-stage clock; determining a phase correction amount of each second-stage clock according to a phase difference amount between each second-stage clock and the first-stage clock and a preset phase shifting parameter, wherein the phase correction amount of each second-stage clock represents a value of a phase which needs to be shifted by each second-stage clock; and respectively sending the phase correction quantity of each second-stage clock to each corresponding second-stage node so as to correct each second-stage clock.

In a second aspect, an embodiment of the present invention provides a clock synchronization method, which is applied to a second-level node, where the second-level node establishes communication with a first-level node, and the method includes: receiving a first-level clock distributed by the first-level node; feeding back a second-stage clock obtained after processing the first-stage clock to the first-stage node, so that the first-stage node determines a phase correction value of the second-stage clock according to a phase difference between the second-stage clock and the first-stage clock and a preset phase shift parameter, wherein the phase correction value of the second-stage clock represents a value of a phase to be shifted of the second-stage clock; and correcting the second-stage clock according to the phase correction quantity of the second-stage clock.

In a third aspect, an embodiment of the present invention provides a clock synchronization method, where the method includes: the first-level node distributes a first-level clock to a plurality of second-level nodes respectively, and the plurality of second-level nodes establish communication with the first-level nodes respectively; each second-level node feeds back a second-level clock obtained after the first-level clock is processed to the first-level node; obtaining a phase correction value of each second-stage clock according to the phase difference quantity between each second-stage clock and the first-stage clock and a preset phase shifting parameter, wherein the phase correction value of each second-stage clock represents a value of a phase which needs to be shifted of each second-stage clock; distributing the phase correction amount of each of the second-stage clocks to each of the corresponding second-stage nodes, respectively, to correct each of the second-stage clocks.

In a fourth aspect, an embodiment of the present invention provides a data transmission system, where the system includes a first-level board card and a plurality of second-level board cards that establish communication with the first-level board card, where the first-level board card includes a first processor and a first transceiver electrically connected to each other, the second-level board card includes a second processor and a second transceiver electrically connected to each other, and the first transceiver and the second transceiver establish communication; the first processor is used for distributing a first-level clock to each second-level board card through the first transceiver; the second processor of each second-level board card is used for processing the received first-level clock to obtain a second-level clock, and feeding the second-level clock back to the first-level board card through the second transceiver; the first processor is further configured to determine a phase difference amount between each second-stage clock and the first-stage clock according to the received second-stage clock fed back by each second-stage board card, determine a phase correction amount of each second-stage clock according to the phase difference amount of each second-stage clock and a preset phase shift parameter, and distribute the phase correction amount of each second-stage clock to each corresponding second-stage board card through the first transceiver; the second processor of each second-stage board card is further configured to correct the second-stage clock according to the received phase correction amount of the corresponding second-stage clock.

Compared with the prior art, the clock synchronization method and the data transmission system provided by the embodiment of the invention determine the phase correction value of each second-stage clock by measuring the phase difference between the second-stage clock and the first-stage clock of each second-stage node and combining the preset phase shift parameter, and further correct each second-stage clock to ensure that the phase difference between each second-stage clock and the first-stage clock is the same, thereby realizing clock synchronization on one data transmission path.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 shows a schematic flow chart of a clock synchronization method provided by a first embodiment of the present invention;

FIG. 2 shows a schematic flow chart of a clock synchronization method provided by a second embodiment of the present invention;

FIG. 3 shows a schematic flow chart of a clock synchronization method provided by a third embodiment of the present invention;

FIG. 4 is a schematic flow chart of the substeps of step S320 in FIG. 3;

FIG. 5 is a schematic flow chart of the substeps of step S330 in FIG. 3;

fig. 6 is a schematic structural diagram showing a data transmission system provided by a fourth embodiment of the present invention;

fig. 7 shows a schematic connection structure diagram of a first-level board card and a second-level board card of a data transmission system according to a fourth embodiment of the present invention;

fig. 8 shows another schematic connection structure diagram of a first-level board card and a second-level board card of a data transmission system according to a fourth embodiment of the present invention;

fig. 9 shows another schematic connection structure diagram of a first-level board card and a second-level board card of a data transmission system according to a fourth embodiment of the present invention;

fig. 10 shows another schematic connection structure diagram of a first-stage board and a second-stage board of a data transmission system according to a fourth embodiment of the present invention.

In the figure: 10-a data transmission system; 100-a first-level board card; 110-a first processor; 120-a first transceiver; 130-a first deserializer; 140-a first clock distributor; 200-a second-level board card; 210-a second processor; 220-a second transceiver; 230-second serializer deserializer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The large-scale array ultrasonic system needs to be realized by a plurality of subsystems through cascade connection, such as a ten-thousand-channel system, and the subsystems which are mutually cascaded need to be accurately triggered and controlled by timing signals, so that the subsystems can work cooperatively according to a certain time sequence.

However, the timing signals of the subsystems are generated by high-precision time delay relative to the synchronous signals or the reference timing points, and all of the time delay depends on a high-precision clock system. The timing signal and the high-precision clock system jointly form a clock synchronization system.

In the prior art, when the precision required by the cooperative work among subsystems is not high, the subsystems can be directly connected in a small-scale array to work respectively. However, in the large-scale array ultrasound system, because the requirement on the accuracy of the cooperative work of each subsystem is high, the synchronization signal is usually adopted to cooperate with each subsystem to work in the prior art, but because the synchronization signal cannot synchronize the clock, the accuracy of the cooperative work of each subsystem is still low in the large-scale array ultrasound system due to the difference of the clocks in each subsystem. At this time, another clock synchronization solution is provided in the prior art, that is, when the large-scale array ultrasound system performs data transmission, another external system performs clock synchronization, that is, two systems are used to perform data transmission and clock synchronization, respectively.

The first embodiment:

based on the problems in the prior art, the inventor proposes an implementation manner in practical work as follows: in the ultrasonic system, after a previous node distributes a clock to all next nodes related to the previous node, the previous node receives the clocks of all next nodes related to the previous node, compares the phases of the clocks of each next node related to the previous node with the preset phase delay after measuring the phase delay of the clock of each next node related to the previous node, obtains the respective phase shift value of the clock of each next node related to the previous node, distributes the phase shift value to each corresponding next node, and corrects the clock of each next node to realize the clock synchronization of each next node. Referring to fig. 1, fig. 1 is a schematic flow chart of a clock synchronization method according to a first embodiment of the present invention, in which the ultrasound system includes a plurality of cascaded subsystems, each subsystem includes a first-level node and a plurality of second-level nodes, and the first-level node and each second-level node establish communication, where the first-level node in the subsystem may also be used as a second-level node of another subsystem, and the second-level node in the subsystem may also be used as a first-level node of another subsystem. In this embodiment, the clock synchronization method is applied to the first-level node, and the clock synchronization method includes the following steps:

and S110, respectively distributing the first-level clock to each second-level node.

In this embodiment, when the ultrasound system is clocked, the first level node distributes the first level clock separately to each of the second level nodes in communication with it in the subsystem.

And S120, receiving the second-stage clock fed back after each second-stage node processes the first-stage clock.

In this embodiment, since the communication paths of the first-level node and each second-level node are different, the time required for the first-level clock to be distributed to each second-level node through the first-level node is different, and thus the second-level clocks obtained by processing the obtained first-level clocks by each second-level node are different, so that the second-level clocks obtained by each second-level node need to be corrected. However, in this subsystem, each second-level node is independent from each other, and the common feature of these second-level nodes is that these second-level nodes establish communication with the first-level node, so after completing step S110, the first-level node distributes the first-level clock to each second-level node, and then receives the second-level clock fed back after each second-level node processes the first-level clock, so as to perform correction calculation.

And S130, determining a phase correction amount of each second-stage clock according to the phase difference amount of each second-stage clock and the first-stage clock and a preset phase shift parameter.

In this embodiment, after the first-level node receives the second-level clocks sent by the second-level node, each second-level clock is transmitted from the first-level node to the second-level node after a certain time, and is processed after the second-level node, so that each second-level clock and the first-level clock have a delay, and the specific external representation thereof is different in time, but the internal representation thereof is that the phase of each second-level clock and the phase of the first-level clock have a delay, that is, each second-level clock and the first-level clock have a phase difference, but since the time for transmitting the first-level clock from the first-level node to each second-level node is different, the phase difference of each second-level clock and the first-level clock is different, and therefore, according to the respective phase difference of each second-level clock and the first-level clock and the phase shift parameter set in advance, a unique phase correction amount for each second stage clock may be determined to correct the second stage clocks, where the phase correction amount for each second stage clock is indicative of the value of the phase that the corresponding second stage clock needs to be shifted.

For better illustration, in a hypothetical subsystem, the first-level node is a, and the second-level nodes are a1, a2, A3 and a4, respectively, and for the reason of the above-mentioned transmission time, we assume that the second-level clock of each second-level node a1, a2, A3 and a4 has a time difference with the first-level clock of the first-level node a, and the inherent characterization form is that the phase difference between the second-level clock of each second-level node a1, a2, A3 and a4 and the first-level clock of the first-level node a is 0.1ms, 0.2ms, 0.3ms and 0.4ms, respectively, and at this time, assuming that the preset phase shift parameter is 0.3ms, the phase shift amount of the second-level clock of each second-level node a1, a2, A3 and a4 is 0.2ms, 0.1ms, 0ms and-0.1 ms, respectively, that is, according to the preset phase shift parameter, the phase of the second level clock of the second level node a1 needs to be moved forward by 0.2ms, the phase of the second level clock of the second level node a2 needs to be moved forward by 0.1ms, the phase of the second level clock of the second level node A3 needs to be moved forward by 0ms, and the phase of the second level clock of the second node a4 needs to be moved backward by 0.1 ms.

It should be noted that, as an embodiment, the preset phase shift parameter may be a preset constant value, such as 0.3ms in the above-mentioned assumed system; as another embodiment, the determined phase shift parameter may be determined according to a preset rule, for example, in the above assumed system, after obtaining the respective phase difference amount of each second-stage node through measurement, by sorting, for example, from large to small or from small to large, the phase shift parameter may be set to one of the phase difference amounts determined according to a preset rule, for example, the largest one or the smallest one, or one of the sequence numbers is the order number, or may be a value located in the middle of the phase difference amounts, as long as a predetermined rule is satisfied to obtain a determined phase shift parameter, for example, a geometric mean value obtained according to the phase difference amounts may be used as a determined phase shift parameter.

And S140, respectively sending the phase correction quantity of each second-stage clock to each corresponding second-stage node to correct each second-stage clock.

In this embodiment, after determining the phase correction amount of each second-stage clock in step S130, the first-stage node sends the phase correction amount of each second-stage clock to each corresponding second-stage node, so that each second-stage node corrects its respective second-stage clock.

It should be noted that, as an implementation manner, since the phase delay of the clock in the array transmission system is influenced by other environmental conditions such as temperature, and the like, and the accuracy requirement for clock correction often cannot be met after once correction between each second-level clock, in the clock synchronization method provided in the first embodiment of the present invention, after the phase correction amount of each second-level clock is sent to each corresponding second-level node, the first-level node may further receive the corrected second-level clock fed back by each second-level node again, and calculate the phase correction amount of the second-level clock corrected by each second-level node again until the phase difference amount between each second-level clock and the first-level clock calculated by the first-level node meets the accuracy requirement of the array transmission system.

Based on the above design, the clock synchronization method provided in the first embodiment of the present invention determines the phase correction amount of the second-level clock of each second-level node by measuring the phase difference between the second-level clock of each second-level node and the first-level clock of the first-level node and combining the preset phase shift parameter, thereby implementing clock synchronization on one data transmission path.

Second embodiment:

referring to fig. 2, fig. 2 is a schematic flow chart of a clock synchronization method according to a second embodiment of the present invention, in an ultrasound system according to the first embodiment of the present invention, the ultrasound system includes a plurality of cascaded subsystems, each subsystem includes a first-level node and a plurality of second-level nodes, and the first-level node and each second-level node establish communication, where the first-level node in the subsystem may also be used as a second-level node of another subsystem, and the second-level node in the subsystem may also be used as a first-level node of another subsystem. In this embodiment, the clock synchronization method is applied to the second-level node, and the clock synchronization method includes the following steps:

s210, receiving a first-level clock distributed by a first-level node.

In this embodiment, the second level node receives the first level clock from the first level node distribution in the subsystem when the ultrasound system is clocked.

S220, feeding back a second-level clock obtained after the first-level clock is processed to the first-level node.

In this embodiment, after obtaining the first-level clock distributed by the first-level node through step S210, the second-level node processes the first-level clock to obtain the second-level clock of the second-level node. In the process of transmitting the first-level clock from the first-level node to the second-level node, transmission time is required, so that a second-level clock obtained by the second-level node through processing according to the received first-level clock has time delay compared with the first-level clock, and because a plurality of second-level nodes exist in the subsystem, the delays of the first-level clock from the first-level node to the second-level node are different, so that the second-level clocks processed by each second-level node are different, and the respective second-level clocks of the second-level nodes need to be subjected to clock synchronization.

Therefore, after the second-level node processes the first-level clock transmitted by the first-level node to obtain a second-level clock, the processed second-level clock is fed back to the first-level node, so that the first-level node determines the phase correction value of the second-level clock according to the phase difference between the second-level clock and the first-level clock and the preset phase shift parameter, wherein the phase correction value of the second-level clock represents the value of the phase to be shifted of the second-level clock.

And S230, correcting the second-stage clock according to the phase correction quantity of the second-stage clock.

In this embodiment, after the second-level node receives the phase correction amount of the second-level clock sent by the first-level node, the second-level clock is corrected according to the phase correction amount, so that the phase difference between the corrected second-level clock and the first-level clock is the same between each second-level node, that is, the phase difference between the corrected second-level clock and the first-level clock is the same after the phase correction of each second-level clock of each second-level node is performed by the phase correction amount.

It should be noted that, as an implementation manner, in the array transmission system, since the phase delay of the clock is influenced by other environmental conditions such as temperature, and the like, and the accuracy requirement for clock correction often cannot be met after once correction between each second-level clock, in the clock synchronization method provided in the second embodiment of the present invention, after the second-level node corrects the second-level clock according to the phase correction amount of the second-level clock distributed by the first-level node, the second-level node may further feed back the corrected second-level clock to the first-level node again, receive the phase correction amount of the second-level clock distributed by the first-level clock again, and correct the second-level clock again until receiving the signaling that the accuracy requirement for synchronization of each second-level clock fed back by the first-level node is met.

For a brief description, reference is made to the first embodiment of the invention for those points not mentioned in the second embodiment of the invention.

Based on the above design, in the clock synchronization method provided in the second embodiment of the present invention, the second-level node sends the second-level clock to the first-level node, receives the phase correction value of the second-level clock calculated from the first-level node, and corrects the second-level clock of the second-level node, thereby implementing clock synchronization on one data transmission path.

The third embodiment:

referring to fig. 3, fig. 3 is a schematic flowchart of a clock synchronization method according to a third embodiment of the present invention, in an ultrasound system established according to the first embodiment of the present invention, the ultrasound system includes a plurality of cascaded subsystems, each subsystem includes a first-level node and a plurality of second-level nodes, and the first-level node and each second-level node establish communication, where the first-level node in the subsystem may also be used as a second-level node of another subsystem, and the second-level node in the subsystem may also be used as a first-level node of another subsystem. In this embodiment, the clock synchronization method includes the following steps:

and S310, the first-level node distributes the first-level clock to a plurality of second-level nodes respectively.

In this embodiment, there are a plurality of second level nodes that establish communication with the first level node, respectively, and therefore, when performing clock synchronization on the subsystem, the first level node distributes the first level clock to the plurality of second level nodes, respectively. As a specific embodiment, the first level node may distribute the first level clock to each of the second level nodes separately.

And S320, each second-level node feeds back a second-level clock obtained after the first-level clock is processed to the first-level node.

In this embodiment, after each second-level node obtains a first-level clock sent by the first-level node, each second-level node processes the received first-level node to obtain the second-level clock, and since the time required from the first-level node to each second-level node is different, the second-level clocks processed by each second-level node are also different, and the second-level clocks of the second-level nodes need to be corrected, so as to implement clock synchronization. Therefore, after each second-stage node processes the obtained first-stage clock to obtain a second-stage clock, each second-stage node feeds back the respective second-stage clock to the first-stage node, so that the first-stage node executes corresponding processing.

S330, obtaining the phase correction quantity of each second-stage clock according to the phase difference quantity of each second-stage clock and the first-stage clock and the preset phase shift parameter.

In this embodiment, since the first-level node needs time to distribute the first-level clock to each second-level node, in step S320, the second-level clock processed by each second-level node is delayed compared to the first-level clock, and its internal appearance is that the second-level clock is compared to the first-level clock, and there is a phase difference, therefore, after the first-level node receives the respective second-level clock of each second-level node, the phase difference between the second-level clock and the first-level clock of each second-level node is subtracted to obtain the phase difference between each second-level clock and the first-level clock, at this time, the phase difference between each second-level clock is an amount representing the delayed phase between each second-level clock and the first-level clock, wherein the phase difference is larger, i.e. representing that the second-level clock is compared to other second-level clocks, the delay time from the first level clock is longer, that is, the time required for the data and the first level clock to be transmitted from the first level node to the second level node corresponding to the second level clock is longer.

Therefore, in order to synchronize the clocks of each second-stage node to meet the requirement that all second-stage nodes trigger accurate synchronization, a phase correction amount of each second-stage clock is obtained according to a preset phase shift parameter, wherein the phase correction amount is a difference value between the phase shift parameter and the phase difference amount of each second-stage clock, and the phase correction amount of each second-stage clock represents an amount of phase that each second-stage clock needs to be shifted, so that the phase difference amount of each second-stage clock is the same as that of the first-stage clock, that is, each second-stage clock is the same, thereby realizing clock synchronization.

And S340, respectively distributing the phase correction quantity of each second-stage clock to each corresponding second-stage node to correct each second-stage clock.

In this embodiment, after the first-stage node calculates the phase correction amount of each second-stage clock in step S330, the phase correction amount of each second-stage clock is distributed to each corresponding second-stage node, so that the second-stage clocks of the second-stage nodes are corrected in the second-stage nodes to make the phase difference between the second-stage clock of each second-stage node and the first-stage clock the same, that is, the second-stage clocks of the second-stage nodes are made the same to ensure the clock synchronization of all the second-stage nodes, so that each second-stage node triggers accurate synchronization during data transmission.

It should be noted that, as an implementation manner, in the array transmission system, since the phase delay of the clock is influenced by other environmental conditions such as temperature, and the like, and the accuracy requirement for clock correction often cannot be met after once correction between each second-level clock, in the clock synchronization method provided in the third embodiment of the present invention, after the phase correction amount of each second-level clock is sent to each corresponding second-level node by the first-level node, each second-level node corrects its respective second-level clock, and may also send the respective corrected second-level clock to the first-level node again; the first-stage node measures the phase difference between each corrected second-stage clock and the first-stage clock according to the received corrected second-stage clock sent by each second-stage node, calculates the phase correction amount of the corrected second-stage clock of each second-stage node again, and sends the phase correction amount to each corresponding second-stage node; and after each second-stage node receives the phase correction quantity of the respective corrected second-stage clock again, correcting the respective second-stage clock again. And calculating the phase difference quantity of each second-stage clock and the first-stage clock by the first-stage node until the phase difference quantity meets the precision requirement of the array transmission system.

Based on the above design, in a clock synchronization method provided in the third embodiment of the present invention, after each second-level node obtains a first-level clock distributed by the first-level node and processes the first-level clock to obtain a respective second-level clock, the respective second-level clock is sent to the first-level node, so that the first-level node obtains a respective phase correction value of each second-level clock according to a preset phase shift parameter, and the respective phase correction values are distributed to the corresponding second-level nodes, so that the second-level nodes correct the respective second-level clocks, thereby achieving clock synchronization of each second-level node.

After each second-level node processes a first-level clock distributed by a first-level node to obtain a respective second-level clock of each second-level node, because each second-level node sends the respective second-level clock to the first-level node and receives a respective phase correction amount of each second-level clock distributed by the first-level node, time transmitted by the first-level node to each second-level node is different, but the phase correction amount of each second-level clock is a definite value, after each second-level node processes the respective second-level clock, each second-level clock should remain unchanged, and an implementation manner provided by a third embodiment of the present invention is: and latching the second-stage clock obtained by processing the second-stage node through a phase-locked loop. Referring to fig. 4, fig. 4 is a schematic flowchart illustrating the sub-steps of step S320 in fig. 3, in the present embodiment, step S320 includes the following sub-steps:

s321, processing the first-level clock according to the local clock of each second-level node to obtain a second-level clock.

In this embodiment, when the first-level node distributes the first-level clock to each second-level node, the first-level clock is not directly distributed to each second-level node, but the first-level clock is encoded and then transmitted, so that after obtaining the first-level clock of the encoding process transmitted by the first-level node, each second-level node decodes the received first-level clock after the encoding process according to the local clock of each second-level node, so as to obtain the respective second-level clock of each second-level node.

And S322, adopting a phase-locked loop to latch the second-stage clock.

In this embodiment, since each second-level node obtains the first-level clock distributed by the first-level node after processing, and after obtaining the respective second-level clock of each second-level node, it is necessary to send the respective second-level clock of each second-level node to the first-level node to obtain the phase correction value of each second-level clock, but the time required for the transmission process and the process for the first-level node to redistribute the phase correction value of each second-level clock to each second-level node are the same, and the time for the first-level node to redistribute the phase correction value of each second-level clock to each second-level node is different, that is, when obtaining the phase correction value of each second-level clock of each second-level node, the delay of each second-level clock of each second-level node when processing to obtain the respective second-level clock is different from each second-level clock, that is, the phase correction amount for each second-stage clock calculated when each second-stage node obtains its respective second-stage clock through processing is not applicable at this time, that is, it is calculated that each second-stage clock is corrected by the phase correction amount for each second-stage clock at this time, and each corrected second-stage clock is different. Therefore, in the present embodiment, the second-stage clock processed by each second-stage node is latched by the phase-locked loop to determine that the corrected time point does not change.

Based on the above analysis of the first embodiment of the present invention and the second embodiment of the present invention, since the clock change is generated by phase shift inside the clock, and the phase-locked loop is a loop that locks the phase, the phase of each second-stage clock is locked by the phase-locked loop, so that each second-stage node sends its respective second-stage clock to the first-stage node, and then receives the phase correction amount sent by the first-stage node for each second-stage clock, each second-stage clock does not delay, that is, each second-stage node does not have phase shift when sending its respective second-stage clock and receiving the phase correction amount for each second-stage clock, and thus the time point corrected by each second-stage clock does not change.

It should be noted that, since each second-stage clock is latched by using the phase-locked loop, which aims to make the time point of correction of each second-stage clock not change, in some embodiments of the present invention, when the second-stage clock of any one second-stage node is out-of-lock, it is indicated that the second-stage clock may have been delayed, that is, the reference time point of correction is already different from that of other second-stage clocks, so that the result of correction may cause clock synchronization failure, and at this time, step S310 should be executed again, and the first-stage node distributes the first-stage clock to a plurality of second-stage nodes respectively.

Based on the above design, in a clock synchronization method provided by the third embodiment of the present invention, each second-stage node latches the respective second-stage clock through a phase-locked loop, so that when each second-stage node transmits the respective second-stage clock and receives the phase correction amount of each second-stage clock, the phase of each second-stage clock does not shift, and thus the time point corrected by each second-stage clock does not change.

After receiving the second-level clock sent by each second-level node, the first-level node needs to obtain the respective phase correction value of each second-level clock by combining the first-level clock so as to correct each second-level clock. A third embodiment of the present invention provides an implementation manner of: the phase difference between each second-stage clock and the first-stage clock is measured, and the amount of the phase which should be shifted by each second-stage clock is determined according to a preset phase shifting parameter, so that each second-stage clock is corrected to be the same as the phase difference of the first-stage clock, and clock synchronization is realized. Referring to fig. 5, fig. 5 is a schematic flowchart illustrating the sub-steps of step S330 in fig. 3, in the present embodiment, step S330 includes the following sub-steps:

s331, a phase difference amount between each second-stage clock and the first-stage clock is obtained.

In this embodiment, after the first-level node receives the respective second-level clock sent by each second-level node, the phase difference between each second-level clock and the first-level clock is obtained by measuring the respective phases of each second-level clock and the first-level clock, and performing difference calculation, where the phase difference between each second-level clock and the first-level clock represents a phase shift value of the second-level clock relative to the first-level clock, that is, the larger the phase difference between the second-level clock and the first-level clock is, the larger the delay between the second-level clock and the first-level clock is, that is, the more time is required for the second-level node corresponding to the second-level clock to perform data transmission with the first-level node.

S332, obtaining a phase correction amount of each second-stage clock according to the phase difference amount of each second-stage clock and a preset phase shift parameter.

In this embodiment, the phase difference amount of each second stage clock can be obtained by step S331, but since the time required for the first level clock to travel from the first level node to each second level node is different, therefore, the phase difference amount between each second-stage clock and the first-stage clock is different, and the clock synchronization method provided by the embodiment of the invention is to synchronize the phase difference amount between each second-stage clock and the first-stage clock, therefore, calculating a difference between the phase difference amount of each second stage clock and the phase shift parameter based on a phase shift parameter set in advance to determine a phase correction amount for each second stage clock, wherein the amount of phase correction for each second stage clock characterizes the amount of phase that each second stage clock needs to be shifted, so that the phase difference between the second-stage clock and the first-stage clock is equal to the phase shift parameter set in advance.

It should be noted that, as an embodiment, the preset phase shift parameter may be a preset constant value, so that the phase difference amount of each second-stage clock is adjusted to the preset constant value; as another embodiment, the determined phase shift parameter may be determined according to a preset rule, for example, according to a rule from large to small or from small to large by sorting, and the phase shift parameter may be set to be one of the phase difference amounts determined according to a predetermined rule, for example, the largest one or the smallest one, or one of the phase difference amounts with the rank number being the order number, or may be a value located in the middle of the phase difference amounts, as long as a predetermined rule is satisfied to obtain a determined phase shift parameter, for example, a geometric mean value obtained according to the phase difference amounts may be used as a determined phase shift parameter.

Based on the above design, a clock synchronization method provided in the third embodiment of the present invention determines a phase correction amount of each second-stage clock by using a phase difference amount between each second-stage clock and the first-stage clock and a preset phase shift parameter, so that the phase difference amount of each corrected second-stage clock is the same as that of the first-stage clock, thereby implementing clock synchronization between each second-stage node.

For a brief description, reference is made to the first embodiment of the present invention and the second embodiment of the present invention where nothing is mentioned about the third embodiment of the present invention.

The fourth embodiment:

based on the first, second, and third embodiments of the present invention, a fourth embodiment of the present invention provides a data transmission system 10, which can implement the clock synchronization method in the above embodiments during or before data transmission. Referring to fig. 6, fig. 6 is a schematic structural diagram of a data transmission system 10 according to a fourth embodiment of the present invention, in this embodiment, a data transmission system 10 includes a first-level board 100 and a plurality of second-level boards 200 that establish communication with the first-level board 100, each second board may also establish communication with a plurality of third-level boards, and each board and a next-level board that establishes communication with the second-level board may be regarded as a subsystem through this cascade connection, and a large-scale data transmission system 10, such as a wan-channel system, may be established through a mode in which the plurality of subsystems are cascaded, where each subsystem may perform clock synchronization by using the clock synchronization method provided in the first embodiment, the second embodiment, and the third embodiment, so as to achieve triggering accurate synchronization between each board of the same level.

Referring to fig. 7, fig. 7 is a schematic connection structure diagram of a first-stage board 100 and a second-stage board 200 of a data transmission system 10 according to a fourth embodiment of the present invention, in this embodiment, the first-stage board 100 includes a first processor 110 and a first transceiver 120 that are electrically connected to each other, the second-stage board 200 includes a second processor 210 and a second transceiver 220 that are electrically connected to each other, wherein the first transceiver 120 and the second transceiver 220 establish communication to implement data transmission and clock transmission between the first-stage board 100 and the second-stage board 200, and the first-stage board 100 further sends a first-stage clock to the second-stage board 200 through the first transceiver 120, wherein when the first-stage board 100 is connected to a plurality of second-stage boards 200, the first-stage board 100 sends the first-stage clock to each second-stage board 200 through the first transceiver 120, and sends the first stage clock to the first processor 110 for latching. At this time, since the first-level clock cannot be directly distributed to each second-level board card 200 during data transmission, the first-level clock needs to be encoded to obtain serial data, and then the serial data obtained after encoding the first-level clock is distributed to each second-level board card 200.

As an embodiment, the first transceiver 120 and the second transceiver 220 may be configured as optical fiber transceivers, and the first transceiver 120 and the second transceiver 220 may establish communication through optical fibers, so that the data transmission rate between the first-stage board 100 and the second-stage board 200 can be stabilized to 400 Mbit.

After the second processor 210 of the second-level board card 200 obtains the serial data distributed by the first-level board card 100 through the second transceiver 220, the serial data including the first-level clock is decoded according to a decoding program in the second processor 210 to obtain a second-level clock, the second-level clock is encoded to obtain serial data including the second-level clock, and the serial data including the second-level clock is fed back to the first-level board card 100 through the second transceiver 220.

After the second-stage boards 200 feed back the serial data including the second-stage clock to the first-stage boards 100, the first processor 110 in the first-stage board 100 decodes the serial data through a decoding program arranged in the first processor 110, and obtains the second-stage clock of each second-stage board 200. At this time, since the time required for the serial data including the first stage clock to be distributed to each second stage board 200 is different, the delay generated by the second stage clock obtained by each second processor 210 at the time of decoding compared to the first stage clock is different, and this delay is inherently expressed in the form that the phase difference between the second stage clock and the first stage clock is different. Therefore, the first processor 110 is further configured to measure a phase difference amount between each second-stage clock and the first-stage clock according to the phase of the received second-stage clock of each second-stage board card 200 and the phase of the first-stage clock, where the phase difference amount of each second-stage clock represents a length of a delay time of the second-stage clock compared with the first-stage clock, and the larger the phase difference amount is, the longer the delay time generated by the second-stage clock compared with other second-stage clocks is, that is, the longer the time required for the first-stage board card 100 to transmit data to the second-stage board card 200 is. After the first processor 110 measures the phase difference amount of each second-stage clock, determining the phase correction amount of each second-stage clock according to a preset phase shift parameter, and distributing the phase correction amount of each second-stage clock to each corresponding second-stage board 200 through the first transceiver 120, wherein the preset phase shift parameter represents the amount of phase to be shifted when the second-stage clock processed by each second-stage board 200 is compared with the first-stage clock, the phase difference amount of each second-stage clock and the first-stage clock measured by the first processor 110 is adjusted based on the phase shift parameter, so that the phase difference amount of each second-stage clock and the first-stage clock is the same as the phase shift parameter, and the phase correction amount of each second-stage clock is the difference between the phase shift parameter and each second-stage clock, and the phase correction amount of each second stage clock represents the value of the phase that the second stage clock of its corresponding second stage board 200 needs to be shifted.

The second processor 210 of each second-stage board 200 is further configured to correct the second-stage clock of each second-stage board 200 according to the received phase correction amount of each corresponding second-stage clock, so as to implement clock synchronization between each second-stage board 200.

The first processor 110 and the second processor 210 are integrated circuit chips and have signal processing capability. The first Processor 110 and the second Processor 210 may be general-purpose processors including a Central Processing Unit (CPU), a Network Processor (NP), a voice Processor, a video Processor, and the like; but may also be a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Referring to fig. 8, fig. 8 is another schematic connection structure diagram of a first-stage board 100 and a second-stage board 200 of a data transmission system 10 according to a fourth embodiment of the present invention, in this embodiment, the first-stage board 100 further includes a first clock distributor 140, the first clock distributor 140 is electrically connected to the first processor 110, and is configured to generate a first-stage clock and send the first-stage clock to the first processor 110, where after obtaining the first-stage clock, the first processor 110 latches the first-stage clock while distributing the first-stage clock to each second-stage board 200, so as to determine a phase when distributing the first-stage clock, so as to enable a phase reference value of the first-stage clock when measuring a phase difference amount of each second-stage clock.

In the above design, the process of encoding and decoding data and clock is implemented by the first processor 110 and the second processor 210, but if the process of encoding and decoding are implemented by the first processor 110 and the second processor 210, the load of the first processor 110 and the second processor 210 may be increased, and another embodiment of the data transmission system 10 provided by the fourth embodiment of the present invention is as follows: the process of encoding and decoding is accomplished by the serializer by connecting the processor to the serializer and then to the transceiver. Referring to fig. 9, fig. 9 is another schematic connection structure diagram of a first-level board 100 and a second-level board 200 of a data transmission system 10 according to a fourth embodiment of the present invention, in this embodiment, the first-level board 100 further includes a first deserializer 130, the first processor 110 is electrically connected to the first transceiver 120 through the first deserializer 130, at this time, clock information including a first-level clock distributed by the first processor 110 is encoded by the first deserializer 130, and then distributed to each second-level board 200 through the first transceiver 120; meanwhile, the clock information including the second-level clock transmitted by each second-level board card 200 is also decoded by the first deserializer 130 and then transmitted to the first processor 110; the clock information distributed by the first processor 110 and including the phase correction amount of each second-stage clock is also encoded by the first deserializer 130, and then transmitted to the corresponding second-stage board 200 via the first transceiver 120.

The second-level board 200 further includes a second serializer/deserializer 230, and the second processor 210 is electrically connected to the second transceiver 220 through the second serializer/deserializer 230, at this time, the clock information received by the second transceiver 220 and including the phase correction amount of the first-level clock or the second-level clock is decoded by the second serializer/deserializer 230 and then sent to the second processor 210; meanwhile, the clock information including the second-level clock sent by the second processor 210 is also encoded by the second deserializer 230 and then sent to the first-level board 100 through the second transceiver 220.

Referring to fig. 10, fig. 10 is another schematic connection structure diagram of a first-stage board 100 and a second-stage board 200 of a data transmission system 10 according to a fourth embodiment of the present invention, in this embodiment, the first-stage board 100 further includes a first clock distributor 140 and a first deserializer 130 that are electrically connected to each other, the first processor 110 is electrically connected to the first transceiver 120 through the first deserializer 130, at this time, clock information that includes a first-stage clock and is distributed by the first clock distributor 140 is encoded by the first deserializer 130, and then is distributed to each second-stage board 200 through the first transceiver 120; meanwhile, the clock information containing the first-stage clock transmitted by the first clock distributor 140 is also transmitted to the first processor 110 through the first deserializer 130 for latching; meanwhile, the clock information including the second-level clock transmitted by each second-level board card 200 is also decoded by the first deserializer 130 and then transmitted to the first processor 110; the clock information distributed by the first processor 110 and including the phase correction amount of each second-stage clock is also encoded by the first deserializer 130, and then transmitted to the corresponding second-stage board 200 via the first transceiver 120.

The second-level board 200 further includes a second serializer/deserializer 230, and the second processor 210 is electrically connected to the second transceiver 220 through the second serializer/deserializer 230, at this time, the clock information received by the second transceiver 220 and including the phase correction amount of the first-level clock or the second-level clock is decoded by the second serializer/deserializer 230 and then sent to the second processor 210; meanwhile, the clock information including the second-level clock sent by the second processor 210 is also encoded by the second deserializer 230 and then sent to the first-level board 100 through the second transceiver 220.

It should be noted that, in some other embodiments of the present invention, the first clock distributor 140 may be further electrically connected to the first processor 110, at this time, the first-stage clock generated by the first clock distributor 140 is distributed to the first processor 110 and the first deserializer 130 at the same time, at this time, the first processor 110 obtains the first-stage clock latch for obtaining the phase difference amount of each second-stage clock subsequently, and the first deserializer 130 distributes the obtained first-stage clock to each second-stage board 200 respectively.

In summary, in the clock synchronization method and the data transmission system provided in the embodiments of the present invention, the phase difference between the second-level clock of each second-level node and the first-level clock of the first-level node is measured, and a preset phase shift parameter is combined to determine the phase correction value of the second-level clock of each second-level node, so as to correct each second-level clock, so that the phase difference between each second-level clock and the first-level clock is the same, thereby implementing clock synchronization on one data transmission path; meanwhile, a subsystem formed by a first-level node and a plurality of second-level nodes is connected with a plurality of subsystems in a cascading mode, and when the mutual clock synchronization of the nodes at the same level is ensured, the subsystems are easy to cascade, and a large-scale data transmission system is formed.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (7)

1. A method of clock synchronization, the method comprising:

the first-level node distributes a first-level clock to a plurality of second-level nodes respectively, and the plurality of second-level nodes establish communication with the first-level nodes respectively;

each second-level node feeds back a second-level clock obtained after the first-level clock is processed to the first-level node;

obtaining a phase correction value of each second-stage clock according to the phase difference quantity between each second-stage clock and the first-stage clock and a preset phase shifting parameter, wherein the phase correction value of each second-stage clock represents a value of a phase which needs to be shifted of each second-stage clock;

distributing the phase correction amount of each second-stage clock to each corresponding second-stage node to correct each second-stage clock;

the step of feeding back, by each second-level node, a second-level clock obtained after processing the first-level clock to the first-level node includes:

processing the first-level clock according to the local clock of each second-level node to obtain a second-level clock;

and adopting a phase-locked loop to latch the second-stage clock.

2. The method of claim 1, wherein the step of the first level node distributing the first level clock to the plurality of second level nodes, respectively, is re-executed when the second level clock of any one of the second level nodes is out-of-lock.

3. The method according to claim 2, wherein the step of obtaining a phase correction amount for each of the second-stage clocks based on a phase difference amount of each of the second-stage clocks from the first-stage clock and a phase shift parameter set in advance comprises:

obtaining a phase difference amount of each second-stage clock and the first-stage clock;

and obtaining the phase correction quantity of each second-stage clock according to the phase difference quantity of each second-stage clock and a preset phase shift parameter.

4. A data transmission system using the clock synchronization method according to claim 1, wherein the system includes a first-stage board card and a plurality of second-stage board cards that establish communication with the first-stage board card, the first-stage board card includes a first processor and a first transceiver electrically connected to each other, the second-stage board card includes a second processor and a second transceiver electrically connected to each other, the second transceiver establishes communication with the first transceiver, and the first-stage board card transmits a first-stage clock to the plurality of second-stage board cards through the first transceiver;

the second processor of each second-level board card is used for processing the received first-level clock to obtain a second-level clock, and feeding the second-level clock back to the first-level board card through the second transceiver;

the first processor is configured to determine a phase difference amount between each second-stage clock and the first-stage clock according to a received second-stage clock fed back by each second-stage board card, determine a phase correction amount of each second-stage clock according to the phase difference amount of each second-stage clock and a preset phase shift parameter, and distribute the phase correction amount of each second-stage clock to each corresponding second-stage board card through the first transceiver;

the second processor of each second-stage board card is further configured to correct the second-stage clock according to the received phase correction amount of the corresponding second-stage clock.

5. The system of claim 4, wherein the first level board further comprises a first clock distributor electrically coupled to the first processor for generating a first level clock and transmitting to the first processor.

6. The system of claim 5, wherein the first level cards further comprise a first deserializer, the first processor being electrically connected to the first transceiver through the first deserializer, the first deserializer being configured to send clock information distributed by the first processor to each respective second level card through the first transceiver and to send clock information received by the first transceiver for each second level card to the first processor;

the second-level board card further comprises a second deserializer, the second processor is electrically connected with the second transceiver through the second deserializer, and the second deserializer is used for sending the clock information sent by the second processor to the first-level board card through the second transceiver and sending the clock information received by the second transceiver to the second processor.

7. The system of claim 6, wherein the first-level board further comprises a first clock distributor and a first deserializer electrically connected to each other, the first processor is electrically connected to the first transceiver through the first deserializer, the first deserializer is configured to send clock information distributed by the first clock distributor or clock information distributed by the first processor to each corresponding second-level board through the first transceiver, and is configured to send clock information received by the first transceiver for each second-level board or clock information sent by the first clock distributor to the first processor;

the second-level board card further comprises a second deserializer, the second processor is electrically connected with the second transceiver through the second deserializer, and the second deserializer is used for sending the clock information sent by the second processor to the first-level board card through the second transceiver and sending the clock information received by the second transceiver to the second processor.

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