CN101895360B - Structured circuit simulation system, selection method and device of clock reference thereof - Google Patents
Structured circuit simulation system, selection method and device of clock reference thereof Download PDFInfo
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- CN101895360B CN101895360B CN201010239161.8A CN201010239161A CN101895360B CN 101895360 B CN101895360 B CN 101895360B CN 201010239161 A CN201010239161 A CN 201010239161A CN 101895360 B CN101895360 B CN 101895360B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/40—Artificial lines; Networks simulating a line of certain length
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Abstract
The invention provides a selection device of clock reference in a structured circuit simulation system, which is used for receiving a multi-channel circuit clock and a multi-channel pseudowire (PW) clock, selecting one channel from the multi-channel circuit clock or the multi-channel PW clock as the main clock reference to output, and selecting one channel from the multi-channel circuit clock or the multi-channel PW clock as the standby clock reference to output. The invention further provides a selection method of the clock reference in the structured circuit simulation system. The invention can flexibly select to extract a clock from a circuit as a reference or to extract some PW recovery clock from a PSN side as a reference.
Description
Technical field
The present invention relates to the circuit simulation (CESoP based on Packet Based Network in telecommunication technology field, CircuitEmulation Service over Packet) technology, in particular, system of selection and the device of a kind of structured circuit simulation system and clock reference thereof is related to.
Background technology
Along with the high speed development of IP technology and the surge of data service, the IPization of communication network becomes the inexorable trend of future development gradually.But traditional existence based on Circuit-switched time division multiplexing (TDM, TimeDivision Multiplexing) business network still a large amount of reality.How above to carry traditional TDM business at the packet switching network (PSN, Packet Switch Network) of a new generation is the problem that must solve in the development of current communication network.Circuit simulation (CESoP) technology based on Packet Based Network is exactly a kind of well solution.
CESoP is divided into non-structured simulation technology and structurized simulation technology.Non-structured emulation technology is the transparent transmission on PSN network of the TDM bit streams such as E1/T1, nonrecognition frame format.A corresponding 1 pseudo-line of PW (Pseudo Wire) of TDM interface, the clock of each TDM interface can be separate.And structuring emulation technology is the emulation carried out after time slotted circuit, need the frame structure identifying E1/T1 etc., can the pseudo-line of corresponding 1 PW of N*64K time slot.Due to time-slot cross may be there is, require that the clock of each TDM interface must homology homophase.Therefore there is the select permeability of a clock reference.
Exist in prior art and CESoP technology can be provided, and support destructuring emulation and support the chip that structuring emulates.This chip, under structuring simulation model, can be supported to extract clock from E1/T1 line side as clock reference, also can support extraction from the clock (PW clock) of PSN side recovery as clock reference.And one main one can be chosen for two clock references, once master clock reference fault can automatically switch to spare clock reference.But there are the following problems in actual applications:
1) be extract clock from E1/T1 circuit in engineering or be uncertain using PSN side recovered clock as clock reference, and the circuit of this chip once connect cannot be changed at engineering site;
2) select from PW clock as benchmark time, if when this PW business breaks down, this chip can export free-running clock, cause benchmark to switch, impact the overall situation clock synchronous.
Summary of the invention
The technical problem to be solved in the present invention is, provides a kind of configurable, highly reliable, convenient, flexible clock reference system of selection and device, and provides a kind of structured circuit simulation system.
In order to solve the problem, the clock reference that the invention provides in a kind of structured circuit simulation system selects equipment, and described clock reference selects equipment to be used for:
Receive multi-path line clock and pseudo-line (PW) clock of multichannel, from described multi-path line clock or multichannel PW clock, select a road to export as active clock benchmark; And, from described multi-path line clock or multichannel PW clock, select a road to export as spare clock reference.
Further, above-mentioned clock reference selects equipment also can have following characteristics, and described clock reference selects equipment to comprise central processing unit control interface device, line side clock output-controlling device and PW side clock output-controlling device and clock selecting device, wherein:
Described central processing unit control interface device, is connected with outside central processing unit, for receiving the control signal of central processing unit, controlling described clock reference and selecting all the other each devices of equipment;
Described line side clock output-controlling device, for receiving the input of described multi-path line clock, according to the control of described central processing unit control interface device, exports or does not export described line clock to described clock selecting device;
Described PW side clock output-controlling device, for receiving the input of described multichannel PW clock, according to the control of described central processing unit control interface device, exports or does not export described PW clock to described clock selecting device;
Described clock selecting device, for the PW clock that the line clock and described PW side clock output-controlling device that receive the clock output-controlling device output of described line side export, select selection one tunnel to export as active clock benchmark, select a road to export as spare clock reference.
Further, above-mentioned clock reference selects equipment also can have following characteristics, described central processing unit control interface device, for when the service condition of described line clock input is abnormal, controls described line side clock output-controlling device and does not export described line clock; When the service condition of described PW clock input is abnormal, controls described PW side clock output-controlling device and do not export described line clock.
Further, above-mentioned clock reference selects equipment also can have following characteristics, described clock selecting device comprises: line side active clock selection of reference frame device, line side spare clock reference choice device, pseudo-line (PW) side active clock selection of reference frame device, PW side spare clock reference choice device, active clock choice device and standby clock choice device, wherein:
Described line side active clock selection of reference frame device, be connected with described line side clock output-controlling device, for the control according to central processing unit control interface device, from the line clock that described line side clock output-controlling device exports, a road is selected to export as line side active clock benchmark;
Described line side spare clock reference choice device, be connected with described line side clock output-controlling device, for the control according to central processing unit control interface device, from the line clock that described line side clock output-controlling device exports, a road is selected to export as line side spare clock reference;
Described PW side active clock selection of reference frame device, be connected with described PW side clock output-controlling device, for the control according to central processing unit control interface device, from the PW clock that described PW side clock output-controlling device exports, a road is selected to export as PW side active clock benchmark;
Described PW side spare clock reference choice device, be connected with described PW side clock output-controlling device, for the control according to central processing unit control interface device, from the PW clock that described PW side clock output-controlling device exports, a road is selected to export as PW side spare clock reference;
Described active clock choice device, for the control according to central processing unit control interface device, from the two-way clock that described line side active clock selection of reference frame device and described PW side active clock selection of reference frame device export, a road is selected to export as active clock benchmark;
Described standby clock choice device, for the control according to central processing unit control interface device, from the two-way clock that described line side spare clock reference choice device and described PW side spare clock reference choice device export, a road is selected to export as spare clock reference.
The present invention also provides a kind of structured circuit simulation system, described system comprises: central processing unit control appliance, E1/T1 line interface and frame device, Circuit Emulation Service equipment and as arbitrary in Claims 1-4 as described in clock reference select equipment, described clock reference selects equipment and central processing unit control appliance, E1/T1 line interface and frame device, Circuit Emulation Service equipment is connected, described clock reference selects equipment to be used for receiving the input of multi-path line clock from described E1/T1 line interface and frame device and receiving the input of multichannel PW clock from described Circuit Emulation Service equipment, export a road active clock benchmark and a road spare clock reference extremely described Circuit Emulation Service equipment.
Further, said system also can have following characteristics, and described clock reference selects equipment to be used for described active clock benchmark fixedly to export to road time division multiplexing (TDM) clock input interface of described Circuit Emulation Service equipment; Described spare clock reference is fixedly exported to another road TDM clock input interface of described Circuit Emulation Service equipment.
The present invention also provides the system of selection of clock reference in a kind of structured circuit simulation system, comprising:
Receive multi-path line clock and pseudo-line (PW) clock of multichannel, from described multi-path line clock or multichannel PW clock, select a road to export as active clock benchmark; And, from described multi-path line clock or multichannel PW clock, select a road to export as spare clock reference.
Further, said method also can have following characteristics, and described method also comprises:
The service condition of described multi-path line clock or PW clock is detected, controls export or do not export described line clock or PW clock according to described service condition.
Further, said method also can have following characteristics, when the service condition of described multi-path line clock or PW clock is abnormal, does not export described line clock or PW clock.
Further, said method also can have following characteristics, and described method also comprises:
Described active clock benchmark is fixedly exported to road time division multiplexing (TDM) clock input interface of Circuit Emulation Service equipment; Described spare clock reference is fixedly exported to another road TDM clock input interface of described Circuit Emulation Service equipment.
Compared with the clock synchronization scheme provided in prior art, invention increases the judgment mechanism of clock status, when fault, clock does not export, and facilitates the switching of master/backup clock benchmark; Add the configurable of clock source in addition, can select to extract clock as benchmark from certain E1/T1 circuit according to service conditions neatly, or select to extract certain PW recovered clock as benchmark from PSN side.Also simplify the configuration operation of software to chip in addition.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the application scheme schematic diagram being synchronized with E1/T1 line side clock provided in prior art;
Fig. 2 is the application scheme schematic diagram being synchronized with PW side clock provided in prior art;
Fig. 3 is the application scheme schematic diagram that structured circuit simulation system clock reference of the present invention selects equipment;
Fig. 4 is the structural representation that structured circuit simulation system clock reference of the present invention selects equipment;
Fig. 5 and Fig. 6 is the flow chart that structured circuit simulation system clock reference of the present invention selects device software layoutprocedure;
Fig. 7 is that structured circuit simulation system clock reference of the present invention selects device software timing scan line side service condition and the flow chart of control circuit clock output;
Fig. 8 is that structured circuit simulation system clock reference of the present invention selects device software timing scan PW side business state and the flow chart of control PW clock output.
Embodiment
The present invention proposes one clock reference selection scheme flexibly, be mainly reflected in three aspects, the first, whether each alternate clock source can control to export, to facilitate the switching of master/backup clock benchmark according to service conditions; The second, clock reference selects from E1/T1 line side or selects to configure from the clock side that PW recovers, and adds the flexibility in engineering; 3rd, fixing first via clock of selecting inputs as active clock benchmark, selects the second road clock input as spare clock reference, simplifies the configuration to chip.
Clock reference system of selection provided by the invention comprises:
Fixed configurations Circuit Emulation Service equipment one tunnel (such as, the first via) TDM clock be input as active clock benchmark input, another road of configuration circuit copying equipment (such as, second tunnel) TDM clock be input as spare clock reference input, clock reference source is provided by clock reference choice device;
Clock reference takes from line side or PW side is configurable;
Can from n route trackside clock Ren Qu mono-tunnel as active clock benchmark, also can from the clock of PW side, n road Ren Qu mono-tunnel as active clock benchmark;
Can from n route trackside clock Ren Qu mono-tunnel as spare clock reference, also can from the clock of PW side, n road Ren Qu mono-tunnel as spare clock reference;
The each clock status in line side is detected and controls it and export, do not export under abnormality;
The each clock status in PW side is detected and controls it and export, do not export under abnormality.
The invention provides the system of selection of clock reference in a kind of structured circuit simulation system, comprising:
Receive multi-path line clock and pseudo-line (PW) clock of multichannel, from described multi-path line clock or multichannel PW clock, select a road to export as active clock benchmark; And, from described multi-path line clock or multichannel PW clock, select a road to export as spare clock reference.
Wherein, described method also comprises, and detects the service condition of described multi-path line clock or PW clock, controls export or do not export described line clock or PW clock according to described service condition.
Wherein, when the service condition of described multi-path line clock is abnormal, described line clock is not exported; When the service condition of described PW clock is abnormal, do not export described PW clock.
Wherein, described method also comprises, and described active clock benchmark is fixedly exported to road time division multiplexing (TDM) clock input interface of Circuit Emulation Service equipment; Described spare clock reference is fixedly exported to another road TDM clock input interface of described Circuit Emulation Service equipment.
Brief description is carried out to the thinking that the present invention proposes below.
As seen from Figure 1, Figure 2, according to the quantity of TDM interface in prior art, there is the clock input interface of respective amount, can from the clock of these quantity, select a road as active clock benchmark at chip internal, then select a road as spare clock reference.Benchmark for subsequent use can be automatically switched to after primary benchmark is lost.But this chip exists following problem in the application, at the clock that PW side is recovered from PSN, when PW breaks down, free-running clock is still had to export.If when selecting this PW clock like this as active clock benchmark, when PW traffic failure, just normal spare clock reference cannot be switched to.Also may there is similar problem in line side equally, as when on E1/T1 Interface, no signal inputs, the clock extracted from circuit also may export a free-running clock.Whether the thinking that the present invention is directed to the proposition of this problem is, control clock export according to service condition, and as in E1/T1 Interface side, once occur the alarms such as LOS, the clock RCLK that circuit extracts just does not export; In PW side, be unlock state once the DCO that PW clock is corresponding, the clock of PW side does not also export, thus solves the problem that active clock benchmark fault cannot switch to spare clock reference.
In the clock scheme provided in prior art, as Fig. 1 extracts clock as clock reference from E1/T1 line side; If Fig. 2 is as clock reference from PW side recovered clock.But it is uncertain for which direction getting clock reference from engineer applied, the scheme provided in prior art is once it is not configurable that circuit has connected in engineering.The present invention is directed to this problem, propose the configurable scheme that clock reference is got in E1/T1 line side and PW side, which adds the flexibility of engineer applied.
Below in conjunction with accompanying drawing, embodiment of the present invention are described in detail.
Apparatus embodiments
Fig. 4 is the block diagram of the structured circuit simulation system clock reference selection scheme according to present device embodiment, as shown in Figure 4, equipment is selected to comprise and CPU control interface device 409 according to the structured circuit simulation system clock reference of present device embodiment, line side clock output-controlling device 401, PW side clock output-controlling device 402 and clock selecting device, wherein clock selecting device comprises further: line side active clock selection of reference frame device 403, line side spare clock reference choice device 404, PW side active clock selection of reference frame device 405, PW side spare clock reference choice device 406, active clock datum line trackside/PW side choice device 407, spare clock reference line side/PW side choice device 408.Below above-mentioned module is described in detail.
Described CPU control interface device 409, is connected with CPU, for receiving the control signal of central processing unit, controlling described clock reference and selecting all the other each devices of equipment;
Described line side clock output-controlling device 401, for receiving the input of described multi-path line clock, according to the control of described CPU control interface device 409, exports or does not export described line clock to described clock selecting device;
Described PW side clock output-controlling device 402, for receiving the input of described multichannel PW clock, according to the control of described CPU control interface device 409, exports or does not export described PW clock to described clock selecting device;
Described clock selecting device, for the PW clock that the line clock and described PW side clock output-controlling device that receive the clock output-controlling device output of described line side export, select selection one tunnel to export as active clock benchmark, select a road to export as spare clock reference.
This structured circuit simulation system clock reference selects equipment to receive the E1/T1 line clock input of outside n road by line side clock output-controlling device 401, CPU passes through CPU control interface device 409 control line trackside clock output-controlling device 401 according to each road service condition, control clock by this device whether to export, as clock during LOS does not export.
This structured circuit simulation system clock reference selection equipment receives outside n road PW by PW side clock output-controlling device 402 and inputs from PSN recovered clock, CPU according to each road service condition by CPU control interface device 409 control PW side clock output-controlling device 402, control clock by this device whether to export, as when DCO is unlock state, clock does not export.
This structured circuit simulation system clock reference selects equipment from the n road clock that device 401 exports, to choose 1 tunnel as the output of line side active clock benchmark by line side active clock selection of reference frame device 403, and selecting to control is that CPU is realized by device 409.
This structured circuit simulation system clock reference selects equipment from the n road clock that device 401 exports, to choose 1 tunnel as the output of line side spare clock reference by line side spare clock reference choice device 404, and selecting to control is that CPU is realized by device 409.
This structured circuit simulation system clock reference selects equipment from the n road clock that device 402 exports, to choose 1 tunnel as the output of PW side active clock benchmark by PW side active clock selection of reference frame device 405, and selecting to control is that CPU is realized by device 409.
This structured circuit simulation system clock reference selects equipment from the n road clock that device 402 exports, to choose 1 tunnel as the output of PW side spare clock reference by PW side spare clock reference choice device 406, and selecting to control is that CPU is realized by device 409.
This structured circuit simulation system clock reference selects equipment from the 2 road clocks that device 403 and device 405 export, to choose 1 tunnel as the output of active clock benchmark by active clock datum line trackside/PW side choice device 407, and selecting to control is that CPU is realized by device 409.
This structured circuit simulation system clock reference selection equipment is chosen 1 tunnel by spare clock reference line side/PW side choice device 408 and is exported as spare clock reference from the 2 road clocks that device 404 and device 406 export, and selecting to control is that CPU is realized by device 409.
According to description above, structured circuit simulation system clock reference of the present invention selects equipment can realize selecting 1 tunnel to export as active clock benchmark from the n road E1/T1 line clock of input and the n road PW clock of input, and 1 tunnel also can be selected again to export as spare clock reference.
System embodiment
According to the embodiment of the present invention, additionally provide a kind of structured circuit emulation communication system.
Fig. 3 shows the structured circuit emulation communication system of system according to the invention embodiment.As shown in Figure 3, structured circuit emulation communication system according to the present invention comprises E1/T1 line interface and frame device 301, Circuit Emulation Service equipment 302, CPU control appliance 303 and present device embodiment indication clock reference select equipment 304, and Circuit Emulation Service equipment 302 can use Zarlink ZL5011xCESoP to realize.
Below the annexation between each equipment in the emulation of structured circuit shown in Fig. 3 communication system and processing procedure are described in detail.
E1/T1 line interface and frame device 301 mainly complete the effect of line signal transmitting-receiving, Clock Extraction and framing in systems in which, by TDM interface swap data between itself and Circuit Emulation Service equipment 302, TDM interface clock is provided by Circuit Emulation Service equipment, the clock RCLK<1..n> input clock selection of reference frame equipment 304 that its circuit extracts.
Circuit Emulation Service equipment 302 in the present system main completing circuit emulates the function of (CESoP), data after E1/T1 line interface and frame device 301 framing are packaged into PW grouping bag according to PW configuration, PSN network is sent to by FE/GE interface, in contrary direction, then, according to PW configuration, PW grouping bag is reverted to tdm data, recover clock, the clock TDM CLKO<1..n> input clock selection of reference frame equipment 304 recovered simultaneously.In addition Circuit Emulation Service equipment 302 also have an important function be select equipment 304 to provide according to clock reference master/backup clock benchmark by the various clocks needed for the phase-locked rear generation system of phase-locked loop, comprise the clock of CESoP equipment self needed for TDM interface and export to the clock of E1/T1 line interface and frame device 301.Master/backup clock benchmark can automatically switch to the opposing party when side's fault in addition.
CPU control appliance 303 mainly controls the effect of each equipment in native system, and has control interface between each equipment.
Clock reference selection equipment 304 is the equipment of present device embodiment indication, and its Main Function with reference to the said equipment embodiment, can repeat no more.
The configuration selected the following detailed description of clock reference in said structure circuit simulation communication system and the handling process of operating state.
Based on the system shown in Fig. 3, Fig. 5 and Fig. 6 shows clock reference in the structured circuit emulation communication system of system according to the invention embodiment and selects the configuration flow of equipment, wherein Fig. 5 is the configuration flow of active clock benchmark, and as shown in Figure 5, concrete processing procedure comprises the steps.
Step 501, software is input as active clock benchmark by the road of Circuit Emulation Service equipment 302 the 1st shown in CPU control interface allocation plan 3 TDM clock;
Step 502, software is by CPU control interface configuration active clock datum line trackside/PW side selection mode, corresponding diagram 4 shown device 407, determine that clock source is from line side or PW side, the clock chosen exports to the equipment of Circuit Emulation Service shown in Fig. 3 302 as active clock benchmark;
Step 503, judges the state that step 502 configures, if take from line side clock, then forwards step 504 to, if take from PW side clock, then forward step 505 to;
Step 504, software is by CPU control interface layout line trackside active clock selection of reference frame state, and corresponding diagram 4 shown device 403, can choose 1 tunnel as line side active clock benchmark from the input of n road line clock;
Step 505, software is by CPU control interface configuration PW side active clock selection of reference frame state, and corresponding diagram 4 shown device 405, can choose 1 tunnel as PW side active clock benchmark from the input of n road PW clock.
After step 504 or step 505 complete, namely primary selection of reference frame configuration completes.
Fig. 6 is the configuration flow of spare clock reference, and as shown in Figure 6, concrete processing procedure comprises the steps.
Step 601, software is input as spare clock reference by the road of Circuit Emulation Service equipment 302 the 2nd shown in CPU control interface allocation plan 3 TDM clock;
Step 602, software is by CPU control interface configuration spare clock reference line side/PW side selection mode, corresponding diagram 4 shown device 408, determine that clock source is from line side or PW side, the clock chosen exports to the equipment of Circuit Emulation Service shown in Fig. 3 302 as spare clock reference;
Step 603, judges the state that step 602 configures, if take from line side clock, then forwards step 604 to, if take from PW side clock, then forward step 605 to;
Step 604, software is by CPU control interface layout line trackside spare clock reference selection mode, and corresponding diagram 4 shown device 404, can choose 1 tunnel as line side spare clock reference, terminate from the input of n road line clock;
Step 605, software is by CPU control interface configuration PW side spare clock reference selection mode, and corresponding diagram 4 shown device 406, can choose 1 tunnel as PW side spare clock reference from the input of n road PW clock.
After step 604 or step 605 complete, namely selection of reference frame configuration for subsequent use completes.
By the operation of step shown in above-mentioned Fig. 5 and Fig. 6, software just completes the layoutprocedure that clock reference is selected.
Except the configuration of above-mentioned clock reference, clock reference of the present invention is selected equipment also to need to detect each clock status in line side and PW side and controls it according to state to export.Below detection control process is described in detail.
Based on the system shown in Fig. 3, Fig. 7 shows clock reference in the structured circuit emulation communication system of system according to the invention embodiment and selects the Monitoring and Controlling flow process of each clock source state in device line side, as shown in Figure 7, concrete processing procedure comprises the steps:
Step 701, first software scan from the 1st road E1/T1 circuit, judges whether it has LOS alarm, if then forward step 702 to, then forward step 703 to if not;
Step 702, there is LOS alarm in E1/T1 circuit, this clock source is unavailable, and software, by line side clock output-controlling device 401 shown in CPU control interface control chart 4, is closed this road line clock and exported, go to step 704;
Step 703, E1/T1 circuit does not have LOS alarm, and this clock source can be used, and software, by line side clock output-controlling device 401 shown in CPU control interface control chart 4, is opened this road line clock and exported;
Whether step 704, after completing above-mentioned steps 702 or 703, need judge whether the Monitoring and Controlling scanning having completed all each roads clock source state, be namely last 1 tunnel, if so, terminated present scan; If not, lower 1 tunnel is pointed in address, proceeds the Monitoring and Controlling scanning process of the clock source state on all each road from step 701 to step 704.
Software need Open Timer device process carry out detection control scanning by above-mentioned steps timing cycle to each clock source state in line side.
Based on the system shown in Fig. 3, Fig. 8 shows clock reference in the structured circuit emulation communication system of system according to the invention embodiment and selects the Monitoring and Controlling flow process of each clock source state in equipment PW side, and as shown in Figure 8, concrete processing procedure comprises the steps.
Step 801, first software scan from the 1st road PW, judges whether its DCO is lock-out state, then forwards step 802 to if not, if then forward step 803 to;
Step 802, PW clock DCO is unlock state, and this clock source is unavailable, and software, by PW side clock output-controlling device 402 shown in CPU control interface control chart 4, is closed this road PW clock and exported, go to step 804;
Step 803, PW clock DCO is lock-out state, and this clock source can be used, and software, by PW side clock output-controlling device 402 shown in CPU control interface control chart 4, is opened this road PW clock and exported;
Whether step 804, after completing above-mentioned steps 802 or 803, need judge whether the Monitoring and Controlling scanning of the clock source state having completed all each roads, be namely last 1 tunnel, if so, terminated present scan; If not, lower 1 tunnel is pointed in address, proceeds the Monitoring and Controlling scanning process of the clock source state on all each road from step 801 to step 804.
The same with the detection in line side, software need Open Timer device process carry out detection control scanning by above-mentioned steps timing cycle to each clock source state in PW side.
In sum, select equipment and structured circuit emulation communication system by clock reference provided by the invention, the flexible configuration of clock reference can be realized, realize the pretection switch of main/stand-by clock benchmark, improve the reliability of system.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the clock reference in structured circuit simulation system selects an equipment, it is characterized in that, described clock reference selects equipment to be used for:
Receive multi-path line clock and multichannel pseudo-line PW clock, from described multi-path line clock or multichannel PW clock, select a road to export as active clock benchmark; And, from described multi-path line clock or multichannel PW clock, select a road to export as spare clock reference;
Clock reference selects equipment to comprise central processing unit control interface device, line side clock output-controlling device and PW side clock output-controlling device and clock selecting device, wherein:
Described central processing unit control interface device, is connected with outside central processing unit, for receiving the control signal that central processing unit is made according to service condition, controlling described clock reference and selecting all the other each devices of equipment;
Described line side clock output-controlling device, for receiving the input of described multi-path line clock, according to the control of described central processing unit control interface device, exports or does not export described line clock to described clock selecting device;
Described PW side clock output-controlling device, for receiving the input of described multichannel PW clock, according to the control of described central processing unit control interface device, exports or does not export described PW clock to described clock selecting device;
Described clock selecting device, for the PW clock that the line clock and described PW side clock output-controlling device that receive the clock output-controlling device output of described line side export, select a road to export as active clock benchmark, select a road to export as spare clock reference.
2. clock reference as claimed in claim 1 selects equipment, it is characterized in that, described central processing unit control interface device, for when the service condition of described line clock input is abnormal, controls described line side clock output-controlling device and does not export described line clock; When the service condition of described PW clock input is abnormal, controls described PW side clock output-controlling device and do not export described line clock.
3. clock reference as claimed in claim 1 selects equipment, it is characterized in that, described clock selecting device comprises: line side active clock selection of reference frame device, line side spare clock reference choice device, PW side active clock selection of reference frame device, PW side spare clock reference choice device, active clock choice device and standby clock choice device, wherein:
Described line side active clock selection of reference frame device, be connected with described line side clock output-controlling device, for the control according to central processing unit control interface device, from the line clock that described line side clock output-controlling device exports, a road is selected to export as line side active clock benchmark;
Described line side spare clock reference choice device, be connected with described line side clock output-controlling device, for the control according to central processing unit control interface device, from the line clock that described line side clock output-controlling device exports, a road is selected to export as line side spare clock reference;
Described PW side active clock selection of reference frame device, be connected with described PW side clock output-controlling device, for the control according to central processing unit control interface device, from the PW clock that described PW side clock output-controlling device exports, a road is selected to export as PW side active clock benchmark;
Described PW side spare clock reference choice device, be connected with described PW side clock output-controlling device, for the control according to central processing unit control interface device, from the PW clock that described PW side clock output-controlling device exports, a road is selected to export as PW side spare clock reference;
Described active clock choice device, for the control according to central processing unit control interface device, from the two-way clock that described line side active clock selection of reference frame device and described PW side active clock selection of reference frame device export, a road is selected to export as active clock benchmark;
Described standby clock choice device, for the control according to central processing unit control interface device, from the two-way clock that described line side spare clock reference choice device and described PW side spare clock reference choice device export, a road is selected to export as spare clock reference.
4. a structured circuit simulation system, it is characterized in that, described system comprises: central processing unit control appliance, E1/T1 line interface and frame device, Circuit Emulation Service equipment and as arbitrary in claims 1 to 3 as described in clock reference select equipment, described clock reference selects equipment and central processing unit control appliance, E1/T1 line interface and frame device, Circuit Emulation Service equipment is connected, described clock reference selects equipment to be used for receiving the input of multi-path line clock from described E1/T1 line interface and frame device and receiving the input of multichannel PW clock from described Circuit Emulation Service equipment, export a road active clock benchmark and a road spare clock reference extremely described Circuit Emulation Service equipment.
5. system as claimed in claim 4, is characterized in that, described clock reference selects equipment to be used for described active clock benchmark fixedly to export to a road time division multiplexing tdm clock input interface of described Circuit Emulation Service equipment; Described spare clock reference is fixedly exported to another road TDM clock input interface of described Circuit Emulation Service equipment.
6. the system of selection of clock reference in structured circuit simulation system, is characterized in that, comprising:
The service condition of multi-path line clock or multichannel pseudo-line PW clock is detected, controls export or do not export described line clock or PW clock according to described service condition;
Receive described multi-path line clock and multichannel pseudo-line PW clock, the control signal according to outside central processing unit selects a road to export as active clock benchmark from described multi-path line clock or multichannel PW clock; And, from described multi-path line clock or multichannel PW clock, select a road to export as spare clock reference.
7. method as claimed in claim 6, is characterized in that, when the service condition of described multi-path line clock or PW clock is abnormal, does not export described line clock or PW clock.
8. method as claimed in claims 6 or 7, it is characterized in that, described method also comprises:
Described active clock benchmark is fixedly exported to a road time division multiplexing tdm clock input interface of Circuit Emulation Service equipment; Described spare clock reference is fixedly exported to another road TDM clock input interface of described Circuit Emulation Service equipment.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010239161.8A CN101895360B (en) | 2010-07-23 | 2010-07-23 | Structured circuit simulation system, selection method and device of clock reference thereof |
| PCT/CN2011/075134 WO2012010014A1 (en) | 2010-07-23 | 2011-06-02 | Structured circuit emulation system and selection method and apparatus of a clock reference thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010239161.8A CN101895360B (en) | 2010-07-23 | 2010-07-23 | Structured circuit simulation system, selection method and device of clock reference thereof |
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| CN101895360A CN101895360A (en) | 2010-11-24 |
| CN101895360B true CN101895360B (en) | 2015-06-10 |
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| CN101895360B (en) * | 2010-07-23 | 2015-06-10 | 中兴通讯股份有限公司 | Structured circuit simulation system, selection method and device of clock reference thereof |
| CN112950978B (en) * | 2021-02-04 | 2022-07-12 | 伟龙科技(广东)有限公司 | Vehicle positioning method and device based on road side equipment and related equipment |
| CN113177019B (en) * | 2021-04-25 | 2022-08-09 | 山东英信计算机技术有限公司 | Switch board and server |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921371A (en) * | 2005-08-26 | 2007-02-28 | 上海贝尔阿尔卡特股份有限公司 | Synchronised clock providing device and realizing method |
| CN101345763A (en) * | 2007-12-27 | 2009-01-14 | 华为技术有限公司 | Method and apparatus for extracting clock, and network communication equipment |
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| CN101136711B (en) * | 2007-09-29 | 2011-11-23 | 中兴通讯股份有限公司 | Optical terminal service, clock, cross service high integration veneer service smooth switch system of SDH system |
| CN101184040B (en) * | 2007-12-06 | 2010-09-22 | 中兴通讯股份有限公司 | Router and method of implementing circuit simulation applying the router |
| US7821958B2 (en) * | 2007-12-21 | 2010-10-26 | Belair Networks Inc. | Method for estimating and monitoring timing errors in packet data networks |
| CN101895360B (en) * | 2010-07-23 | 2015-06-10 | 中兴通讯股份有限公司 | Structured circuit simulation system, selection method and device of clock reference thereof |
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| CN1921371A (en) * | 2005-08-26 | 2007-02-28 | 上海贝尔阿尔卡特股份有限公司 | Synchronised clock providing device and realizing method |
| CN101345763A (en) * | 2007-12-27 | 2009-01-14 | 华为技术有限公司 | Method and apparatus for extracting clock, and network communication equipment |
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| WO2012010014A1 (en) | 2012-01-26 |
| CN101895360A (en) | 2010-11-24 |
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