CN113177019B - Switch board and server - Google Patents
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- CN113177019B CN113177019B CN202110450251.XA CN202110450251A CN113177019B CN 113177019 B CN113177019 B CN 113177019B CN 202110450251 A CN202110450251 A CN 202110450251A CN 113177019 B CN113177019 B CN 113177019B
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- 239000000872 buffer Substances 0.000 claims description 26
- 238000011144 upstream manufacturing Methods 0.000 claims description 17
- 230000004044 response Effects 0.000 claims description 6
- 238000013461 design Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000014509 gene expression Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The invention discloses a switch board, comprising: the system comprises a plurality of uplink ports, a plurality of control units and a plurality of control units, wherein the uplink ports are used for connecting a mainboard; the clock source generates a first clock signal of the switch board; the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal; each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive a first clock signal; each switch module is also connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and a processed reset signal; the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal. The invention also provides a server.
Description
Technical Field
The invention relates to the field of servers, in particular to a switch board and a server.
Background
In the design of the mainboard, because the Intel adopts the PCH, and the AMD and the sea light do not have the PCH, the difference exists between the Intel and the PCIe in the design of the multi-path server. Specifically, on the Intel motherboard, all 100M clock and Reset signals of PCIe devices under the CPU may come from the PCH; on AMD, the glad mainboard, each CPU provides the PCIe device with the clock and Reset signals, and the PCIe devices under different CPUs cannot use the clock and Reset signals in a mixed way.
As shown in fig. 1, taking a single-layer double Switch design as an example, each Switch and its associated devices such as upstream interface, VR, Clock, etc. are considered as a whole and named as a domain. CPLD and BMC are integrated on the Switch board as board public resources, and power supply, Reset, equipment information and the like of the whole board are managed. After the computer is started, all the switches are powered on at the same time, and the power-on time sequences are unified.
The two uplink ports are generally connected with a machine head mainboard through cables, and Reset signals of the machine head can be connected to a Switch board, wherein the difference is that when an Intel mainboard is matched, a CPLD (complex programmable logic device) needs to carry out logical operation on the two Reset signals, and then the Reset of equipment is generated; when the AMD mainboard and the aureole mainboard are matched, the CPLD needs to respectively judge two Reset signals so as to generate the Reset signals of respective devices under two domains. The same motherboard's Clock signal can also be connected to the Switch board through a cable, or PCIe Clock can be generated directly using the Generator on the Switch board, given to the Switch and downstream devices through buffers. The difference is that when the AMD mainboard is matched, the Clock of different CPUs needs to use Buffer extension respectively and correspondingly connect to corresponding equipment, but the Intel mainboard does not have the requirement. In addition, the handpiece can access the Switch board BMC through the uplink interface and the link I2C for information interaction.
As described above, the existing design does not consider the use requirements of different platforms in terms of Reset and Clock processing, and the PCIe resource expansion also causes a certain waste of resources due to idle:
(1) when different platforms are matched, the logic of processing Reset by the CPLD is different and the Clock is not distinguished according to different CPU domains, so that the same Switch board cannot be reused.
(2) The power supply units are not distinguished, and can not be used for independently powering on and powering off different domains.
(3) Only one handpiece mainboard I2C is connected, and the design of connecting a plurality of handpieces cannot be considered.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a switch board, including:
a plurality of upstream ports for connecting to a motherboard;
the clock source generates a first clock signal of the switch board;
the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive the first clock signal; each switch module is further connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and the processed reset signal;
wherein the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal.
In some embodiments, the switch board further comprises a plurality of downstream ports, each of the switch modules comprising a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
In some embodiments, each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port;
in some embodiments, the voltage regulation module is further connected to the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
In some embodiments, the controller is further configured to, in response to that the received identifiers sent by the plurality of uplink ports are the same and are a first preset identifier, and the reset signals sent by the plurality of uplink ports to obtain the processed reset signal.
Based on the same inventive concept, an embodiment of the present invention further provides a server, including a plurality of switch boards and a plurality of main boards, where the main boards include a plurality of downlink ports, and the switch boards include:
a plurality of upstream ports connected to downstream ports of the motherboard;
the clock source generates a first clock signal of the switch board;
the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive the first clock signal; each switch module is further connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and the processed reset signal;
wherein the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal.
In some embodiments, the switch board further comprises a plurality of downstream ports, each of the switch modules comprising a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
In some embodiments, each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port;
in some embodiments, the voltage regulation module is further connected to the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
In some embodiments, the controller is further configured to, in response to that the received identifiers sent by the plurality of uplink ports are the same and are the first preset identifier, and the reset signals sent by the plurality of uplink ports to obtain processed reset signals.
The invention has one of the following beneficial technical effects: the scheme provided by the embodiment of the invention can consider PCIe design requirements of different platforms and ensure that the Switch board can be matched with a plurality of platform mainboards for use. And meanwhile, the existing design is optimized, so that the Switch board can be matched with a plurality of machine head main boards, the power-on and power-off and board card management communication functions are realized respectively, and the utilization rate of Switch resources is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a diagram of a prior art switch board;
FIG. 2 is a diagram of a switch board provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of a connection between a switch board and a motherboard according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to one aspect of the present invention, an embodiment of the present invention provides a switch board, as shown in fig. 1, including: a plurality of upstream ports 1, the upstream ports 1 being used for connecting a motherboard;
the clock source 2 is used for generating a first clock signal of the switch board;
the controller 3 is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
a plurality of switch modules 4, wherein each switch module 4 is connected with the corresponding uplink port 1 to receive a second clock signal sent by a mainboard connected with the corresponding uplink port 1; each switch module 4 is further connected to the clock source 2 to receive the first clock signal; each switch module 4 is further connected to the controller 3 to receive the control signal generated by the controller 3 based on the corresponding uplink port 1 and the processed reset signal;
wherein the switch module 4 selects the first clock signal or the second clock signal as the final clock signal based on the control signal.
The scheme provided by the embodiment of the invention can consider PCIe design requirements of different platforms and ensure that the Switch board can be matched with a plurality of platform mainboards for use. And meanwhile, the existing design is optimized, so that the Switch board can be matched with a plurality of machine head main boards, the power-on and power-off and board card management communication functions are realized respectively, and the utilization rate of Switch resources is improved.
In some embodiments, the switch board further comprises a plurality of downstream ports, each of the switch modules 4 comprises a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
In some embodiments, each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port;
in some embodiments, the voltage regulation module is further connected to the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
In some embodiments, the controller is further configured to, in response to that the received identifiers sent by the plurality of uplink ports are the same and are the first preset identifier, and the reset signals sent by the plurality of uplink ports to obtain processed reset signals.
The following describes the switch board according to the embodiment of the present invention in detail by taking the switch board shown in fig. 2 as an example.
The switch board shown in FIG. 2 includes 4 switch modules shown in FIG. 2, each of which includes one clock buffer (buf _ A, buf _ B, buf _ C, buf _ D), one VR (VR _ A, VR _ B, VR _ C, VR _ D) and one switch chip (switch A, switch B, switch C, switch D').
The uplink port of the switch board can be connected to the handpiece main board through a cable by using a MiniSAS HD high-speed connector and the like. And each upstream interface can design three sideband signals of PCIE _ RST _ N, 100M _ CLK and I2C. Reset is connected to the CPLD controller on the Switch board, I2C is respectively connected to 4 paths of I2C interfaces of the BMC controller of the Switch board, and Clock is connected to one of four inputs of 2-to-1 Clock Buffer.
The clock source (CLK GEN) generates 4 clock signals respectively connected to the other input signals of the 4 clock buffers.
Each Switch, the downlink port and the equipment are provided with independent power supply VRs, and the CPLD controls corresponding enabling signals to control each domain to be powered up and down independently.
The machine head mainboard and the Switch board are interconnected through I2C, and after the machine head BMC is scanned to the Switch board BMC after being electrified, the information of the self board card PN and QN is transmitted to the Switch board. The Switch board BMC can judge whether the current connected main board is an Intel platform or an AMD or sea light platform by comparing PN and QN information received by 4 uplink I2C links; the same mainboard or a plurality of mainboards. Therefore, the CPLD is informed of the corresponding information, and according to the corresponding information, the CPLD controls each clock buffer, can select the independent clock of the Switch board, can also select the clock from the main board, and simultaneously controls whether to enable the output of the buffer and determines the processing logic of the Reset signal.
For example, when the upstream port A, B is connected to the same Intel motherboard, the upstream port C, D is connected to an AMD motherboard. The Switch board BMC stores the information of the corresponding board card PN and QN, so as to judge the processing mode of the Reset signal.
After being powered on, the BMC on the Switch board receives PN and QN information sent by the mainboard through Port A and B, C, D four paths of I2C, and transmits the information related to the mainboard to the CPLD of the Switch board after comparison and judgment. The program on the CPLD can confirm that the upstream port A, B is connected to an Intel motherboard and the upstream port C, D is connected to an AMD motherboard, and then logically and-operate the RST _ a/B transmitted by the upstream port A, B, and regard the switch module connected to the upstream port A, B as a whole to control the simultaneous enabling of the corresponding clock and VR. And respectively processing RST _ C, RST _ D sent by the uplink port C, D, and respectively controlling corresponding VR and buffer to be enabled in sequence.
The Switch board provided by the embodiment of the invention has more resources, and 4 uplink ports can be flexibly matched with the machine head mainboard to carry out power-on and power-off control, so that all PCIe resources can be fully utilized. And the port which is not used temporarily can be kept in a standby state, so that the power consumption is saved.
Based on the same inventive concept, an embodiment of the present invention further provides a server, including a plurality of switch boards and a plurality of motherboards of the same model and/or different models, where the motherboard includes a plurality of downlink ports, and the switch boards include:
a plurality of upstream ports connected to downstream ports of the motherboard;
the clock source generates a first clock signal of the switch board;
the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive the first clock signal; each switch module is further connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and the processed reset signal;
wherein the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal.
In some embodiments, the switch board further comprises a plurality of downstream ports, each of said switch modules comprising a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
In some embodiments, each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port;
in some embodiments, the voltage regulation module is further connected to the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
In some embodiments, the controller is further configured to, in response to that the received identifiers sent by the plurality of uplink ports are the same and are the first preset identifier, and the reset signals sent by the plurality of uplink ports to obtain processed reset signals.
The scheme provided by the embodiment of the invention can consider PCIe design requirements of different platforms and ensure that the Switch board can be matched with a plurality of platform mainboards for use. And meanwhile, the existing design is optimized, so that the Switch board can be matched with a plurality of machine head main boards, the power-on and power-off and board card management communication functions are realized respectively, and the utilization rate of Switch resources is improved.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A switch board, comprising:
a plurality of upstream ports for connecting to a motherboard;
the clock source generates a first clock signal of the switch board;
the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive the first clock signal; each switch module is further connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and the processed reset signal;
wherein the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal.
2. The switch board of claim 1, wherein switch board further comprises a plurality of downstream ports, each of said switch modules comprising a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
3. The switch board of claim 2, wherein each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port.
4. The switch board of claim 3, wherein the voltage regulation module is further connected with the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
5. The switch board of claim 1, wherein the controller is further configured to, in response to the received identities transmitted by the plurality of upstream ports being the same and a first predetermined identity, and to AND the reset signals transmitted by the plurality of upstream ports to obtain a processed reset signal.
6. The utility model provides a server, its characterized in that includes a plurality of switch board and a plurality of mainboard, the mainboard includes a plurality of downstream port, the switch board includes:
a plurality of upstream ports connected to downstream ports of the motherboard;
the clock source generates a first clock signal of the switch board;
the controller is connected with each uplink port to receive the reset signal and the identification code sent by the mainboard, generate a control signal based on the identification code of the mainboard and process the reset signal by using the control signal;
each switch module is connected with the corresponding uplink port to receive a second clock signal sent by the mainboard connected with the corresponding uplink port; each switch module is also connected with the clock source to receive the first clock signal; each switch module is further connected with the controller to receive a control signal generated by the controller based on the corresponding uplink port and the processed reset signal;
wherein the switch module selects the first clock signal or the second clock signal as a final clock signal based on the control signal.
7. The server of claim 6, wherein a switch board further comprises a plurality of downstream ports, each of the switch modules comprising a clock buffer and a switch chip;
the clock buffer receives the first clock signal and the second clock signal to select the first clock signal or the second clock signal as a final clock signal based on the control signal;
the switch chip is connected with the corresponding downlink port;
wherein the clock buffer further inputs the final clock signal to the switch chip and a corresponding downstream port.
8. The server of claim 7, wherein each of the switch modules further comprises a voltage regulation module connected to the switch chip and the corresponding downstream port.
9. The server of claim 8, wherein the voltage regulation module is further connected to the controller to cause the controller to control the voltage regulation module to be enabled based on an enable signal.
10. The server according to claim 6, wherein the controller is further configured to, in response to that the received identifiers sent by the plurality of uplink ports are the same and are the first preset identifier, and perform an and operation on the reset signals sent by the plurality of uplink ports to obtain the processed reset signals.
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| CN202110450251.XA CN113177019B (en) | 2021-04-25 | 2021-04-25 | Switch board and server |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2008200472A1 (en) * | 2000-11-20 | 2008-02-21 | Sca Ipla Holdings, Inc. | Systems and methods for preventing unauthorized use of digital content related applications |
| CN204406395U (en) * | 2015-02-13 | 2015-06-17 | 成都爱斯顿科技有限公司 | A kind of high speed communication interacted system of CPCI framework |
| CN110781130A (en) * | 2019-10-16 | 2020-02-11 | 广东高云半导体科技股份有限公司 | System on chip |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7457974B2 (en) * | 2005-09-08 | 2008-11-25 | International Business Machines Corporation | Dynamically changing PCI clocks |
| CN101895360B (en) * | 2010-07-23 | 2015-06-10 | 中兴通讯股份有限公司 | Structured circuit simulation system, selection method and device of clock reference thereof |
| KR102507714B1 (en) * | 2016-05-02 | 2023-03-09 | 삼성전자주식회사 | PCIe DEVICE FOR SUPPORTING SRIS |
| US10671560B2 (en) * | 2017-09-27 | 2020-06-02 | Hewlett Packard Enterprise Development Lp | Serial connection between management controller and microcontroller |
| CN112069121A (en) * | 2020-08-21 | 2020-12-11 | 苏州浪潮智能科技有限公司 | MCU control GPU server Switch board system and control method |
-
2021
- 2021-04-25 CN CN202110450251.XA patent/CN113177019B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2008200472A1 (en) * | 2000-11-20 | 2008-02-21 | Sca Ipla Holdings, Inc. | Systems and methods for preventing unauthorized use of digital content related applications |
| CN204406395U (en) * | 2015-02-13 | 2015-06-17 | 成都爱斯顿科技有限公司 | A kind of high speed communication interacted system of CPCI framework |
| CN110781130A (en) * | 2019-10-16 | 2020-02-11 | 广东高云半导体科技股份有限公司 | System on chip |
Non-Patent Citations (2)
| Title |
|---|
| 《High channel count ultrasound beamformer system with external multiplexer support for ultrafast 3D/4D ultrasound》;Christoph Risser;《2016 IEEE International Ultrasonics Symposium (IUS)》;20161231;第1页-第4页 * |
| 《边界扫描JTAG控制器设计及实现》;邬子婴;《航空电子技术》;20160315(第1期);第31页-第35页 * |
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