CN105790872B - A kind of network clock synchronous device and its working method - Google Patents
A kind of network clock synchronous device and its working method Download PDFInfo
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- CN105790872B CN105790872B CN201410829183.8A CN201410829183A CN105790872B CN 105790872 B CN105790872 B CN 105790872B CN 201410829183 A CN201410829183 A CN 201410829183A CN 105790872 B CN105790872 B CN 105790872B
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- Prior art keywords
- clock
- access device
- recovery portion
- clock recovery
- data access
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J14/00—Optical multiplex systems
- H04J14/02—Wavelength-division multiplex systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
The present invention provides a kind of network clock synchronous device and its working method, is related to network technique field, network clocking poor synchronization when solving the problems, such as external data abnormal interrupt in the prior art.Described device includes: clock recovery portion and clock gate portion, the clock recovery portion, and one end is connected with network data access device, and the other end is connected with the clock gate portion, and the data for being passed to using the network data access device recover line clock；The clock gate portion, its first input end is connected with the clock recovery portion, second input terminal is connected with the network data access device, output end is connected with phaselocked loop, for: when the network data access device interrupts and transmits data to the clock recovery portion, the line clock that the clock recovery portion is voluntarily transmitted to the phaselocked loop is truncated.
Description
Technical field
The present invention relates to Internet technical fields, more particularly to a kind of network clock synchronous device and its working method.
Background technique
Wireless application needs the clock frequency of communication network to have good synchronism, for example, IP RAN (IP wireless access
Network, IP Radio Access Networks) frequency between different base station must synchronize within certain precision, otherwise
Business will appear when base station switches to go offline, and influences using normal use.
In the prior art, the clock between synchronous ethernet equipment is synchronous, generallys use from the bitstream data of port
Restore the method for line clock to realize that the transmitting of clock restores the signal pipe of line clock when port data disconnecting
Foot can export the clock that but phase identical as regular link clock frequency generates offset therewith, need until software inquiry port is different
Clock could be switched to it according to SSM (Synchronization Status Message Synchronization Status Message) algorithm after often
His Back Up Source.Since software operation is all often Millisecond, in this period, system can all be in asynchronous regime, right
Synchronous service, which will cause, to be seriously affected.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of network clock synchronous device and its working methods, to solve
In the prior art when external data abnormal interrupt the problem of network clocking poor synchronization.
On the one hand, the present invention provides a kind of network clock synchronous device, comprising: clock recovery portion and clock gate portion, institute
Clock recovery portion is stated, one end is connected with network data access device, and the other end is connected with the clock gate portion, for utilizing institute
It states the incoming data of network data access device and recovers line clock；The clock gate portion, first input end with it is described
Clock recovery portion is connected, and the second input terminal is connected with the network data access device, and output end is connected with phaselocked loop, is used for:
The network data access device to the clock recovery portion transmit data when, by the clock recovery portion export route when
The transmitting of phaselocked loop described in clockwise；When the network data access device interrupts and transmits data to the clock recovery portion, truncation
The line clock that the clock recovery portion is voluntarily transmitted to the phaselocked loop, so that the phaselocked loop keeps the line before data outage
Road clock.
Optionally, the network data access device includes optical module, and the clock recovery portion includes physical chip.
Optionally, the dropout LOS pin of second input terminal with the optical module in the clock gate portion is connected.
Optionally, the clock gate portion includes detection module and gating module interconnected, wherein the detection mould
Block is connected with the network data access device, and the gating module is connected with the clock recovery portion.
Optionally, the clock gate portion is combinational logic circuit.
Further, frequency division department, the clock gate portion are additionally provided between the clock gate portion and the phaselocked loop
It is connected by the frequency division department with the phaselocked loop, the frequency division department is used for, the clock division that the clock gate portion is exported.
Further, frequency division department is additionally provided between the clock recovery portion and the clock gate portion, the clock is extensive
Multiple portion is connected by the frequency division department with the clock gate portion, and the frequency division department is used for, by clock recovery portion output
The clock gate portion is transferred to after clock division.
On the other hand, the present invention also provides the working methods of the network clock synchronous device, comprising: detects the net
Network data access device whether to the clock recovery portion transmit data；It is extensive to the clock in the network data access device
When multiple portion's transmission data, the line clock that the clock recovery portion exports is transmitted to the phaselocked loop；In the network data
Access device interrupt to the clock recovery portion transmit data when, be truncated the clock recovery portion voluntarily to the phaselocked loop transmit
Line clock so that the phaselocked loop keep data outage before line clock.
Optionally, the network data access device includes optical module；The detection network data access device is
It is no to clock recovery portion transmission data include: to detect the net by detecting the dropout LOS pin of the optical module
Network data access device whether to the clock recovery portion transmit data.
Network clock synchronous device provided in an embodiment of the present invention and its working method, clock recovery portion can utilize network
The incoming data of data access device recover line clock；It clock gate portion can be extensive to clock in network data access device
When multiple portion's transmission data, the line clock that clock recovery portion is exported is transmitted to phaselocked loop, is interrupted in network data access device
When transmitting data to clock recovery portion, the line clock that truncation clock recovery portion is voluntarily transmitted to phaselocked loop, to make phaselocked loop
Line clock before keeping data outage.Since clock gate portion is directly connected with network data access device, can obtain in real time
The data output state of Hownet network data access device, so as to the first of the output interruption of network data access device data
The line clock for the mistake that clock recovery portion is voluntarily transmitted to phaselocked loop is truncated in time in time, and phaselocked loop is made to continue to keep original
Clock output, the case where avoiding phaselocked loop output error clock, effectively increase the synchronism of network clocking.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of network clock synchronous device provided in an embodiment of the present invention；
Fig. 2 is another structural schematic diagram of network clock synchronous device provided in an embodiment of the present invention；
Fig. 3 is another structural schematic diagram of network clock synchronous device provided in an embodiment of the present invention；
Fig. 4 is network clock synchronous device provided in an embodiment of the present invention yet another construction schematic diagram again；
Fig. 5 is a kind of flow chart of the working method of network clock synchronous device provided in an embodiment of the present invention；
Fig. 6 is a kind of detail flowchart of the working method of network clock synchronous device provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing, the present invention is described in detail.It should be appreciated that specific embodiment described herein is only
To explain the present invention, the present invention is not limited.
As shown in Figure 1, the embodiment of the present invention provides a kind of network clock synchronous device, comprising: clock recovery portion 11 and when
Clock strobe portion 12；Clock recovery portion 11, one end are connected with network data access device 13, the other end and 12 phase of clock gate portion
Even, the data for being passed to using network data access device 13 recover line clock；Clock gate portion 12, the first input
End is connected with clock recovery portion 11, and the second input terminal is connected with network data access device 13, and output end is connected with phaselocked loop 14,
For: when network data access device 13 transmits data to clock recovery portion 11, when the route that clock recovery portion 11 is exported
Clockwise phaselocked loop 14 transmits；When network data access device 13 interrupts and transmits data to clock recovery portion 11, truncation clock is extensive
The line clock for the mistake that multiple portion 11 is voluntarily transmitted to phaselocked loop 14, when so that phaselocked loop 14 keeping the route before data outage
Clock.
Network clock synchronous device provided in an embodiment of the present invention includes clock recovery portion 11 and clock gate portion 12；Wherein
Clock recovery portion 11 can recover line clock using the data that network data access device 13 is passed to；12 energy of clock gate portion
Enough line clocks that when network data access device 13 transmits data to clock recovery portion 11, clock recovery portion 11 is exported to
Phaselocked loop 14 transmits, and when network data access device 13 interrupts and transmits data to clock recovery portion 11, clock recovery portion is truncated
11 line clocks voluntarily transmitted to phaselocked loop 14, so that phaselocked loop 14 be made to keep the line clock before data outage.Due to when
Clock strobe portion 12 is directly connected with network data access device 13, can know that the data of network data access device 13 are defeated in real time
It does well, so as to the first time interrupted in the output of 13 data of network data access device, clock recovery portion is truncated in time
11 line clocks voluntarily transmitted to phaselocked loop 14, make phaselocked loop 14 continue to keep original clock output, avoid phaselocked loop
The case where 14 output error clock, effectively increases the synchronism of network clocking.
In network communication protocol, clock recovery can be completed by the circuit or chip of physical layer, therefore, clock recovery
Portion 11 can specifically include physical chip.Optionally, network data access device 13 can access external network to be any
To the equipment of local network, correspondingly, clock gate portion 12 can also by with various types of network data access devices 13
It is connected and detects whether corresponding data output is normal in time.For example, if external network is to be passed to local network by optical fiber
Network, then network data access device 13 may include optical module, for the mutual conversion between optical signal and electric signal.By
In optical module all have dropout LOS pin, output LOS signal be also it is general in communication standard, in order to reinforce
Versatility, it is preferred that second input terminal in clock gate portion 12 can be connected with the dropout LOS pin of optical module.LOS pipe
The LOS signal of foot output can reflect that optical module receives the state of optical signal in real time, and light is reflected in the form of level signal
On the electrical interface of module, it is normal that low level represents route optical signal, and high level represents alarm route optical signal and loses.LOS signal
It is a signal defined in optical module standard, each producer's optical module definition is all identical, therefore uses optical module as route
The advantage that state monitoring module has versatility good, simple and convenient.
Specifically, clock gate portion 12 can be made of various forms of circuit structures or module, circuit structure is simpler
It is single, it reacts faster, more clock recovery portion 11 can be truncated in time voluntarily to phaselocked loop when network data access device 13 interrupts
The line clock of 14 transmitting.For example, as shown in Fig. 2, in one embodiment of the invention, clock gate portion 12 may include phase
The detection module 121 and gating module 122 to connect, wherein detection module 121 is connected with network data access device 13, choosing
Logical module 122 is connected with clock recovery portion 11.Gating module 122 is responsible for control line-recovered clock on-off, external connection one
Road input clock signal exports clock all the way, while being connected with detection module, and gating module 122 is in the normal feelings of line status
It is remained turned on always under condition, when outside line abnormal interrupt, gating module 122 can carry out self-test receiving at the first time
The notice of module 121, cuts off clock at once, and the system phaselocked loop of allowing immediately enters hold mode.
In another embodiment of the present invention, clock gate portion 12 can also be combinational logic circuit, for example, can incite somebody to action
The line-recovered clock signal of the LOS signal of optical module, physical chip output accesses CPLD (Complex simultaneously
Programmable Logic Device, Complex Programmable Logic Devices) or FPGA (Field-Programmable Gate
Array, field programmable gate array), two signals are done by a simple combinational logic operation by hardware description language.
It should be noted that in order to which chips different in adaptation system, port or circuit are to the different demands of clock frequency, such as
Shown in Fig. 3, frequency division department 15 is also provided between clock gate portion 12 and phaselocked loop 14, clock gate portion 12 can pass through frequency dividing
Portion 15 is connected with phaselocked loop 14.Frequency division department 15 is used for the clock division for exporting clock gate portion 12.
Optionally, as shown in figure 4, frequency division department 15 can also be arranged between clock recovery portion 11 and clock gate portion 12,
Clock recovery portion 11 is connected by frequency division department 15 with clock gate portion 12, frequency division department 15 for by clock recovery portion 11 export when
Clock gate portion 12 is transferred to after clock frequency dividing.
After adopting the above technical scheme, line status monitoring and the shutdown of clock pass through hardware completely and realize automatically, it is not necessarily to
Software participates in, and speed is fast, and from line interruption to shutdown clock, the time is nanosecond, effectively can make system when external
Zhong Yuan is lost to still work between the new clock source of switching and improves the performance of system in synchronous regime.
Correspondingly, as shown in figure 5, the embodiment of the present invention also to provide any network clocking in a kind of previous embodiment same
Walk the working method of device, comprising:
S21, detect the network data access device whether to the clock recovery portion transmit data；
S22, when the network data access device transmits data to the clock recovery portion, by the clock recovery portion
The line clock of output is transmitted to the phaselocked loop；It interrupts in the network data access device to the clock recovery portion and transmits
When data, the line clock that the clock recovery portion is voluntarily transmitted to the phaselocked loop is truncated, so that the phaselocked loop keeps number
According to the line clock before interruption.
The working method of network clock synchronous device provided in an embodiment of the present invention, clock gate portion 12 can be in network numbers
When transmitting data to clock recovery portion 11 according to access device 13, the line clock that clock recovery portion 11 exports is passed to phaselocked loop 14
It passs, when network data access device 13 interrupts and transmits data to clock recovery portion 11, clock recovery portion 11 is truncated voluntarily to lock
The line clock that phase ring 14 transmits, so that phaselocked loop 14 be made to keep the line clock before data outage.Due to clock gate portion 12
Directly it is connected with network data access device 13, can knows the data output state of network data access device 13 in real time, from
And the first time interrupted can be exported in 13 data of network data access device, clock recovery portion 11 is truncated in time voluntarily to lock
The line clock that phase ring 14 transmits, makes phaselocked loop 14 continue to keep original clock output, avoids 14 output error of phaselocked loop
The case where clock, effectively increases the synchronism of network clocking.
Optionally, it when network data access device 13 includes optical module, in step S21, detects the network data and connects
Entering device whether to transmit data to the clock recovery portion includes: the dropout LOS pin inspection by detecting the optical module
Survey the network data access device whether to the clock recovery portion transmit data.
Below by specific embodiment, the working method of network clock synchronous device provided by the invention is carried out specifically
It is bright.
Work the equipment in synchronous ethernet, first Systematic selection present port synchronised clock, then by configuring choosing
It selects, line-recovered clock of the system phase lock loop locks from present port, and as benchmark generation system work clock, when working as
When the external connection of front port is interrupted suddenly because of abnormal failure, after the detection module in clock gate portion detects that optical signal is lost
Current port state is informed gating module in the form of level signal at once, gating module after receiving level translation, work as by cutting
The clock of front port physical chip line-recovered clock output pin output.System phaselocked loop detects that external clock is lost immediately
It loses, keeps mode into HOLDOVER, wait system management layers to detect external signal exception, then pass through SSM
Synchronisation source is switched to other clocks by (Synchronization Status Message, Synchronization Status Message) algorithm, in detail
Process can be as shown in Figure 6.
The abnormal influence to synchronous ethernet equipment of external clock reference can be substantially reduced by adopting the above technical scheme, improved
Clock system performance, and then the reliability of entire clock synchronous network network is improved, and method is simple, it is reliable efficient, without increasing volume
Outer hardware cost.
Although for illustrative purposes, the preferred embodiment of the present invention has been disclosed, those skilled in the art will recognize
It is various improve, increase and replace be also it is possible, therefore, the scope of the present invention should be not limited to the above embodiments.
Claims (9)
1. a kind of network clock synchronous device characterized by comprising clock recovery portion and clock gate portion,
The clock recovery portion, one end are connected with network data access device, and the other end is connected with the clock gate portion, are used for
Line clock is recovered using the data that the network data access device is passed to；
The clock gate portion, first input end are connected with the clock recovery portion, the second input terminal and the network data
Access device is connected, and output end is connected with phaselocked loop, is used for: passing in the network data access device to the clock recovery portion
When transmission of data, the line clock that the clock recovery portion exports is transmitted to the phaselocked loop；It accesses and fills in the network data
Set interruption to the clock recovery portion transmit data when, be truncated the clock recovery portion voluntarily to the phaselocked loop transmit route
Clock, so that the phaselocked loop keeps the line clock before data outage.
2. the apparatus according to claim 1, which is characterized in that the network data access device includes optical module, described
Clock recovery portion includes physical chip.
3. the apparatus of claim 2, which is characterized in that second input terminal and the optical mode in the clock gate portion
The dropout LOS pin of block is connected.
4. device according to any one of claim 1 to 3, which is characterized in that the clock gate portion includes mutually interconnecting
The detection module and gating module connect, wherein the detection module is connected with the network data access device, the gating mould
Block is connected with the clock recovery portion.
5. device according to any one of claim 1 to 3, which is characterized in that the clock gate portion is combinational logic
Circuit.
6. device according to any one of claim 1 to 3, which is characterized in that the clock gate portion and the locking phase
Frequency division department is additionally provided between ring, the clock gate portion is connected by the frequency division department with the phaselocked loop, the frequency division department
For the clock division for exporting the clock gate portion.
7. device according to any one of claim 1 to 3, which is characterized in that the clock recovery portion and the clock
Frequency division department is additionally provided between strobe portion, the clock recovery portion is connected by the frequency division department with the clock gate portion, institute
It states frequency division department to be used for, the clock gate portion will be transferred to after the clock division of clock recovery portion output.
8. the working method of network clock synchronous device according to claim 1 characterized by comprising
Detect the network data access device whether to the clock recovery portion transmit data；
When the network data access device transmits data to the clock recovery portion, by the line of clock recovery portion output
Phaselocked loop described in clockwise transmits when road；When the network data access device interrupts and transmits data to the clock recovery portion,
The line clock that the clock recovery portion is voluntarily transmitted to the phaselocked loop is truncated, so that before the phaselocked loop keeps data outage
Line clock.
9. according to the method described in claim 8, it is characterized in that, the network data access device includes optical module；
Whether the detection network data access device transmits data to the clock recovery portion
Whether dropout LOS pin by detecting the optical module detects the network data access device to the clock
Recovery section transmits data.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410829183.8A CN105790872B (en) | 2014-12-26 | 2014-12-26 | A kind of network clock synchronous device and its working method |
| PCT/CN2015/081973 WO2016101562A1 (en) | 2014-12-26 | 2015-06-19 | Network clock synchronization device and working method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410829183.8A CN105790872B (en) | 2014-12-26 | 2014-12-26 | A kind of network clock synchronous device and its working method |
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| Publication Number | Publication Date |
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| CN105790872A CN105790872A (en) | 2016-07-20 |
| CN105790872B true CN105790872B (en) | 2019-01-29 |
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|---|---|---|---|
| CN201410829183.8A Active CN105790872B (en) | 2014-12-26 | 2014-12-26 | A kind of network clock synchronous device and its working method |
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| CN (1) | CN105790872B (en) |
| WO (1) | WO2016101562A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107579796B (en) * | 2017-09-21 | 2019-04-26 | 烽火通信科技股份有限公司 | A kind of the clock processing unit and method of OTN branch board |
| CN111432139B (en) * | 2020-03-31 | 2022-05-17 | 北京淳中科技股份有限公司 | Distributed system and clock synchronization switching device thereof |
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|---|---|---|---|---|
| CN1311587A (en) * | 2000-02-26 | 2001-09-05 | 三星电子株式会社 | Method and device used for data flow clock |
| CN101394181A (en) * | 2008-09-24 | 2009-03-25 | 硅谷数模半导体（北京）有限公司 | Time clock and data recovery circuit and integrated chip having the circuit |
| CN101807965A (en) * | 2009-02-13 | 2010-08-18 | 大唐移动通信设备有限公司 | Device and method for synchronizing clock in communication system |
| CN102138298A (en) * | 2008-05-02 | 2011-07-27 | 北电网络有限公司 | Method and apparatus for time and frequency transfer in communication networks |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100486148C (en) * | 2001-07-02 | 2009-05-06 | 中兴通讯股份有限公司 | Loopback protector for light monitor channel |
| US7106823B2 (en) * | 2002-11-15 | 2006-09-12 | Broadcom Corporation | System and method for accelerated clock synchronization of remotely distributed electronic devices |
| CN101686120B (en) * | 2008-09-26 | 2012-07-25 | 电信科学技术研究院 | Device and method for realizing clock synchronization |
| JP5193846B2 (en) * | 2008-12-25 | 2013-05-08 | 株式会社東芝 | Synchronization circuit |
| JP2012169721A (en) * | 2011-02-10 | 2012-09-06 | Nec Software Hokuriku Ltd | Encryption processing circuit, and encryption processing method |
| CN103354493B (en) * | 2013-06-26 | 2016-06-29 | 华为技术有限公司 | A kind of clock recovery circuitry, photoreceiver and passive optical network equipment |
-
2014
- 2014-12-26 CN CN201410829183.8A patent/CN105790872B/en active Active
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2015
- 2015-06-19 WO PCT/CN2015/081973 patent/WO2016101562A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311587A (en) * | 2000-02-26 | 2001-09-05 | 三星电子株式会社 | Method and device used for data flow clock |
| CN102138298A (en) * | 2008-05-02 | 2011-07-27 | 北电网络有限公司 | Method and apparatus for time and frequency transfer in communication networks |
| CN101394181A (en) * | 2008-09-24 | 2009-03-25 | 硅谷数模半导体（北京）有限公司 | Time clock and data recovery circuit and integrated chip having the circuit |
| CN101807965A (en) * | 2009-02-13 | 2010-08-18 | 大唐移动通信设备有限公司 | Device and method for synchronizing clock in communication system |
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| Publication number | Publication date |
|---|---|
| CN105790872A (en) | 2016-07-20 |
| WO2016101562A1 (en) | 2016-06-30 |
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