JP2012169721A - Encryption processing circuit, and encryption processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an encryption processing circuit capable of reducing the possibility of allowing a key to be specified even when a cycle of external clock signals is changed.SOLUTION: An encryption processing circuit 100 is an encryption processing circuit for encrypting inputted information by executing round processing of acquiring information stored in a register, converting the acquired information on the basis of a key according to a preset system, and storing the converted information in the register. The encryption processing circuit 100 includes: a phase locked loop circuit 101 for receiving input of external clock signals from the outside and generating internal clock signals synchronized with the inputted external clock signals by executing feedback control; and a round processing circuit 102 which is configured to be operated in synchronism with the generated internal clock signals and encrypts the inputted information by repeatedly executing the round processing.

Description

  The present invention relates to an encryption processing circuit that encrypts information by executing a round process.

  An encryption processing circuit that encrypts information by executing round processing is known. As one of this type of encryption processing circuit, the encryption processing circuit described in Patent Document 1 encrypts input information by repeatedly executing round processing in synchronization with an external clock signal. The round process is a process of acquiring information stored in a register, converting the acquired information based on a key in accordance with a preset method, and storing the converted information in the register.

JP 2010-245753 A

  By the way, it is assumed that the information input to the register to be stored in the register is changed within a preset data maintenance request period. Here, the data maintenance request period is a period from a time point before the rising edge (or falling edge) of the external clock signal by a setup time to a time point after the edge by the hold time. In this case, it is not guaranteed whether the information stored in the register is the information before the change or the information after the change.

  Therefore, when information representing the execution result of the round process is input to the register, the encryption processing circuit can be caused to execute an abnormal process by shortening the cycle of the external clock signal. In addition, the information indicating the difference between the encrypted information when the encryption processing circuit performs abnormal processing and the encrypted information when the encryption processing circuit performs normal processing. It is known that it may be possible to identify a key based on (ie, by a fault attack).

  Thus, in the encryption processing circuit, there is a possibility that the key is specified by changing the cycle of the external clock signal.

  For this reason, an object of the present invention is to provide an encryption processing circuit capable of solving the above-described problem “a case where a key is specified by changing the period of an external clock signal”. There is to do.

In order to achieve such an object, an encryption processing circuit according to an aspect of the present invention includes:
By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, It is an encryption processing circuit that encrypts input information.

Furthermore, this encryption processing circuit
An external clock signal is input from the outside, and a phase synchronization circuit that generates an internal clock signal synchronized with the input external clock signal by performing feedback control;
A round processing circuit configured to operate in synchronization with the generated internal clock signal, and encrypting the input information by repeatedly executing the round processing;
Is provided.

In addition, an encryption processing method according to another aspect of the present invention includes:
By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, This is a method of encrypting input information.

Furthermore, this encryption processing method is
An external clock signal is input from the outside and feedback control is performed to generate an internal clock signal synchronized with the input external clock signal.
It is a method of encrypting the inputted information by repeatedly executing the round process by operating in synchronization with the generated internal clock signal.

  By configuring as described above, the present invention can reduce the possibility of specifying a key even when the period of the external clock signal is changed.

It is a figure showing schematic structure of the encryption processing circuit which concerns on 1st Embodiment of this invention. It is the flowchart which showed the process which the encryption processing circuit which concerns on 1st Embodiment of this invention performs. It is a figure showing schematic structure of the encryption processing circuit which concerns on 2nd Embodiment of this invention. It is a figure showing schematic structure of the encryption processing circuit which concerns on 3rd Embodiment of this invention.

  Hereinafter, embodiments of an encryption processing circuit and an encryption processing method according to the present invention will be described with reference to FIGS.

<First Embodiment>
(Constitution)
As shown in FIG. 1, the encryption processing circuit 1 according to the first embodiment is an integrated circuit. Information (plain text) is input to the encryption processing circuit 1 from the outside of the encryption processing circuit 1. The encryption processing circuit 1 encrypts the input information based on the key (information as). Then, the encryption processing circuit 1 outputs the encrypted information (ciphertext) to the outside of the encryption processing circuit 1.

  In this example, the encryption processing circuit 1 encrypts input information in accordance with an AES (Advanced Encryption Standard) encryption method, which is one of common key encryption methods. The AES encryption method is one of block encryption methods. The encryption processing circuit 1 may be configured to encrypt input information in accordance with another encryption method such as a DES (Data Encryption Standard) encryption method.

  The encryption processing circuit 1 includes a round processing circuit 10, a key schedule processing circuit 20, and a phase locked loop (PLL) 30.

  A clock signal (external clock signal) is input to the phase synchronization circuit 30 from the outside of the encryption processing circuit 1. The phase synchronization circuit 30 performs feedback control to generate a clock signal (internal clock signal) that is synchronized with the input external clock signal. The phase synchronization circuit 30 outputs (supplies) the generated internal clock signal to each of the round processing circuit 10 and the key schedule processing circuit 20.

  The round processing circuit 10 is configured to operate in synchronization with the internal clock signal generated by the phase synchronization circuit 30. The round processing circuit 10 encrypts information (plain text) input to the encryption processing circuit 1 by repeatedly executing round processing for a preset number of iterations. The round processing circuit 10 executes round processing only once each time a rising edge (which may be a falling edge) of the internal clock signal arrives.

  The round processing circuit 10 starts executing round processing at a time after the time when the internal clock signal generated by the phase synchronization circuit 30 is synchronized with the external clock signal. In this example, the round processing circuit 10 performs round processing when the number of times that the rising edge of the external clock signal input to the phase synchronization circuit 30 has arrived (number of times of arrival of the edge) reaches a preset number of standby times. Start running.

The round processing circuit 10 includes a register 11 and a conversion processing circuit 12.
The conversion processing circuit 12 performs a round process.
Specifically, in the first round process, the conversion processing circuit 12 acquires the input plaintext as information (conversion process target information) to be converted. The conversion processing circuit 12 acquires information stored in the register 11 as conversion processing target information in the second and subsequent round processing.

The extended key generated by the key schedule processing circuit 20 is input to the conversion processing circuit 12. Based on the input extended key, the conversion processing circuit 12 converts the acquired information (conversion processing target information) according to a preset method (that is, executes conversion processing on the conversion processing target information). The conversion processing circuit 12 stores the converted information in the register 11.
In this way, the conversion processing circuit 12 performs round processing.

  The round processing circuit 10 obtains information stored in the register 11 after the round processing is executed by the conversion processing circuit 12 by the number of iterations, and the obtained information is converted into encrypted information (ciphertext). Output to the outside of the encryption processing circuit 1.

  The key schedule processing circuit 20 includes an extended key generation circuit 21. The extended key generation circuit 21 generates an extended (extended) key (round key) for each round process based on a key stored in advance. In this example, the extended key generation circuit 21 generates an extended key so that the extended keys for each round process are different from each other. Then, the extended key generation circuit 21 outputs the generated extended key to the conversion processing circuit 12. The extended key generation circuit 21 may be configured such that a key is input from the outside of the encryption processing circuit 1.

(Operation)
Next, the operation of the encryption processing circuit 1 described above will be described.
The encryption processing circuit 1 is configured to execute the processing shown by the flowchart in FIG. 2 when the encryption processing circuit 1 is activated.

  More specifically, the encryption processing circuit 1 waits until the edge arrival count reaches (matches) the standby count in step S101. When the edge arrival count reaches the standby count, the encryption processing circuit 1 determines “Yes”, proceeds to step S102, and waits until a plaintext is input.

  Next, when plaintext is input to the encryption processing circuit 1, the encryption processing circuit 1 determines “Yes” and proceeds to step S <b> 103, and converts the input plaintext into conversion processing target information in the first round processing. Get as.

  Then, the encryption processing circuit 1 generates an expanded key for the first round process based on the key stored in advance (step S104). Next, the encryption processing circuit 1 sets the counter value i to 1 (step S105).

Then, the encryption processing circuit 1 executes the first conversion process on the conversion process target information acquired in step S103 based on the expanded key generated in step S104 (step S106). Then, the encryption processing circuit 1 stores the converted information in the register 11 (step S107).
Note that the processes of step S103, step S106, and step S107 constitute the first round process.

  Next, the encryption processing circuit 1 determines whether or not the counter value i is smaller than the number of iterations N (step S108). Assume that the counter value i is smaller than the number of iterations N. In this case, the encryption processing circuit 1 determines “Yes”, proceeds to step S109, and acquires the information stored in the register as the conversion process target information in the i-th round process.

  Then, the encryption processing circuit 1 generates an expanded key for the i-th round process based on the key stored in advance (step S110). Next, the encryption processing circuit 1 adds 1 to the counter value i (step S111).

Then, the encryption processing circuit 1 executes the i-th conversion process on the conversion process target information acquired in step S109 based on the expanded key generated in step S110 (step S112). Then, the encryption processing circuit 1 stores the converted information in the register 11 (step S113).
Note that the processes in step S109, step S112, and step S113 constitute the i-th round process.

  Thereafter, when the counter value i reaches (matches) the number of iterations N, the encryption processing circuit 1 determines “No” when it proceeds to step S108, and proceeds to step S114. Then, the encryption processing circuit 1 acquires the information stored in the register as information (ciphertext) obtained by encrypting the input plaintext. Next, the encryption processing circuit 1 outputs the acquired ciphertext to the outside of the encryption processing circuit 1. Thereafter, the encryption processing circuit 1 returns to step S102.

  As described above, according to the encryption processing circuit 1 according to the first embodiment of the present invention, the encryption processing circuit 1 performs round processing in synchronization with the internal clock signal generated by the phase synchronization circuit 30. Repeated execution encrypts input information. Thereby, even when the cycle of the external clock signal is changed, the encryption processing circuit 1 can execute normal processing. As a result, it is possible to reduce the possibility that the key is specified even when the period of the external clock signal is changed.

  Furthermore, according to the encryption processing circuit 1 according to the first embodiment of the present invention, the round processing circuit 10 has a time after the time when the internal clock signal generated by the phase synchronization circuit 30 is synchronized with the external clock signal. , Configured to start execution of the round process.

  By the way, the phase synchronization circuit 30 generates an internal clock signal synchronized with the external clock signal by performing feedback control. Therefore, a predetermined delay time (lock-up time) is required until the internal clock signal generated by the phase synchronization circuit 30 is synchronized with the external clock signal. Therefore, by configuring the encryption processing circuit 1 as described above, it is possible to cause the encryption processing circuit 1 to execute normal processing more reliably.

Second Embodiment
Next, an encryption processing circuit according to the second embodiment of the present invention will be described. The encryption processing circuit according to the second embodiment erases the information stored in the register when it is detected that the external clock signal is abnormal with respect to the encryption processing circuit according to the first embodiment. Is different. Accordingly, the following description will focus on such differences.

  As illustrated in FIG. 3, the encryption processing circuit 1 according to the second embodiment includes an abnormality detection circuit (abnormality detection unit) 40 in addition to the configuration included in the encryption processing circuit 1 according to the first embodiment. . The abnormality detection circuit 40 includes an operation amplification circuit 41.

  The operational amplifier circuit 41 detects a difference between an external clock signal input to the encryption processing circuit 1 from the outside of the encryption processing circuit 1 and an internal clock signal generated by the phase synchronization circuit 30.

  The abnormality detection circuit 40 detects that the external clock signal is abnormal when the difference detected by the operation amplification circuit 41 is larger than a preset threshold value difference. Further, the abnormality detection circuit 40 erases the information stored in the register 11 when it is detected that the external clock signal is abnormal.

  By the way, when the external clock signal is abnormal (for example, when the period of the external clock signal is changed), there is a possibility that the encryption processing circuit 1 is attacked (fault attack, side channel attack, etc.). Relatively high.

  Therefore, by configuring the encryption processing circuit 1 as described above, when the external clock signal is detected to be abnormal, the encryption processing circuit 1 substantially performs the process of encrypting the input information. Can be discontinued. As a result, the possibility of specifying the key can be further reduced.

<Third Embodiment>
Next, an encryption processing circuit according to a third embodiment of the present invention will be described with reference to FIG.
The encryption processing circuit 100 according to the third embodiment includes:
By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, It is an encryption processing circuit that encrypts input information.

Further, the encryption processing circuit 100 includes:
An external clock signal is input from the outside, and by performing feedback control, a phase synchronization circuit 101 that generates an internal clock signal synchronized with the input external clock signal;
A round processing circuit 102 configured to operate in synchronization with the generated internal clock signal and encrypting the input information by repeatedly executing the round processing;
Is provided.

  According to this, the encryption processing circuit 100 encrypts input information by repeatedly executing round processing in synchronization with the internal clock signal generated by the phase synchronization circuit 101. Thereby, even when the cycle of the external clock signal is changed, the encryption processing circuit 100 can perform normal processing. As a result, it is possible to reduce the possibility that the key is specified even when the period of the external clock signal is changed.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above-described embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  In addition, as another modified example of the above-described embodiment, any combination of the above-described embodiments and modified examples may be employed.

<Appendix>
A part or all of the above embodiment can be described as the following supplementary notes, but is not limited thereto.

(Appendix 1)
By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, An encryption processing circuit that encrypts input information,
An external clock signal is input from the outside, and a phase synchronization circuit that generates an internal clock signal synchronized with the input external clock signal by performing feedback control;
A round processing circuit configured to operate in synchronization with the generated internal clock signal and encrypting the input information by repeatedly executing the round processing;
An encryption processing circuit comprising:

  According to this, the encryption processing circuit encrypts the input information by repeatedly executing the round processing in synchronization with the internal clock signal generated by the phase synchronization circuit. Thereby, even if the cycle of the external clock signal is changed, the encryption processing circuit can be made to execute normal processing. As a result, it is possible to reduce the possibility that the key is specified even when the period of the external clock signal is changed.

(Appendix 2)
An encryption processing circuit according to attachment 1, wherein
The round processing circuit is configured to start execution of the round processing at a time after the time when the internal clock signal generated by the phase synchronization circuit is synchronized with the external clock signal. .

  By the way, the phase synchronization circuit generates an internal clock signal synchronized with the external clock signal by performing feedback control. Therefore, a predetermined delay time is required until the internal clock signal generated by the phase synchronization circuit is synchronized with the external clock signal. Therefore, by configuring the encryption processing circuit as described above, it is possible to cause the encryption processing circuit to execute normal processing more reliably.

(Appendix 3)
The encryption processing circuit according to Supplementary Note 1 or Supplementary Note 2, wherein
Comprising an abnormality detection means for detecting that the external clock signal is abnormal;
An encryption processing circuit configured to erase information stored in the register when it is detected that the external clock signal is abnormal.

  By the way, when the external clock signal is abnormal (for example, when the cycle of the external clock signal is changed), the possibility that the encryption processing circuit is attacked (fault attack, side channel attack, etc.) is compared. High. Thus, by configuring the encryption processing circuit as described above, when the external clock signal is detected to be abnormal, the encryption processing circuit substantially performs the process of encrypting the input information. Can be canceled. As a result, the possibility of specifying the key can be further reduced.

(Appendix 4)
The encryption processing circuit according to attachment 3, wherein
The abnormality detection means includes an operational amplifier circuit that detects a difference between the external clock signal and the internal clock signal, and when the detected difference is larger than a preset threshold difference, An encryption processing circuit configured to detect that an external clock signal is abnormal.

(Appendix 5)
The encryption processing circuit according to any one of appendices 1 to 4,
An encryption processing circuit configured to encrypt the input information according to a block encryption method.

(Appendix 6)
By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, An encryption processing method for encrypting input information,
An external clock signal is input from the outside and feedback control is performed to generate an internal clock signal synchronized with the input external clock signal.
An encryption processing method for encrypting the input information by repeatedly executing the round processing by operating in synchronization with the generated internal clock signal.

(Appendix 7)
The encryption processing method according to attachment 6, wherein
An encryption processing method, wherein execution of the round processing is started at a time after the time when the internal clock signal is synchronized with the external clock signal.

(Appendix 8)
The encryption processing method according to appendix 6 or appendix 7,
Detecting that the external clock signal is abnormal;
An encryption processing method for erasing information stored in the register when it is detected that the external clock signal is abnormal.

  The present invention can be applied to an encryption processing circuit that encrypts information by executing a round process.

DESCRIPTION OF SYMBOLS 1 Encryption processing circuit 10 Round processing circuit 11 Register 12 Conversion processing circuit 20 Key schedule processing circuit 21 Extended key generation circuit 30 Phase synchronization circuit 40 Abnormality detection circuit 41 Operation amplification circuit 100 Encryption processing circuit 101 Phase synchronization circuit 102 Round processing circuit

Claims (8)

By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, An encryption processing circuit that encrypts input information,
An external clock signal is input from the outside, and a phase synchronization circuit that generates an internal clock signal synchronized with the input external clock signal by performing feedback control;
A round processing circuit configured to operate in synchronization with the generated internal clock signal and encrypting the input information by repeatedly executing the round processing;
An encryption processing circuit comprising: The encryption processing circuit according to claim 1,
The round processing circuit is configured to start execution of the round processing at a time after the time when the internal clock signal generated by the phase synchronization circuit is synchronized with the external clock signal. . The encryption processing circuit according to claim 1 or 2, wherein
Comprising an abnormality detection means for detecting that the external clock signal is abnormal;
An encryption processing circuit configured to erase information stored in the register when it is detected that the external clock signal is abnormal. The encryption processing circuit according to claim 3,
The abnormality detection means includes an operational amplifier circuit that detects a difference between the external clock signal and the internal clock signal, and when the detected difference is larger than a preset threshold difference, An encryption processing circuit configured to detect that an external clock signal is abnormal. An encryption processing circuit according to any one of claims 1 to 4,
An encryption processing circuit configured to encrypt the input information according to a block encryption method. By acquiring the information stored in the register, converting the acquired information based on a key according to a preset method, and storing the converted information in the register, by performing a round process, An encryption processing method for encrypting input information,
An external clock signal is input from the outside and feedback control is performed to generate an internal clock signal synchronized with the input external clock signal.
An encryption processing method for encrypting the input information by repeatedly executing the round processing by operating in synchronization with the generated internal clock signal. The encryption processing method according to claim 6,
An encryption processing method, wherein execution of the round processing is started at a time after the time when the internal clock signal is synchronized with the external clock signal. The encryption processing method according to claim 6 or 7, wherein
Detecting that the external clock signal is abnormal;
An encryption processing method for erasing information stored in the register when it is detected that the external clock signal is abnormal.

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