CN103412615A - Glitch-free self-adaptive clock switching method for UART (Universal Asynchronous Receiver Transmitter) interface chip - Google Patents

Glitch-free self-adaptive clock switching method for UART (Universal Asynchronous Receiver Transmitter) interface chip Download PDF

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CN103412615A
CN103412615A CN2013103712357A CN201310371235A CN103412615A CN 103412615 A CN103412615 A CN 103412615A CN 2013103712357 A CN2013103712357 A CN 2013103712357A CN 201310371235 A CN201310371235 A CN 201310371235A CN 103412615 A CN103412615 A CN 103412615A
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clock
chip
frequency
frequency multiplier
uart interface
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CN103412615B (en
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郑炜
朱天成
李鑫
杨阳
周津
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No 8357 Research Institute of Third Academy of CASIC
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Abstract

The invention discloses a glitch-free self-adaptive clock switching method for a UART (Universal Asynchronous Receiver Transmitter) interface chip. The glitch-free self-adaptive clock switching method for the UART interface chip comprises the flowing steps of (1) obtaining a next working state, namely, inputting the clock frequency and the baud rate of the UART interface chip through a self-adaptive clock switching module according to configuration information which is wrote in through a CPU (Central Processing Unit) in a parallel mode; (2) calculating the UART interface chip required mclk frequency; (3) comparing the required mclk frequency with clkin frequency, calculating the double frequency and opening a frequency doubler when the required mclk frequency is higher than the clkin frequency and closing the frequency doubler when the required mclk frequency is lower than the clkin frequency; (4) switching the chip mclk according to opening and closing of the frequency doubler. The UART interface chip comprises the self-adaptive clock switching module which is connected with a chip mclk. According to the glitch-free self-adaptive clock switching method for the UART interface chip, clock strategies of the chip is automatically adjusted and the purpose of optimizing power consumption is achieved according to a current working state of the UART interface chip and the next working state which is wrote in through the CPU.

Description

A kind of for the UART interface chip without burr self-adaptation clock changing method
Technical field
The present invention relates to the clock-switching method of UART interface chip.
Background technology
Data transmission between main frame and external unit comprises two kinds of parallel transmission and serial transmissions, and wherein parallel transmission is for short, the fireballing occasion of distance, and, in the situation that distance, rate request are not high, usually adopts serial transmission.As shown in Figure 1, the UART(UART Universal Asynchronous Receiver Transmitter that adopt between CPU and serial equipment) interface chip carries out and the serial ports conversion more: the UART interface chip changes into serial port protocol by the data that CPU is written in parallel to, and sends to serial equipment by predefined frame format and baud rate; And the serial data that will receive is stored in inner buffer, reads for CPU is parallel.
Most of UART interface chips can work under multiple baud rate (transfer rate), and in order to improve the anti-interference and reliability of serial communication, serial interface chip usually adopts 16 times of clock sampling rs 232 serial interface signals, and namely the chip major clock is 16 times of serial ports baud rate.Development along with computer technology, it is even higher that some special occasions tend to require serial ports speed to reach 5Mbit/s, therefore require serial port chip in the situation that meet working standard baud rate (as 110,300,600,1200,2400,4800,9600,19200,38400,614400 etc.) transmission, can also take into account nonstandard High Speed Serial agreement.In order to take into account nonstandard High Speed Serial agreement when 16 sampling, integrated clock frequency multiplier usually in the UART interface chip as shown in Figure 1.Mostly the baud rate adjustment of current serial port chip, be that the chip input clock frequency fixes, and the method for being adjusted UART interface chip internal clocking pre-divider 101 by CPU realizes.But due to the existence of UART interface chip internal clocking frequency multiplier, only depend on the mode of frequency division to adjust baud rate, can't reach the optimization of UART interface chip power consumption.
Summary of the invention
The object of the invention is to: make the High Speed UART interface chip in wider baud rate scope, can require to adjust in real time the chip internal clock strategy according to baud rate, and guarantee clock safety, without the switching of burr ground, thereby reach the purpose of optimization chip power-consumption.
In digital circuit, the digital signal of input change or carry out some logical operations (as non-, with or etc.) time, output signal does not have to change by Complete Synchronization, thereby cause the rub-out signal pulse output in blink, the pulse of this rub-out signal is very narrow, is known as " burr " (English: glitch); In the present invention, when the major clock of UART chip (mclk) switched between the two at chip input clock clkin and chip internal frequency multiplier output clock pllclk, the mistake burst pulse that misoperation can be introduced, be also referred to as burr.
The technical scheme adopted for achieving the above object is: a kind of clock-switching method of UART interface chip comprises the steps:
1) configuration information that is written in parallel to according to CPU of self-adaptation clock handover module obtains next duty of UART interface chip: input clock frequency and baud rate;
2) calculate the required master clock frequency of UART interface chip;
3) more required master clock frequency and input clock frequency, when required master clock frequency, during higher than input clock frequency, calculate overtones band: the frequency during overtones band=master clock frequency/input, open frequency multiplier, when required master clock frequency, during lower than input clock frequency, close frequency multiplier;
4) according to the switching of frequency multiplier, carry out the switching of chip major clock.
The required master clock frequency of described UART interface chip is baud rate * UART interface chip clock multiplier.UART interface chip clock multiplier is 16.
The switching of described chip major clock is the switching between chip input clock and frequency multiplier output clock.
The changing method of described chip input clock and frequency multiplier output clock, comprise the steps:
A. by unlatching, switched to while closing when frequency multiplier, the chip major clock is switched to the chip input clock by the frequency multiplier output clock;
B. work as frequency multiplier and switch to unlatching by closing, the chip major clock is switched to the frequency multiplier output clock by the chip input clock;
If C. frequency multiplier need to be held open, and while need adjusting overtones band, the chip major clock is switched to the frequency multiplier output clock after overtones band is adjusted.
Describedly by the chip major clock, by the step that the frequency multiplier output clock switches to the chip input clock be:
At the negative edge of frequency multiplier output clock, close the path of frequency multiplier output clock to the chip major clock;
Close frequency multiplier;
At the negative edge opening chip input clock of the next chip input clock path to the chip major clock;
Complete the chip major clock by the switching of chip input clock to the frequency multiplier output clock.
Describedly by the chip major clock, by the step that the chip input clock switches to the frequency multiplier output clock be:
Overtones band is set, opens frequency multiplier, after the frequency multiplier stable output, carry out the switching of chip major clock:
At the negative edge of chip input clock, close the path of chip input clock to the chip major clock;
At the negative edge of next frequency multiplier output clock, open the path of frequency multiplier output clock to the chip major clock;
Complete the chip major clock by the switching of chip input clock to the frequency multiplier output clock.
The described step that the chip major clock is switched to the frequency multiplier output clock after the overtones band adjustment is:
At the negative edge of frequency multiplier output clock, close the path of frequency multiplier output clock to the chip major clock;
Adjust the overtones band of frequency multiplier;
After the frequency multiplier stable output, open the path of frequency multiplier output clock to the chip major clock at the negative edge of next frequency multiplier output clock;
Complete the switching of the frequency multiplier output clock after the chip major clock is adjusted to overtones band;
By a counter, determine frequency multiplier stable output required time, the value of counter is switched after reaching locking time of frequency multiplier.
The advantage of patent of the present invention is:
The duty current according to the High Speed UART interface chip, and the next duty that writes of CPU, automatically adjust the clock strategy of chip, reaches the purpose of optimizing power consumption.
If need to adjust the duty of the inner frequency multiplier of High Speed UART interface chip, automatically avoid the amphibolia of frequency multiplier when state switch, avoid the High Speed UART interface chip to run and fly because of the major clock shake, when clock switches without burr.
Between frequency multiplier output clock and High Speed UART interface chip input clock, have certain phase differential, and this phase differential is relevant to chip manufacturing process, therefore can thinks that frequency multiplier output clock and High Speed UART interface chip input clock are asynchronous relationship.An important component part of the present invention is, while guaranteeing this two asynchronous clock switchings, can not introduce burr.
The accompanying drawing explanation
Fig. 1 is the structural representation of High Speed UART interface chip of the prior art;
Fig. 2 is the High Speed UART interface chip work structuring schematic diagram that adds the self-adaptation clock handover module of UART interface chip of the present invention;
Fig. 3 is the process flow diagram of the inventive method;
Fig. 4 is that clock in Fig. 3 is without the process flow diagram of burr switch step.
Embodiment
Chip major clock (mclk) is the work clock of UART chip internal sequential circuit; The duty different according to the UART chip, mclk can be chip input clock (clkin), can be also frequency multiplier output clock (pllclk), namely mclk is the alternative of clkin and pllclk; Such as selecting signal=0 o'clock, mclk=pllclk, select signal=1 o'clock, mclk=clkin.Because there is the delay uncertainty between input and output in frequency multiplier, cause the phase differential between pllclk and clkin uncertain, thereby while causing pllclk and clkin switching, very narrow pulse appears in mclk, i.e. burr, thus cause the logic error that chip circuit is very serious.The object of the invention is to solve chip major clock (mclk) because of the Burr Problem that the different duty switching of UART chip brings, guarantee the safe operation of chip circuit.
Embodiment
UART interface chip of the present invention as shown in Figure 2, in the pre-divider 101 of original High Speed UART interface chip is front, add self-adaptation clock handover module 201, self-adaptation clock handover module 201 is connected with the chip major clock, according to the state variation of frequency multiplier, carries out the switching of chip major clock.
Concrete self-adaptation clock handover module 201 also comprises duty identification module 202, clock handover module 203, the UART interface chip work state information that duty identification module 202 is written in parallel to according to CPU, the frequency of the required major clock of computing chip, according to required master clock frequency, whether higher than input clock frequency and current frequency multiplier state, judge whether to open frequency multiplier and calculate where necessary overtones band; Clock handover module 203 needs the state of redirect to adjust in real time frequency multiplier according to frequency multiplier, and carries out the switching between chip input clock and frequency multiplier output clock.
Workflow of the present invention as shown in Figure 3,
A. the UART interface chip work state information (frequency f of chip input clock clkin at first be written in parallel to according to CPU by 202 Clkin, baud rate Br), the frequency f of the required major clock mclk of computing chip Mclk=Br * 16(16 is UART interface chip clock multiplier).According to f MclkWhether be greater than f Clkin, and the current duty of frequency multiplier, determine the next duty of frequency multiplier:
Figure BDA0000370691660000041
If required master clock frequency is not higher than input clock frequency (f Mclk≤ f Clkin), frequency multiplier will be closed.
Figure BDA0000370691660000042
If required master clock frequency is higher than input clock frequency (f Mclk>f Clkin), calculate required overtones band.
B.203 according to the state transition situation of frequency multiplier, switch clock without burr.
203 clocks in Fig. 3 are without burr switch operating flow process as shown in Figure 4:
If a. the frequency multiplier state is switched to and closed by unlatching, judgement chip major clock mclk will switch to chip input clock clkin by frequency multiplier output clock pllclk:
At the negative edge of pllclk, close the path of pllclk to mclk.(rising edge refers to the moment of signal from the low transition to the high level, and negative edge refers to that signal jumps to low level moment from high level.）
Figure BDA0000370691660000044
Close frequency multiplier;
At pllclk, after the path blockade of mclk, open the path of clkin to mclk at the negative edge of next clkin, complete mclk by the switching of pllclk to clkin.(due to mclk, be the alternative of clkin and pllclk, close the clock path and complete with door by one, namely " selection signal ", while being low level, should be clamped at low level with the output of door.）
If b. the frequency multiplier state switches to unlatching by closing, judgement chip major clock mclk will switch to pllclk by clkin:
Set overtones band, open frequency multiplier;
Figure BDA0000370691660000052
Postpone a period of time: the clkin of take is clock count, and count value is the locking time of frequency multiplier.
Figure BDA0000370691660000053
At the negative edge of clkin, close the path of clkin to mclk.
Figure BDA0000370691660000054
At clkin, after the path blockade of mclk, open the path of pllclk to mclk at the negative edge of next pllclk, complete mclk by the switching of clkin to pllclk
If c. frequency multiplier need to be held open, and while need adjusting overtones band:
Figure BDA0000370691660000055
At the negative edge of pllclk, close the path of pllclk to mclk;
Adjust the overtones band of frequency multiplier;
Figure BDA0000370691660000057
Postpone a period of time: the clkin of take is clock count, and count value is the locking time of frequency multiplier;
At the negative edge of next pllclk, open the path of pllclk to mclk, complete the adjustment of overtones band.

Claims (8)

1. the clock-switching method of a UART interface chip, comprise the steps:
1) configuration information that is written in parallel to according to CPU of self-adaptation clock handover module obtains next duty of UART interface chip: input clock frequency and baud rate;
2) calculate the required master clock frequency of UART interface chip;
3) more required master clock frequency and input clock frequency, when required master clock frequency, during higher than input clock frequency, calculate overtones band: the frequency during overtones band=master clock frequency/input, open frequency multiplier, when required master clock frequency, during lower than input clock frequency, close frequency multiplier;
4) according to the switching of frequency multiplier, carry out the switching of chip major clock.
2. the clock-switching method of UART interface chip according to claim 1, is characterized in that, the required master clock frequency of described UART interface chip is baud rate * UART interface chip clock multiplier.
3. the clock-switching method of UART interface chip according to claim 1, is characterized in that, the switching of described chip major clock is the switching between chip input clock and frequency multiplier output clock.
4. the clock-switching method of UART interface chip according to claim 3, is characterized in that, the changing method of described chip input clock and frequency multiplier output clock, comprise the steps:
A. by unlatching, switched to while closing when frequency multiplier, the chip major clock is switched to the chip input clock by the frequency multiplier output clock;
B. work as frequency multiplier and switch to unlatching by closing, the chip major clock is switched to the frequency multiplier output clock by the chip input clock;
If C. frequency multiplier need to be held open, and while need adjusting overtones band, the chip major clock is switched to the frequency multiplier output clock after overtones band is adjusted.
5. the clock-switching method of UART interface chip according to claim 4, is characterized in that, describedly by the chip major clock, by the step that the frequency multiplier output clock switches to the chip input clock is:
At the negative edge of frequency multiplier output clock, close the path of frequency multiplier output clock to the chip major clock;
Close frequency multiplier;
At the negative edge opening chip input clock of the next chip input clock path to the chip major clock;
Complete the chip major clock by the switching of chip input clock to the frequency multiplier output clock.
6. the clock-switching method of UART interface chip according to claim 4, is characterized in that, describedly by the chip major clock, by the step that the chip input clock switches to the frequency multiplier output clock is:
Overtones band is set, opens frequency multiplier, after the frequency multiplier stable output, carry out the switching of chip major clock:
At the negative edge of chip input clock, close the path of chip input clock to the chip major clock;
At the negative edge of next frequency multiplier output clock, open the path of frequency multiplier output clock to the chip major clock;
Complete the chip major clock by the switching of chip input clock to the frequency multiplier output clock.
7. the clock-switching method of UART interface chip according to claim 4, is characterized in that, the described step that the chip major clock is switched to the frequency multiplier output clock after the overtones band adjustment is:
At the negative edge of frequency multiplier output clock, close the path of frequency multiplier output clock to the chip major clock;
Adjust the overtones band of frequency multiplier;
After the frequency multiplier stable output, open the path of frequency multiplier output clock to the chip major clock at the negative edge of next frequency multiplier output clock;
Complete the switching of the frequency multiplier output clock after the chip major clock is adjusted to overtones band.
8. according to the clock-switching method of claim 6 or the described UART interface chip of 7 any one, it is characterized in that, determine frequency multiplier stable output required time by a counter, the value of counter is switched after reaching locking time of frequency multiplier.
CN201310371235.7A 2013-08-22 2013-08-22 A kind of impulse- free robustness self-adaptation clock switching method for UART interface chip Expired - Fee Related CN103412615B (en)

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