CN103152035B - A kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop - Google Patents
A kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop Download PDFInfo
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Abstract
The present invention relates to a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop.In the invention process, the frequency plot testing circuit be made up of d type flip flop is adopted to detect two road frequency signals, the signal produced after detecting, through the control signal output circuit be made up of XOR gate, NAND gate and inverter, forms four roads and arrives next stage parts in phase-locked loop simultaneously---the control signal of charge pump.Often detected the one-period of signal, the reset be made up of NOR gate, inverter and metal-oxide-semiconductor, delay circuit can reset to frequency plot testing circuit, thus make frequency plot testing circuit carry out the detection in next cycle to signal.Delay circuit in reset, delay circuit is PLC technology, according to the need of work of phase-locked loop, can choose different delay times.This phase frequency detector have structure simple, without dead band, low-power consumption and the advantage that can form multi-way control signals.
Description
Technical field
The present invention relates to a kind of phase frequency detector for phase-locked loop, especially, the present invention relates to a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop.
Background technology
Phase-locked loop circuit is widely used in frequency synthesizer system, data and clock recovery system and electronics, computer realm.Fig. 1 is the structure chart of phase-locked loop circuit, and it generally includes 5 critical pieces: phase frequency detector, charge pump, filter, voltage controlled oscillator and frequency divider.
As shown in Figure 1, phase frequency detector receives crystal oscillation signal f
1with the output signal f of frequency divider
2, detect difference on the frequency therebetween and phase difference, and generate output control signal UP and DOWN.Charge pump reception control signal UP and DOWN, and they are converted to the electric current on filter.Electric current is device after filtering, output voltage to voltage controlled oscillator, to control the frequency of voltage controlled oscillator output signal.The signal that voltage controlled oscillator exports turns back to phase frequency detector again after frequency divider frequency division.
As crystal oscillation signal f
1lead over the output signal f of frequency divider
2time, the output increased with at filter is produced larger voltage by the output current of charge pump, and then the frequency of the output signal of increase voltage controlled oscillator.On the contrary, as crystal oscillation signal f
1lag behind the output signal f of frequency divider
2time, the output reduced with at filter is produced less voltage by the output current of charge pump, and then the frequency of the output signal of reduction voltage controlled oscillator.As crystal oscillation signal f
1with the output signal f of frequency divider
2during calibration, the voltage on filter is constant and the output signal frequency of voltage controlled oscillator keeps constant, then phase-locked loop is in " locking " state.
But, as crystal oscillation signal f
1with the output signal f of frequency divider
2edge closely time, the control signal UP that phase frequency detector exports and DOWN does not have the sufficient time to carry out thoroughly switching and driving charge pump thus, causes phase-locked loop to bear excessive phase jitter on little phase difference, greatly reduces the performance of phase-locked loop.The low gain district of the little phase difference that can not detect is dead band.Meanwhile, the two path control signal UP that phase frequency detector produces and DOWN is too single, can not meet the demand for control to the day by day complicated charge pump of structure.And control signal is difficult to reach charge pump simultaneously, to such an extent as to cause the shake of pll output signal.
Summary of the invention
For background technology Problems existing, the invention provides that a kind of structure is simple, zero dead band, low-power consumption and a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop of four tunnel control signals can be formed simultaneously.
For achieving the above object, technical scheme of the present invention is:
A kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop, it is characterized in that, comprise input connect two road frequency signals and for the frequency that detects this two-way frequency signal and phase place frequency plot testing circuit, the control signal that frequency plot testing circuit produces is formed four tunnels after treatment can arrive the control signal output circuit of the control signal of charge pump and the control signal of reading frequency phase detecting circuit simultaneously, then frequency plot testing circuit is resetted and the reset of delays time to control, delay circuit; Wherein, frequency plot testing circuit is connected with reset, delay circuit with two road frequency signals, control signal output circuit respectively; Control signal output circuit is connected with frequency plot testing circuit; Reset, delay circuit are connected with frequency plot testing circuit.
At above-mentioned a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop, described frequency plot testing circuit comprises two d type flip flop DFF1 and DFF2; The CLK end of described two d type flip flop DFF1 and DFF2 connects two road frequency signals, D termination power VDD respectively, and output Q connects the input of control signal output circuit, and output Qn connects the input of reset, delay circuit.
At above-mentioned a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop, described control signal output circuit comprises two and controls output unit, and each control unit comprises two XOR gate, two NAND gate and six inverters; The input of the XOR gate XOR1 of one of them control unit is connected with control signal UP with power vd D respectively, and output is connected with NAND gate NAND1; The input of XOR gate XOR2 is connected with ground with control signal UP respectively, and output is connected with NAND gate NAND2; The input of NAND gate NAND1 is connected with the output of NAND2 with the output of XOR1 respectively, exports termination inverter INV1; The input of NAND gate NAND2 is connected with the output of NAND1 with the output of XOR2 respectively, exports termination inverter INV4; Inverter INV1 ~ INV3 joins end to end successively, and wherein the input of INV1 is connected with the output of NAND1, and the output of INV3 exports control signal UPB1; Inverter INV4 ~ INV6 joins end to end successively, and wherein the input of INV4 is connected with the output of NAND2, and the output of INV6 exports control signal UP1; The input of the XOR gate XOR3 of another control unit is connected with ground with control signal DOWN respectively, and output is connected with NAND gate NAND3; The input of XOR gate XOR4 is connected with power vd D with control signal DOWN respectively, and output is connected with NAND gate NAND4; The input of NAND gate NAND3 is connected with the output of NAND4 with the output of XOR3 respectively, exports termination inverter INV7; The input of NAND gate NAND4 is connected with the output of NAND3 with the output of XOR4 respectively, exports termination inverter INV10; Inverter INV7 ~ INV9 joins end to end successively, and wherein the input of INV7 is connected with the output of NAND3, and the output of INV9 exports control signal DOWN1; Inverter INV10 ~ INV12 joins end to end successively, and wherein the input of INV10 is connected with the output of NAND4, and the output of INV12 exports control signal DOWNB1.
At above-mentioned a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop, described reset, delay circuit comprise NOR gate, inverter and metal-oxide-semiconductor; Wherein the input of NOR gate NOR1 is connected with the output Qn of two d type flip flops respectively, output is connected with inverter INV13, inverter INV13 ~ INV20 joins end to end successively, the drain electrode of metal-oxide-semiconductor Q1 ~ Q8 is connected with the output of inverter INV13 ~ INV20 respectively, source electrode is connected with the grid of metal-oxide-semiconductor Q9 ~ Q16 respectively, wherein the grid of Q1 with Q5 is connected with power vd D, the grid of Q2 with Q6 with or the output of door OR1 be connected, the grid of Q3 with Q7 is connected with the first PLC technology signal simultaneously, and the grid of Q4 with Q8 is connected with the output of door AND1; Source electrode and the drain electrode of metal-oxide-semiconductor Q9 ~ Q16 are all connected to the ground, and grid is connected with the source electrode of Q1 ~ Q8 respectively; Or the input of door OR1 connects the first PLC technology signal and the second PLC technology signal respectively, export the grid of termination Q2 and Q5; Connect PLC technology signal first PLC technology signal and the second PLC technology signal respectively with the input of door AND1, export the grid of termination Q4 and Q8.
Therefore, tool of the present invention has the following advantages: 1, reasonable in design, structure is easily understood, and can be completely achieved.2, have programmable delay function, flexibility is good.3, zero dead band.4, four tunnel control signals can be produced.5, low-power consumption.
Accompanying drawing explanation
Fig. 1 is the structure chart of phase-locked loop.
Fig. 2 is the structure chart of phase frequency detector of the present invention.
Fig. 3 is frequency plot testing circuit structure chart.
Fig. 4 is control signal output circuit structure figure.
Fig. 5 is reset, delay circuit structure chart.
Fig. 6 is the overall circuit figure of phase frequency detector.
Fig. 7 is the structure chart of charge pump circuit.
Embodiment
In order to the explanation the object, technical solutions and advantages of the present invention clearly understood, below in conjunction with drawings and Examples, the present invention is further detailed.
The structure of programmable delay multi-way control signals phase frequency detector as shown in Figure 2, its composition comprise input connect two road frequency signals and for the frequency that detects this two-way frequency signal and phase place frequency plot testing circuit, the control signal that frequency plot testing circuit produces is formed four tunnels after treatment can arrive the control signal output circuit of the control signal of charge pump and the control signal of reading frequency phase detecting circuit simultaneously, then frequency plot testing circuit is resetted and the reset of delays time to control, delay circuit; Wherein, frequency plot testing circuit is connected with reset, delay circuit with two road frequency signals, control signal output circuit respectively; Control signal output circuit is connected with frequency plot testing circuit; Reset, delay circuit are connected with frequency plot testing circuit.
Fig. 3 is frequency plot testing circuit schematic diagram.F
1and f
2 aretwo road frequency signals.F
1produced by crystal oscillator, it is held with the CLK of d type flip flop DFF1 and is connected.F
2be the output signal of frequency divider, it is held with the CLK of d type flip flop DFF2 and is connected.Frequency plot testing circuit is made up of d type flip flop DFF1 and DFF2.The CLK end of DFF1 and f
1be connected, D end is connected with power vd D, output Q and Qn respectively output signals UP with
.The CLK end of DFF2 and f
2be connected, D end be connected with power vd D, output Q and Qn output signal respectively DOWN with
.
Fig. 4 is control signal output circuit schematic diagram.It is by XOR gate XOR1 ~ XOR4, NAND gate NAND1 and NAND2(NAND3 and NAND4) the basic trigger of RS that forms and inverter INV1 ~ INV12 form.The input of XOR gate XOR1 is connected with control signal UP with power vd D respectively, and output is connected with NAND gate NAND1.The input of XOR gate XOR2 is connected with ground with control signal UP respectively, and output is connected with NAND gate NAND2.The input of XOR gate XOR3 is connected with ground with control signal DOWN respectively, and output is connected with NAND gate NAND3.The input of XOR gate XOR4 is connected with power vd D with control signal DOWN respectively, and output is connected with NAND gate NAND4.The input of NAND gate NAND1 is connected with the output of NAND2 with the output of XOR1 respectively, exports termination inverter INV1.The input of NAND gate NAND2 is connected with the output of NAND1 with the output of XOR2 respectively, exports termination inverter INV4.The input of NAND gate NAND3 is connected with the output of NAND4 with the output of XOR3 respectively, exports termination inverter INV7.The input of NAND gate NAND4 is connected with the output of NAND3 with the output of XOR4 respectively, exports termination inverter INV10.Inverter INV1 ~ INV3 joins end to end successively, and wherein the input of INV1 is connected with the output of NAND1, and the output of INV3 exports control signal UPB1.Inverter INV4 ~ INV6 joins end to end successively, and wherein the input of INV4 is connected with the output of NAND2, and the output of INV6 exports control signal UP1.Inverter INV7 ~ INV9 joins end to end successively, and wherein the input of INV7 is connected with the output of NAND3, and the output of INV9 exports control signal DOWN1.Inverter INV10 ~ INV12 joins end to end successively, and wherein the input of INV10 is connected with the output of NAND4, and the output of INV12 exports control signal DOWNB1.
Fig. 5 is reset, delay circuit schematic diagram.Reset circuit is made up of NOR gate NOR1.The input of NOR1 respectively with control signal
with
be connected, output is connected with inverter INV13.Delay circuit is by inverter INV13 ~ INV20, metal-oxide-semiconductor Q1 ~ Q16 or door OR1 and form with door AND1.Inverter INV13 ~ INV20 joins end to end successively, and wherein the input of INV13 is connected with NOR1, and the output of INV20 exports reset signal V0.The drain electrode of metal-oxide-semiconductor Q1 ~ Q8 is connected with the output of inverter INV13 ~ INV20 respectively, source electrode is connected with the grid of metal-oxide-semiconductor Q9 ~ Q16 respectively, wherein the grid of Q1 with Q5 is connected with power vd D, the grid of Q2 with Q6 with or the output of door OR1 be connected, the grid PLC technology signal Delay<1> of Q3 with Q7 is connected, and the grid of Q4 with Q8 is connected with the output of door AND1.Source electrode and the drain electrode of metal-oxide-semiconductor Q9 ~ Q16 are all connected to the ground, and grid is connected with the source electrode of Q1 ~ Q8 respectively.Or the input of door OR1 meets PLC technology signal Delay<0> and Delay<1> respectively, export the grid of termination Q2 and Q5.Meet PLC technology signal Delay<0> and Delay<1> respectively with the input of door AND1, export the grid of termination Q4 and Q8.
Illustrate embodiment of the present invention and the principle of optimality below:
Fig. 6 is the overall circuit schematic diagram of phase frequency detector.Wherein d type flip flop selects the TSPC structure of edging trigger, and its transistor size used is few, effectively can reduce the area of circuit, and it does not have quiescent dissipation, and dynamic power consumption is also very low.
The basic RS filpflop that circuit in dotted line is made up of two XOR gate and two NAND gate is formed.Wherein XOR gate XOR1 (XOR3) is equivalent to inverter, and XOR gate XOR2 (XOR4) is equivalent to transmission gate, is only used to match with XOR1 (XOR3), makes signal can reach two inputs of rest-set flip-flop simultaneously.They with by NAND gate NAND1 and NAND2(NAND3 with NAND4) signal that d type flip flop exports is transformed into two paths of signals, a road high level, a road low level together with basic RS filpflop.This structure can change the two paths of signals that d type flip flop exports into four tunnel control signals, and charge pump can be arrived simultaneously, effectively prevent the delayed charge or discharge problem that charge pump causes because of control signal time delay disunity, effectively reduce the shake of phase-locked loop and spuious.
The structure chart of charge pump as shown in Figure 7, metal-oxide-semiconductor Q17 and Q18 is switch, compared with traditional structure, difference is metal-oxide-semiconductor Q19 and Q20(Q21 and Q22) electric capacity that forms is connected on VDD(VSS respectively) and control signal UP1(DOWNB1) between and switch Q17(Q18) drain electrode and control signal UP1(DOWNB1) between.When UPB1 is high level, switch Q17 turns off, if the electric capacity do not added, the drain terminal voltage of Q17 can draw high as supply voltage VDD by the parasitic capacitance of switch Q17 source and drain, causes electric charge to share.And the electric capacity Q20 one end added is connected with the drain electrode of Q17, the other end is connected with UP1, so the parasitic capacitance of Q17 and electric capacity Q20 are series connection between VDD and UP1, the drain voltage of such Q17 can by pincers at a voltage lower than VDD, this just well reduces electric charge and shares, in addition, when switch OFF, this electric capacity also can consume a part of channel charge very soon, reduces charge injection problem.Q19 is connected between VDD and UP1, further can suppress signal jitter, reduces noise.The operation principle of Q21 with Q22 is identical with Q19 with Q20.
The time delay that delay circuit produces can eliminate the dead band of charge pump, increases phase frequency detector to the susceptibility of phase difference.It is in series primarily of eight grades of inverters (INV14-INV21), the load capacitance of a nmos switch and a NMOS tube formation has been added at each output of eight grades of inverters, extend the delay time of each inverter like this, avoid simultaneously and use a lot of level inverter to reach the object increasing delay time, and use metal-oxide-semiconductor electric capacity can save a lot of areas than use metal capacitance.NMOS tube Q1 in figure ~ Q8 is control switch, and their on off operating mode decides the size of circuit delay time.Due to NMOS tube Q9 ~ Q16 be coupling, so their form electric capacity can be similar to regard as equal.If the delay time of each load capacitance to be equivalent to a unit time delay, so this circuit has eight timers.By control signal Delay<1> and Delay<0>, there are four kinds of delay times below available: the first is Delay<0>=0, Delay<1>=0, Q1 and Q5 conducting, the time delay of You Liangge unit; The second is Delay<0>=1, Delay<1>=0, Q1, Q2, Q5 and Q6 conducting, has four unit time delays; The third is Delay<0>=0, Delay<1>=1, Q1, Q2, Q3, Q5, Q5 and Q7 conducting, has six unit time delays; 4th kind is Delay<0>=1, Delay<1>=1, and Q1 ~ Q8 is conducting, has eight unit time delays.Can programme as required and select different delay times, so that deadband eliminating.
Claims (2)
1. the programmable delay multi-way control signals phase frequency detector for phase-locked loop, it is characterized in that, comprise input connect two road frequency signals and for the frequency and phase place that detect this two roads frequency signal frequency plot testing circuit, the control signal that frequency plot testing circuit produces is formed four tunnels after treatment can arrive the control signal output circuit of the control signal of charge pump and the control signal of reading frequency phase detecting circuit simultaneously, then frequency plot testing circuit is resetted and the reset of delays time to control, delay circuit; Wherein, frequency plot testing circuit is connected with reset, delay circuit with two road frequency signals, control signal output circuit respectively; Control signal output circuit is connected with frequency plot testing circuit; Reset, delay circuit are connected with frequency plot testing circuit;
Described frequency plot testing circuit comprises two d type flip flop DFF1 and DFF2; The CLK end of described two d type flip flop DFF1 and DFF2 connects two road frequency signals, D termination power VDD respectively, and output Q connects the input of control signal output circuit, and output Qn connects the input of reset, delay circuit;
Described control signal output circuit comprises two and controls output unit, and each control unit comprises two XOR gate, two NAND gate and six inverters; The input of the XOR gate XOR1 of one of them control unit is connected with control signal UP with power vd D respectively, and output is connected with NAND gate NAND1; The input of XOR gate XOR2 is connected with ground with control signal UP respectively, and output is connected with NAND gate NAND2; The input of NAND gate NAND1 is connected with the output of NAND2 with the output of XOR1 respectively, exports termination inverter INV1; The input of NAND gate NAND2 is connected with the output of NAND1 with the output of XOR2 respectively, exports termination inverter INV4; Inverter INV1 ~ INV3 joins end to end successively, and wherein the input of INV1 is connected with the output of NAND1, and the output of INV3 exports control signal UPB1; Inverter INV4 ~ INV6 joins end to end successively, and wherein the input of INV4 is connected with the output of NAND2, and the output of INV6 exports control signal UP1; The input of the XOR gate XOR3 of another control unit is connected with ground with control signal DOWN respectively, and output is connected with NAND gate NAND3; The input of XOR gate XOR4 is connected with power vd D with control signal DOWN respectively, and output is connected with NAND gate NAND4; The input of NAND gate NAND3 is connected with the output of NAND4 with the output of XOR3 respectively, exports termination inverter INV7; The input of NAND gate NAND4 is connected with the output of NAND3 with the output of XOR4 respectively, exports termination inverter INV10; Inverter INV7 ~ INV9 joins end to end successively, and wherein the input of INV7 is connected with the output of NAND3, and the output of INV9 exports control signal DOWN1; Inverter INV10 ~ INV12 joins end to end successively, and wherein the input of INV10 is connected with the output of NAND4, and the output of INV12 exports control signal DOWNB1.
2. a kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop according to claim 1, it is characterized in that, described reset, delay circuit comprise NOR gate, inverter and metal-oxide-semiconductor; Wherein the input of NOR gate NOR1 is connected with the output Qn of two d type flip flops respectively, output is connected with inverter INV13, inverter INV13 ~ INV20 joins end to end successively, the drain electrode of metal-oxide-semiconductor Q1 ~ Q8 is connected with the output of inverter INV13 ~ INV20 respectively, source electrode is connected with the grid of metal-oxide-semiconductor Q9 ~ Q16 respectively, wherein the grid of Q1 with Q5 is connected with power vd D, the grid of Q2 with Q6 with or the output of door OR1 be connected, the grid of Q3 with Q7 is connected with the first PLC technology signal simultaneously, and the grid of Q4 with Q8 is connected with the output of door AND1; Source electrode and the drain electrode of metal-oxide-semiconductor Q9 ~ Q16 are all connected to the ground, and grid is connected with the source electrode of Q1 ~ Q8 respectively; Or the input of door OR1 connects the first PLC technology signal and the second PLC technology signal respectively, export the grid of termination Q2 and Q5; Connect PLC technology signal first PLC technology signal and the second PLC technology signal respectively with the input of door AND1, export the grid of termination Q4 and Q8.
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| EP3217558B1 (en) * | 2016-03-11 | 2020-05-13 | Socionext Inc. | Timing-difference measurement |
| CN109302179B (en) * | 2018-09-03 | 2022-04-19 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sampling logic tolerance circuit |
| CN109596854B (en) * | 2018-12-03 | 2020-11-06 | 湖南湘依铁路机车电器股份有限公司 | Method and structure for preventing speed sensor from generating error pulse during parking shake |
| CN111884636B (en) * | 2020-06-17 | 2024-04-12 | 芯创智（北京）微电子有限公司 | RS trigger output delay compensating circuit |
| CN113098498B (en) * | 2021-04-01 | 2023-12-01 | 南京航空航天大学 | Blind eliminating PFD circuit based on recovery mechanism |
| CN116915243B (en) * | 2023-09-12 | 2023-12-26 | 思特威(上海)电子科技股份有限公司 | Phase-locked loop circuit and image sensor |
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