CN105610430A - Dual-mode self switching radiation hardening clock generation circuit based on phase-locked loops - Google Patents
Dual-mode self switching radiation hardening clock generation circuit based on phase-locked loops Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention provides a dual-mode self switching radiation hardening clock generation circuit based on phase-locked loops, which is mainly composed of two independent phase-locked loops, a delay unit, an error detection unit and a clock selection unit. The two independent phase-locked loops are charge pump phase-locked loops not subjected to radiation hardening, and used for providing corresponding clock output; the delay unit realizes the delay of output signals of the phase-locked loops; the error detection unit is used for detecting whether two output signals of a phase frequency detector in a main phase-locked loop are right and outputting corresponding indication signals; and the clock selection unit performs selective output on the delayed output of the two phase-locked loops as the final output. The dual-mode self switching radiation hardening clock generation circuit based on the phase-locked loops provided by the invention can eliminate interference of a single event effect in a radiation environment on a circuit working state to a great extent, ensure the stability of the phase-locked loops as clock signals, improve the reliability of the system, and has the advantages of being easy in implementation, small in area, low in power consumption and so on.
Description
Technical field
The present invention relates to a kind of clock forming circuit based on phaselocked loop, relate in particular to a kind of bimodulus adaptive switched anti-Radiation hardened clock forming circuit, can effectively eliminate and suppress single-ion transient state (SET) effect.
Background technology
Along with constantly dwindling of integrated circuit characteristic size, for energetic particle hits institute in irradiation space environmentSingle-ion transient state (SET) effect causing can not be ignored all the more. Stable system clock be at a high speed guarantee beThe key of system high speed steady running, when single-ion transient state (SET) effect not only can make the output of phaselocked loopClock signal makes a mistake, and the clock of mistake also will cause data transmission fault whole system paralysis even.
For the seriousness of single particle effect, use with the phaselocked loop of radiation tolerance design system clock is providedSeem very necessary. According to the analysis to phaselocked loop single particle effect, its inside of the phase-locked loop circuit of non-reinforcingHave many places sensitive nodes, the especially analog module such as charge pump and voltage controlled oscillator, once be subject to once singleParticle disturbance, just needs a period of time can be restored to stable state.
For existing phaselocked loop radiation hardening technology, be mainly divided into two classes: a class is in phaselocked loopPortion's many places sensitive nodes carries out the modes such as redundancy or compensation and reinforces. Due to the inner sensitive nodes of phaselocked loopMany, the larger node of impact can only be carried out to Design of Reinforcement, so just from large probability, SET effect is enteredRow is reinforced, and error rate is reduced to part; Another kind of for phaselocked loop is carried out to system-level reinforcing, i.e. triplication redundancyReinforce, because phaselocked loop is copied three parts by which, consume larger power consumption and area.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of bimodulus based on phaselocked loop adaptive switched radioresistanceReinforce clock forming circuit, both possessed the consolidation effect of high reliability, possess again simultaneously low in energy consumption, area is littleAdvantage.
Technical scheme of the present invention is:
The adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, is characterized in that: bagDraw together main road phaselocked loop and bypass phaselocked loop, main road delay unit and bypass delay unit, error detection unit andClock selecting unit; Main road phaselocked loop and bypass phaselocked loop are the charge pump phase lock loop that does not pass through radiation hardening,Clock signal output is provided respectively; Main road delay unit carries out time delay to the clock signal of main road phaselocked loop outputObtain the time delay output of main road pll clock signal; The clock of bypass delay unit to the output of bypass phaselocked loopSignal carries out time delay and obtains the time delay output of bypass pll clock signal; Described error detection unit is to masterIn the phaselocked loop of road, two of phase frequency detector output signals detect and export index signal, work as frequency and phase discriminationWhen two output signals of device are identical, the index signal of error detection unit output is the first level signal, whenWhen two output signals of phase frequency detector are different, the index signal of error detection unit output is second electrical levelSignal; Clock selecting unit is selected as final output, main road the time delay output of two-way phaselocked loopThe time delay of the time delay output He Fu road pll clock signal of pll clock signal is exported as clock selecting listTwo clock inputs of unit, the index signal of error detection unit output is defeated as the control of clock selecting unitEnter, in the time that the index signal of error detection unit is the first level signal, main road lock is selected in clock selecting unitThe time delay of ring is output as final output mutually, in the time that the index signal of error detection unit is second electrical level signal,Clock selecting unit selects the time delay of bypass phaselocked loop to be output as final output.
Described the first level signal is high level, and second electrical level signal is low level.
Described main road phaselocked loop and bypass phaselocked loop are identical unit, respectively by phase frequency detector, electric chargePump, wave filter, voltage controlled oscillator and frequency divider form; The output signal of external reference signal and frequency divider is doneFor two input signals of phase frequency detector, the input signal of two output signal charge pumps of phase frequency detector,The output of charge pump connects the input of wave filter, and the output of wave filter connects the input of voltage controlled oscillator, VCOThe output of device is as the clock signal of phaselocked loop output, and the while is as the input of frequency divider, the output of frequency dividerAs the input of phase frequency detector, thereby form a loop; In the time that stabilized is worked, frequency and phase discriminationTwo output signals of device are two pulse-period signal with same pulse width, and its rising edge and declineAlong complete matching; In the time that phase-locked loop operation is abnormal, two output signal pulsewidths of phase frequency detector change,The frequency of variable quantity and pll output signal and phase place be varied to direct ratio, can directly react phase-locked loop operationAbnormal conditions.
Described main road delay unit and bypass delay unit are identical unit, all adopt chain of inverters structure;Input signal, by the propagation in chain of inverters, makes output signal have prolonging of corresponding time compared with input signalLate time t, wherein time delay, t should at least be greater than time in an external reference signal cycle.
Described error detection unit is by XOR gate, filter capacitor C, the first drive circuit, NMOS pipe, electricityStream source, electric capacity and the second drive circuit composition, in main road phaselocked loop, two of phase frequency detector output signals are doneFor the input of XOR gate, the output of XOR gate connects one end of filter capacitor C, and as the first drive circuitInput, the other end ground connection of filter capacitor C; The output of the first drive circuit connects the grid of NMOS pipe,The drain electrode of NMOS pipe is connected with the output of current source, the source ground of NMOS pipe, one end of electric capacity withThe drain electrode of NMOS pipe is connected, the other end ground connection of electric capacity, and whether the effective current source of controlling of NMOS is to electricityHold and charge; Current source input is connected with power vd D; The drain electrode of NMOS pipe and second drives electricityThe input on road is connected, and the output of the second drive circuit is exported described index signal.
Clock selecting unit comprise first with door, second and door, phase inverter, the first d type flip flop, the 2nd DTrigger, 3d flip-flop, four d flip-flop, the 3rd with door, the 4th with door and or door;
Wherein index signal is connected with input of door and the input of phase inverter with first respectively, simultaneouslyAnother input of the QN termination first of four d flip-flop and door, first with the output of door as firstThe D end input of d type flip flop; The time delay output of main road pll clock signal respectively with the first d type flip flopCK end, 3d flip-flop CK end, the 3rd are connected with an input of door; The Q of the first d type flip flopEnd output is connected with the D end input of 3d flip-flop, and the Q end of 3d flip-flop is exported and connect with doorAnother input; The output of the output of phase inverter and the QN of 3d flip-flop end as second with the input of door,Second inputs as the D end of the second d type flip flop with the output of door, and the time delay of spoke road pll clock signal is defeatedGo out respectively with the CK end of the second d type flip flop be connected, the CK end of four d flip-flop and the 4th withOne input is connected; The Q end output of the second d type flip flop is connected with the D end input of four d flip-flop, DThe Q end of trigger is exported and is connected with another input of door; The 3rd with door output and the 4th with door defeatedGo out as or door input; Or the output of door is the clock output signal of clock selecting unit.
The present invention's advantage is compared with prior art: due to the adaptive switched structure of bimodulus of the present invention's employing,If the main road pll output signal as final output signal in circuit occurs extremely, system can be cut immediatelyChange to the output of bypass phaselocked loop as final output, when error detection unit points out main road phase-locked loop operation extensiveAfter multiple stable state, system can be switched to again the output of main road phaselocked loop as final output, and system is by twoAdaptive switched between the pll output signal of road, utilizes the less resource moment to ensure to be finally output as when correctClock output, has and realizes the advantages such as convenient, area is little, low in energy consumption, and itself has well single-ion transient stateImmunity, when the single event transient pulse that occurs in inside configuration arbitrary node all can not make two-way phaselocked loopThere is disturbance simultaneously and guarantee that whole circuit has high anti-single particle transient state ability in clock output.
Brief description of the drawings
Fig. 1 is the adaptive switched radiation hardening clock forming circuit of the bimodulus based on phaselocked loop structured flowchart;
Fig. 2 is phaselocked loop schematic diagram;
Fig. 3 is delay unit schematic diagram;
Fig. 4 is error detection unit schematic diagram;
Fig. 5 is clock selecting cell schematics.
Detailed description of the invention
As shown in Figure 1, the adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, by main roadPhaselocked loop 1 and bypass phaselocked loop 2, main road delay unit 3 and bypass delay unit 5, error detection unit 4Form with clock selecting unit 6; Main road phaselocked loop 1 and bypass phaselocked loop 2 are not pass through radiation hardeningCharge pump phase lock loop, provides respectively clock signal output; Main road delay unit 3 is exported main road phaselocked loop 1Clock signal PLL-CLK1 carry out time delay and obtain the time delay output CK1 of main road pll clock signal; AuxiliaryThe clock signal PLL-CLK1 that road delay unit 5 is exported bypass phaselocked loop 2 carries out time delay and obtains bypass lockEncircle mutually the time delay output CK2 of clock signal; Described error detection unit 4 is to frequency discrimination in main road phaselocked loop 1Two output signals UP, DN of phase discriminator detect and export index signal Error, when two workWhen status signal is identical, the index signal Error that error detection unit 4 is exported is the first level signal, whenWhen two working state signals are different, the index signal Error that error detection unit 4 is exported is second electrical levelSignal; Clock selecting unit 6 is selected as final output the time delay output of two-way phaselocked loop, mainThe time delay output CK2 of the time delay output CK1He Fu road pll clock signal of road pll clock signal doesFor two clock inputs of clock selecting unit 6, the index signal Error that error detection unit 4 is exported doesFor the control inputs of clock selecting unit 6, when the index signal of error detection unit 4 is the first level signalTime, it is final output that the time delay output CK1 of main road phaselocked loop 1 is selected in clock selecting unit 6, works as errorWhen the index signal of detecting unit 4 is second electrical level signal, bypass phaselocked loop 2 is selected in clock selecting unit 6Time delay output CK2 be final output. Preferably, described the first level signal is high level, the second electricityFlat signal is low level.
As shown in Figure 2, main road phaselocked loop 1 is identical with bypass phaselocked loop 2 structures, is typical charge pump lockXiang Huan, by phase frequency detector 211, charge pump 212, wave filter 213, voltage controlled oscillator 214 and frequency divisionDevice 215 forms. The output signal of external reference signal FREF and frequency divider 25 is as phase frequency detector 211Input, two of phase frequency detector 211 output UP and DN are the input of charge pump 212, charge pump212 output connects the input of wave filter 213, and the output of wave filter 213 connects the input of voltage controlled oscillator 214,The output of voltage controlled oscillator 214 connects the input of frequency divider 215, and the output of frequency divider 215 takes back frequency and phase discriminationDevice 211 forms a loop. Wherein in the time that stabilized is worked, two outputs of phase frequency detector 211Signal UP and DN are two pulse-period signal with same pulse width, and its rising edge and trailing edgeComplete matching; In the time that phase-locked loop operation is abnormal, two output signals UP of phase frequency detector 211 and DNPulsewidth changes, the frequency of variable quantity and pll output signal and phase place be varied to direct ratio, can be directReaction phase-locked loop operation abnormal conditions.
As shown in Figure 3, main road delay unit 3 and bypass delay unit 5 are identical unit, all adopt anti-Phase device chain structure. Input signal, by the propagation in chain of inverters, makes output signal have compared with input signalT time delay of corresponding time, wherein time delay t should at least be greater than a reference-input signal cycle timeBetween, specifically can by design corresponding progression chain of inverters, and in phase inverter metal-oxide-semiconductor design parameter comeRealize the design of time delay. Select the phase delay time, the output signal obtaining and input signal are apart from phaseOutside should postponing, it is identical signal.
As shown in Figure 4, described error detection unit 4 is driven by XOR gate 311, filter capacitor C312, firstMoving circuit 313, NMOS pipe 314, current source 315, electric capacity 316 and the second drive circuit 317 form,Two of phase frequency detector output signals UP in main road phaselocked loop 1, DN be as the input of XOR gate 311,The output of XOR gate 311 connects one end of filter capacitor C312, and as the input of the first drive circuit 313,The other end ground connection of filter capacitor C312; The output of the first drive circuit 313 connects NMOS pipe 314Grid a1, the drain electrode a2 of NMOS pipe 314 is connected with the output of current source 315, NMOS pipe 314Source ground, the drain electrode a2 of one end of electric capacity 316 and NMOS pipe 314 is connected, electric capacity 316Other end ground connection, whether NMOS pipe 314 is used for controlling current source 315 and electric capacity 316 is charged;Current source 315 inputs are connected with power vd D; Drain electrode and second drive circuit 317 of NMOS pipe 314Input be connected, the output of the second drive circuit 317 is exported described index signal Error. Work as main roadWhen phaselocked loop 1 steady operation, UP and DOWN have identical pulsewidth, output after XOR gate 311For low level, a0 node is low level, and the output of corresponding the first drive circuit 313 is also low level,NMOS pipe 314 is in off state, and current source 315 charges to electric capacity 316, and node a2 is highLevel, therefore the second drive circuit 317 is output as high level, i.e. index signal Error output high level,The clock signal that represents main road phaselocked loop 1 is normally exported. In the time of main road phaselocked loop 1 operation irregularity, UP andThe pulsewidth of DN can change, and the pulsewidth of the two can become along with the variation of phase-lock-ring output frequency and phase placeChange, XOR gate 311 can be exported high impulse, and pulse width is come by the variation size of frequency and phase place and normal valueDetermine; In the time that the output high impulse time of XOR gate 311 lengthening number increases, the charging of electric capacity 312 is reachedTo a certain extent, the voltage of node a0 exceedes certain threshold value, and the output of the first drive circuit 313 becomes heightLevel, opens NMOS pipe 314, and NMOS pipe 314 is connected to the ground node a2 after opening,The output state of the second drive circuit 317 changes simultaneously, index signal Error output low level, generationThe clock signal of table main road phaselocked loop 1 occurs abnormal. Along with phaselocked loop 1 recovers lock-out state again,The pulsewidth of UP and DN is tending towards identical, and electric capacity 312 discharges gradually, and node a0 recovers low level again, drivesThe output node a1 of moving circuit 313 becomes low level, and NMOS pipe 314 turn-offs, and current source 315 is to electricityHold 316 chargings again, a2 node voltage raises, and drive circuit 317 is output as high level, and error refers toShow that signal recovers high level, represents that the recovering clock signals of main road phaselocked loop 1 is normally exported. This error-detectingUnit can provide corresponding index signal according to the duty of phaselocked loop, in the time of phaselocked loop generation operation irregularity,This unit can be made fast detecting and provide error indication signal; In the time that phaselocked loop is resumed work again, shouldUnit can provide phaselocked loop through duplicate detection and recover normal enough stabilization time.
As shown in Figure 5, clock selecting unit 6 comprise first with door 418, second and 419, phase inverter420, the first d type flip flop 411, the second d type flip flop 412,3d flip-flop 413, the 4th D touchHair device 414, the 3rd with door 415, the 4th with door 416 and or door 417; Wherein index signal ErrorBe connected with the input of phase inverter 420 with an input of door 418 with first respectively, the 4th D touches simultaneouslyAnother input of the QN termination first of hair device 414 and door 418, first with the output conduct of door 418The D end input of the first d type flip flop 411; The time delay output CK1 of main road pll clock signal respectively withThe first d type flip flop 411CK end, 3d flip-flop 413CK end, the 3rd with an input of door 415End is connected; The Q end output of the first d type flip flop 411 is connected with the D end input of 3d flip-flop 413,The Q end output of 3d flip-flop 413 connects another input with door 415; The output of phase inverter 420With the QN end output of 3d flip-flop 413 as second with the input of door 419, second with door 419Output as the D end input of the second d type flip flop 412, the time delay output of spoke road pll clock signalCK2 is connected with the CK end of the second d type flip flop 412 respectively, the CK of four d flip-flop 414 hold withAnd the 4th be connected with an input of door 416; The Q end output of the second d type flip flop 412 is touched with the 4th DThe D end input of hair device 414 is connected, the Q end output of four d flip-flop 414 with another of door 416Input is connected; The 3rd with door 415 output and the 4th with the output of door 416 as or the input of door 417;Or the output of door 417 is the clock output signal of clock selecting unit 6.
Wherein error indication signal Error obtains the signal～Error of Error negate by phase inverter 420,Error signal and Error phase by after SECO and input as the first d type flip flop 411, then warpCross the SECO of two-stage d type flip flop 411 and 413, the output of 3d flip-flop 413 and main road lockEncircle mutually clock signal time delay output CK1 as the 3rd with the input of door 415, obtain Error signal and beThe clock signal of effectively exporting when high level;～Error signal with by after SECO～Error phase and workBe the input of the second d type flip flop 412, then pass through the SECO of two-stage d type flip flop 412 and 414,The time delay output CK2 of the output Yu Fu road pll clock signal of four d flip-flop 414 as the 4th withDoor 416 input, the effective clock signal of output when obtaining Error signal and being low level. Two-way clock letterThe input of number conduct or door 417, obtains final clock output signal, and the clock signal of final output existsWhen Error value is high, export CK1 signal, when Error value is low, export CK2 signal.
Adopt the above-mentioned clock selecting unit with SECO function, can eliminate in clock handoff procedureExisting burr, avoids system to switch and cause data transmission fault because of clock signal.
The unspecified content of the present invention is common practise of the present invention.
Claims (6)
1. the adaptive switched radiation hardening clock forming circuit of the bimodulus based on phaselocked loop, is characterized in that:Comprise main road phaselocked loop (1) and bypass phaselocked loop (2), main road delay unit (3) and bypass delay unit(5), error detection unit (4) and clock selecting unit (6); Main road phaselocked loop (1) and bypass are phase-lockedRing (2), for not passing through the charge pump phase lock loop of radiation hardening, provides respectively clock signal output; Main road prolongsShi Danyuan (3) carries out time delay to the clock signal (PLL-CLK1) of main road phaselocked loop (1) output and obtainsThe time delay output (CK1) of main road pll clock signal; Bypass delay unit (5) is to bypass phaselocked loop (2)The clock signal (PLL-CLK1) of output is carried out time delay and obtains the time delay output of bypass pll clock signal(CK2); Described error detection unit (4) is defeated to two of phase frequency detector in main road phaselocked loop (1)Go out signal (UP, DN) and detect and export index signal (Error), when two of phase frequency detector defeatedGo out signal when identical, the index signal (Error) of error detection unit (4) output is the first level signal,In the time that two output signals of phase frequency detector are different, the index signal of error detection unit (4) output(Error) be second electrical level signal; Clock selecting unit (6) carries out the time delay output of two-way phaselocked loopSelect as final output time delay output (CK1) He Fu road phaselocked loop of main road pll clock signalThe time delay output (CK2) of clock signal is as two clock inputs of clock selecting unit (6), error inspectionThe index signal (Error) of measurement unit (4) output is as the control inputs of clock selecting unit (6), whenWhen the index signal of error detection unit (4) is the first level signal, clock selecting unit (6) are selected mainThe time delay output (CK1) of road phaselocked loop (1) is final output, when the instruction of error detection unit (4)When signal is second electrical level signal, clock selecting unit (6) select the time delay output of bypass phaselocked loop (2)(CK2) be final output.
2. the adaptive switched radiation hardening clock of the bimodulus based on phaselocked loop according to claim 1 generates electricityRoad, is characterized in that: described the first level signal is high level, and second electrical level signal is low level.
3. the adaptive switched radiation hardening clock of the bimodulus based on phaselocked loop according to claim 1 generates electricityRoad, is characterized in that: described main road phaselocked loop (1) and bypass phaselocked loop (2) are identical unit,Respectively by phase frequency detector (211), charge pump (212), wave filter (213), voltage controlled oscillator (214)And frequency divider (215) forms; The output signal of external reference signal (FREF) and frequency divider is as frequency discriminationTwo input signals of phase discriminator (211), two output signals (UP) of phase frequency detector (211) and(DN) be the input signal of charge pump (212), the output of charge pump (212) connects wave filter (213)Input, the output of wave filter (213) connects the input of voltage controlled oscillator (214), voltage controlled oscillator (214)Output as the clock signal (PLL-CLK) of phaselocked loop output, defeated as frequency divider (215) simultaneouslyEnter, the output of frequency divider (215) is as the input of phase frequency detector (211), thus a loop of formation;In the time that stabilized is worked, two output signals (UP, DN) of phase frequency detector (211) are for havingTwo pulse-period signal of same pulse width, and its rising edge and trailing edge complete matching; When phaselocked loop workDo when abnormal, two output signals (UP, DN) pulsewidth of phase frequency detector (211) changes, and becomesThe frequency of change amount and pll output signal and phase place be varied to direct ratio, can directly react phase-locked loop operation differentReason condition.
4. the adaptive switched radiation hardening clock of the bimodulus based on phaselocked loop according to claim 1 generates electricityRoad, is characterized in that: described main road delay unit (3) and bypass delay unit (5) are identical listUnit, all adopts chain of inverters structure; Input signal, by the propagation in chain of inverters, makes output signalHave t time delay of corresponding time compared with input signal, wherein time delay, t should at least be greater than an external referenceThe time of signal period.
5. the adaptive switched radiation hardening clock of the bimodulus based on phaselocked loop according to claim 1 generates electricityRoad, is characterized in that: described error detection unit (4) by XOR gate (311), filter capacitor C (312),The first drive circuit (313), NMOS pipe (314), current source (315), electric capacity (316) and secondDrive circuit (317) composition, two output signals of phase frequency detector in main road phaselocked loop (1) (UP,DN) as the input of XOR gate (311), the output of XOR gate (311) meets filter capacitor C (312)One end, and as the input of the first drive circuit (313), another termination of filter capacitor C (312)Ground; The output of the first drive circuit (313) meets the grid (a1) of NMOS pipe (314), NMOSThe drain electrode (a2) of pipe (314) is connected with the output of current source (315), NMOS pipe (314)Source ground, one end of electric capacity (316) is connected with the drain electrode (a2) of NMOS pipe (314), electric capacity(316) other end ground connection, whether NMOS pipe (314) is used for controlling current source (315) to electric capacity(316) charge; Current source (315) input is connected with power vd D; NMOS manages (314)Drain electrode be connected with the input of the second drive circuit (317), the output of the second drive circuit (317)Export described index signal (Error).
6. the adaptive switched radiation hardening clock of the bimodulus based on phaselocked loop according to claim 1 generatesCircuit, is characterized in that: clock selecting unit (6) comprise first with door (418), second with (419),Phase inverter (420), the first d type flip flop (411), the second d type flip flop (412), 3d flip-flop(413), four d flip-flop (414), the 3rd with door (415), the 4th with door (416) and or door(417)；
Wherein index signal (Error) respectively with first with input and the phase inverter (420) of door (418)Input be connected, simultaneously another of the QN termination first of four d flip-flop (414) and door (418)Individual input, first inputs as the D end of the first d type flip flop (411) with the output of door (418);The time delay output (CK1) of main road pll clock signal respectively with the first d type flip flop (411) CK end,3d flip-flop (413) CK end, the 3rd is connected with an input of door (415); The one D triggersThe Q end output of device (411) is connected with the D end input of 3d flip-flop (413), and the 3rd D triggersThe Q end output of device (413) connects another input with door (415); The output of phase inverter (420) withThe QN end output of 3d flip-flop (413) as second with the input of door (419), second with door (419)Output as the D end input of the second d type flip flop (412), the time delay of spoke road pll clock signal is defeatedGo out that (CK2) is connected with the CK end of the second d type flip flop (412) respectively, four d flip-flop (414)CK end and the 4th be connected with an input of door 416; The Q end of the second d type flip flop (412) is defeatedGo out with the D end input of four d flip-flop (414) and be connected, the Q end output of d type flip flop (414) andBe connected with another input of door (416); The 3rd with door (415) output and the 4th with door (416)Output as or door (417) input; Or the output of door (417) is clock selecting unit (6)Clock output signal.
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