CN103001629B - Self-adapting changeable bandwidth phase-locked loop - Google Patents

Self-adapting changeable bandwidth phase-locked loop Download PDF

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CN103001629B
CN103001629B CN201110266339.2A CN201110266339A CN103001629B CN 103001629 B CN103001629 B CN 103001629B CN 201110266339 A CN201110266339 A CN 201110266339A CN 103001629 B CN103001629 B CN 103001629B
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nmos tube
detection signal
locked loop
phase
output current
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CN103001629A (en
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刘国军
朱红卫
李丹
胡冠斌
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention discloses a kind of self-adapting changeable bandwidth phase-locked loop, comprise phase-locked loop circuit, adaptation control circuit, threshold voltage generation circuit.Adaptation control circuit is used for detecting the control voltage of voltage controlled oscillator, and exports the first detection signal and the second detection signal.It is interval that first detection signal and the second detection signal are input to the operating frequency also automatically choosing phase-locked loop circuit in phase-locked loop circuit.The size that the first detection signal exported by adaptation control circuit and the second detection signal can also control the load of the delay cell of the current source of charge pump, the parameter of low pass filter and voltage controlled oscillator respectively carrys out the bandwidth of phase-locked loop circuit described in Automatic Optimal.

Description

Self-adapting changeable bandwidth phase-locked loop
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of self-adapting changeable bandwidth phase-locked loop.
Background technology
Phase Lock Technique generally adopts phase-locked loop circuit (Phase Locked Loop, PLL) to realize, and has proposed nearly 100 years, has been widely used in electronic system, simultaneously also more and more higher to the requirement of performance.The future developments such as existing PLL chip is high towards frequency, bandwidth, integrated level are large, low in energy consumption, cheap, powerful.Existing phase-locked loop is all the structures being optimized design based on particular frequency range, cannot carry out sectional bandwidth optimization in the scope of whole data code flow.
As shown in Figure 1, be the structured flowchart of existing phase-locked loop.Existing phase-locked loop comprises phase frequency detector, low pass filter, voltage controlled oscillator and frequency divider, described phase frequency detector receives the fractional frequency signal FB of input frequency signal FIN and output frequency signal FOUT, compares frequency difference or the difference rear output rising control signal UP and decline control signal DOWN of input frequency signal FIN and fractional frequency signal FB.Described rising control signal UP and decline control signal DOWN is input in described low pass filter and produces the control voltage VCRL shown in control voltage VCTRL and Fig. 2.Control voltage VCRL is input in described voltage controlled oscillator and produces output frequency signal FOUT.
As shown in Figure 2, be the oscillogram of each signal of existing phase-locked loop.Described rising control signal UP is activated by the rising edge of described input frequency signal FIN, and decline control signal DOWN is activated by the rising edge of described fractional frequency signal FB.The overlapping internal latency by described phase frequency detector of described rising control signal UP and described decline control signal DOWN determines.Described rising control signal UP can control the capacitor charging to described low pass filter, thus makes the control voltage VCRL of the output of described low pass filter increase; After described decline control signal DOWN triggers, described control voltage VCRL stops rising.Described control voltage VCRL can change the output frequency signal FOUT of described voltage controlled oscillator, and the fractional frequency signal FB of described output frequency signal FOUT finally can be made identical with phase place with the frequency of described input frequency signal FIN.
Existing phase-locked loop generally all designs based on particular frequency range, and its structure also can only be optimized design based on particular frequency range.Existing phase-locked loop cannot carry out sectional bandwidth optimization in the scope of whole data code flow.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of self-adapting changeable bandwidth phase-locked loop, automatically can choose the operating frequency interval of phase-locked loop circuit and the bandwidth to adaptive optimization phase-locked loop circuit.
For solving the problems of the technologies described above, self-adapting changeable bandwidth phase-locked loop provided by the invention comprises a phase-locked loop circuit, an adaptation control circuit, a threshold voltage generation circuit.
Described phase-locked loop circuit comprises phase frequency detector, charge pump, low pass filter and voltage controlled oscillator.
Described threshold voltage generation circuit is used for providing two threshold voltage signals to described adaptation control circuit, and wherein first threshold voltage signal is greater than Second Threshold voltage signal.
Described adaptation control circuit is used for detecting the control voltage of described voltage controlled oscillator, described adaptation control circuit compares described control voltage and described first threshold voltage signal and exports the first detection signal, and described adaptation control circuit compares described control voltage and described Second Threshold voltage signal and exports the second detection signal.
Described first detection signal and described second detection signal are input to charge pump, voltage controlled oscillator and low pass filter three modules in described phase-locked loop circuit, and automatically select the parameter of described charge pump, described voltage controlled oscillator and described low pass filter, make the bandwidth Automatic Optimal of described phase-locked loop circuit.
Further improvement is, the current source of described charge pump comprises charging current source and discharging current source; Described electric charge delivery side of pump is received on described low pass filter, and the current source of described charge pump carries out discharge and recharge to described low pass filter and exports described control voltage; Described first detection signal and described second detection signal to be input in described charge pump and automatically to choose the described charging current source of described charge pump and the size in described discharging current source, by choosing the bandwidth of phase-locked loop circuit described in the described charging current source of different size and described discharging current source Automatic Optimal.
Further improvement is, described charging current source is a multipath current-source, comprise the first reference current, first via output current, the second road output current and the 3rd road output current, output in described low pass filter after described first via output current, described second road output current and described 3rd road output current merge; Described second road output current is connected in series the first PMOS, and described first PMOS grid connects the inversion signal of described first detection signal, is controlled the break-make of described second road output current by described first detection signal; Described 3rd road output current is connected in series the second PMOS, and described second PMOS grid connects the inversion signal of described second detection signal, is controlled the break-make of described 3rd road output current by described second detection signal.Described discharging current source is a multipath current-source, comprise the 4th road output current, the 5th road output current and the 6th road output current, output in described low pass filter after described 4th road output current, described 5th road output current and described 6th road output current merge; Described 5th road output current is connected in series the first NMOS tube, and described first NMOS tube grid connects described first detection signal, is controlled the break-make of described 5th road output current by described first detection signal; Described 6th road output current is connected in series the second NMOS tube, and described second NMOS tube grid connects described second detection signal, is controlled the break-make of described 6th road output current by described second detection signal.
Further improvement is, described low pass filter comprises and is series at resistance between described control voltage and ground and the first electric capacity, and described resistance is connected with described control voltage, described first electric capacity is connected with ground; Described first detection signal and described second detection signal to be input in described low pass filter and automatically to choose the parameter of described low pass filter, the parameter of described low pass filter comprise the size of described resistance, the size of the first electric capacity; By the bandwidth of phase-locked loop circuit described in the parameter automatic optimization of choosing the described low pass filter of different size.
Further improvement is, described low pass filter also comprises the second electric capacity, described second electric capacity is connected between described control voltage and ground, described resistance and described first electric capacity of described second electric capacity and series connection form parallel-connection structure, and the parameter of described low pass filter also comprises the size of described second electric capacity.
Further improvement is, described resistance is connected in series by the first resistance, the second resistance and the 3rd resistance and forms; Two ends first switch in parallel of described second resistance, described first switch is controlled by described first detection signal, and described in when described first switch cuts out, the second resistance is shorted; The two ends second switch in parallel of described 3rd resistance, described second switch is controlled by described second detection signal, and described in when described second switch is closed, the 3rd resistance is shorted.
Further improvement is, the ring retard that described voltage controlled oscillator is connected to form by multiple delay cell forms, described first detection signal and described second detection signal to be input in each described delay cell and automatically to choose the size of the load of each described delay cell, by the bandwidth of phase-locked loop circuit described in the load Automatic Optimal of choosing each described delay cell of different size.
Further improvement is, the load of each described delay cell comprises the first load in parallel, the second load and the 3rd load.Described first load comprises the 3rd NMOS tube and the 4th NMOS tube, source electrode all ground connection of described 3rd NMOS tube and described 4th NMOS tube, the grid that the drain electrode of described 3rd NMOS tube connects the grid of described 4th NMOS tube, the drain electrode of described 4th NMOS tube connects described 3rd NMOS tube; The drain electrode of described 3rd NMOS tube connects the negative output terminal of described delay cell, the drain electrode of described 4th NMOS tube connects the positive output end of described delay cell.Described second load comprises the 5th NMOS tube and the 6th NMOS tube, source electrode all ground connection of described 5th NMOS tube and described 6th NMOS tube, the grid that the drain electrode of described 5th NMOS tube connects the grid of described 6th NMOS tube, the drain electrode of described 6th NMOS tube connects described 5th NMOS tube; The drain electrode of described 5th NMOS tube connects the source electrode of the 7th NMOS tube, the drain electrode of described 7th NMOS tube is connected with described negative output terminal, and the drain electrode of described 6th NMOS tube connects the source electrode of the 8th NMOS tube, the drain electrode of described 8th NMOS tube connects described positive output end; The grid of described 7th NMOS tube and described 8th NMOS tube all connects described first detection signal, and described first detection signal controls the break-make of described second load.Described 3rd load comprises the 9th NMOS tube and the tenth NMOS tube, source electrode all ground connection of described 9th NMOS tube and described tenth NMOS tube, the grid that the drain electrode of described 9th NMOS tube connects the grid of described tenth NMOS tube, the drain electrode of described tenth NMOS tube connects described 9th NMOS tube; The drain electrode of described 9th NMOS tube connects the source electrode of the 11 NMOS tube, the drain electrode of described 11 NMOS tube is connected with described negative output terminal, described tenth NMOS tube drain electrode connects the source electrode of the 12 NMOS tube, the drain electrode of described 12 NMOS tube connects described positive output end; The grid of described 11 NMOS tube and described 12 NMOS tube all connects described second detection signal, and described second detection signal controls the break-make of described 3rd load.
To the detection of the control voltage of voltage controlled oscillator, the present invention can choose that the operating frequency of phase-locked loop circuit is interval by adaptation control circuit automatically can the bandwidth of Automatic Optimal phase-locked loop circuit.The size that the first detection signal exported by adaptation control circuit and the second detection signal can control the load of the delay cell of the current source of charge pump, the parameter of low pass filter and voltage controlled oscillator respectively carrys out the bandwidth in selected operating frequency interval of phase-locked loop circuit described in Automatic Optimal.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structured flowchart of existing phase-locked loop;
Fig. 2 is the oscillogram of each signal of existing phase-locked loop;
Fig. 3 is the structured flowchart of embodiment of the present invention self-adapting changeable bandwidth phase-locked loop;
Fig. 4 is the structured flowchart of the phase-locked loop circuit of the embodiment of the present invention;
Fig. 5 is the structure chart of the phase frequency detector of the phase-locked loop circuit of the embodiment of the present invention;
Fig. 6 is the structure chart of the charge pump of the phase-locked loop circuit of the embodiment of the present invention;
Fig. 7 is the structure chart of the low pass filter of the phase-locked loop circuit of the embodiment of the present invention;
Fig. 8 is the structure chart of the voltage controlled oscillator of the phase-locked loop circuit of the embodiment of the present invention;
Fig. 9 is the delay cell structure chart of the voltage controlled oscillator of the phase-locked loop circuit of the embodiment of the present invention;
Figure 10 is the structure chart of the adaptation control circuit of the phase-locked loop circuit of the embodiment of the present invention;
Figure 11 is the structure chart of the threshold voltage generation circuit of the phase-locked loop circuit of the embodiment of the present invention.
Embodiment
As shown in Figure 3, be the structured flowchart of embodiment of the present invention self-adapting changeable bandwidth phase-locked loop.Embodiment of the present invention self-adapting changeable bandwidth phase-locked loop: comprise phase-locked loop circuit 11, adaptation control circuit 12, threshold voltage generation circuit 13.
As shown in Figure 4, the described phase-locked loop circuit 11 of the embodiment of the present invention comprises phase frequency detector 111, charge pump 112, low pass filter 114 and voltage controlled oscillator 113.Also comprise a lock detector 115.
As shown in Figure 5, it is the structural representation of the described phase frequency detector 111 of the embodiment of the present invention, described phase frequency detector 111 receives the fractional frequency signal FB of input frequency signal FIN and output frequency signal CK_VCP, compares frequency difference or the difference rear output rising control signal UP and decline control signal DOWN of input frequency signal FIN and fractional frequency signal FB.Described rising control signal UP is activated by the rising edge of described input frequency signal FIN, and decline control signal DOWN is activated by the rising edge of described fractional frequency signal FB.The overlapping internal latency by described phase frequency detector of described rising control signal UP and described decline control signal DOWN determines.Described rising control signal UP and described decline control signal DOWN is input in described charge pump 112, is also input in described lock detector 115 simultaneously, and after described phase-locked loop circuit locking, described lock detector 115 can export a locking signal LOCK.
As shown in figure 11, be the structure chart of the described threshold voltage generation circuit 13 of the embodiment of the present invention.Described threshold voltage generation circuit 13 is for providing two threshold voltage signal VHI and VLO to described adaptation control circuit 12, and wherein first threshold voltage signal VHI is greater than Second Threshold voltage signal VLO.Described threshold voltage generation circuit 13 also produces a control voltage pre-signal VCTRL_PRST.
As shown in Figure 10, for the structure chart of adaptation control circuit described in the embodiment of the present invention 12, described adaptation control circuit 12 is for detecting the control voltage VCTRL of described voltage controlled oscillator 113, described adaptation control circuit 12 compares described control voltage VCTRL and described first threshold voltage signal VHI and exports the first detection signal GEAR1, and described adaptation control circuit 12 compares described control voltage VCTRL and described Second Threshold voltage signal VLO and exports the second detection signal GEAR2.Above-mentioned two comparison circuits all comprise a comparator and a d type flip flop, and the clock signal of two d type flip flops is all formed after the frequency division of the second frequency divider by described input frequency signal FIN.Described locking signal LOCK is also input in described adaptation control circuit 12.In addition, be also provided with signal RESET and PDB, wherein signal RESET can carry out reset operation to testing circuit separately, and signal PDB is the work that can turn off separately this testing circuit.Described first detection signal GEAR1 and described second detection signal GEAR2 to be input in described phase-locked loop circuit 11 and automatically to choose the bandwidth of phase-locked loop circuit 11 described in the operating frequency interval of described phase-locked loop circuit 11 and Automatic Optimal.
Fig. 6 is the structure chart of the charge pump 112 of the phase-locked loop circuit 11 of the embodiment of the present invention.The current source of described charge pump 112 comprises charging current source and discharging current source; The output of described charge pump 112 is received on described low pass filter 114, and the current source of described charge pump 112 carries out discharge and recharge to described low pass filter 114 and exports described control voltage VCTRL; Described first detection signal GEAR1 and described second detection signal GEAR2 to be input in described charge pump 112 and automatically to choose the described charging current source of described charge pump 112 and the size in described discharging current source, by choosing the bandwidth of phase-locked loop circuit 11 described in the described charging current source of different size and described discharging current source Automatic Optimal.
Described charging current source is a multipath current-source, comprise the first reference current 121, first via output current 122, second road output current 123 and the 3rd road output current 124, output in described low pass filter 114 after described first via output current 122, described second road output current 123 and described 3rd road output current 124 merge.Described second road output current 123 is connected in series the first PMOS Mp1, and described first PMOS Mp1 grid meets the inversion signal GB1 of described first detection signal GEAR1, is controlled the break-make of described second road output current 123 by described first detection signal GEAR1.Described 3rd road output current 124 is connected in series the second PMOS Mp2, and described second PMOS Mp2 grid meets the inversion signal GB2 of described second detection signal GEAR2, is controlled the break-make of described 3rd road output current 124 by described second detection signal GEAR2.Described first reference current 121 is the image current of current source IB.
Described discharging current source is a multipath current-source, comprise the 4th road output current 125, the 5th road output current 126 and the 6th road output current 127, output in described low pass filter 114 after described 4th road output current 125, described 5th road output current 126 and described 6th road output current 127 merge.Described 5th road output current 126 is connected in series the first NMOS tube M1, and described first NMOS tube M1 grid meets described first detection signal GEAR1, is controlled the break-make of described 5th road output current 126 by described first detection signal GEAR1; Described 6th road output current 127 is connected in series the second NMOS tube M2, and described second NMOS tube M2 grid meets described second detection signal GEAR2, is controlled the break-make of described 6th road output current 127 by described second detection signal GEAR2.Described 4th road output current 125, the 5th road output current 126 and the 6th road output current 127 are all the image current of described current source IB.
Described charge pump 112 is also provided with four switches, switch between described charging current source and described discharging current source to control described charge pump 112, described four switches control by the inversion signal UB of described rising control signal UP, described decline control signal DOWN, described rising control signal UP and the inversion signal DB of described decline control signal DOWN respectively.The amplifier that a multiplication factor is 1 is also connected with at the output of described charge pump 112.
As shown in Figure 7, be the structure chart of low pass filter 114 of phase-locked loop circuit 11 of the embodiment of the present invention.
Described low pass filter 114 comprises and is series at resistance between described control voltage VCTRL and ground and the first electric capacity Cp, and described resistance is connected with described control voltage VCTRL, described first electric capacity Cp is connected with ground; Described first detection signal GEAR1 and described second detection signal GEAR2 is input to the parameter also automatically choosing described low pass filter 114 in described low pass filter 114.Described low pass filter 114 also comprises the second electric capacity C2, and described second electric capacity C2 is connected between described control voltage VCTRL and ground, and described resistance and the described first electric capacity Cp of described second electric capacity C2 and series connection form parallel-connection structure.The parameter of low pass filter 114 described in the embodiment of the present invention is the size of described resistance, certainly also by other set-up mode choose the size of the first electric capacity Cp or described second electric capacity C2.By the bandwidth of phase-locked loop circuit 11 described in the parameter automatic optimization of choosing the described low pass filter 114 of different size.
Described resistance is connected in series by the first resistance Rp1, the second resistance Rp2 and the 3rd resistance Rp3 and forms; Two ends first switch in parallel of described second resistance Rp2, described first switch is controlled by described first detection signal GEAR1, and described in when described first switch cuts out, the second resistance Rp2 is shorted; The two ends second switch in parallel of described 3rd resistance Rp3, described second switch is controlled by described second detection signal GEAR2, and described in when described second switch is closed, the 3rd resistance Rp3 is shorted.So just can choose the size of described resistance eventually through described first detection signal GEAR1 and described second detection signal GEAR2, thus optimize the bandwidth of described phase-locked loop circuit 11.
Described low pass filter 114 also comprises NMOS tube Mn1 and NMOS tube Mn2.The grid of described NMOS tube Mn1 and described NMOS tube Mn2 all meets described control voltage pre-signal VCTRL_PRST.
As shown in Figure 8, be the structure chart of voltage controlled oscillator 113 of phase-locked loop circuit 11 of the embodiment of the present invention.The delay cell 1131 that described voltage controlled oscillator 113 is serially connected by multiple annular forms.Described delay cell 1131 comprises positive input terminal INP, negative input end INN, negative output terminal OUTN and positive output end OUTP.The negative output terminal OUTN of each described delay cell 1131 is connected with negative input end INN with the positive input terminal INP of adjacent described delay cell 1131 respectively with positive output end OUTP, finally forms a loop configuration.Described control voltage VCTRL, described first detection signal GEAR1 and described second detection signal GEAR2 are input in each described delay cell 1131, described first detection signal GEAR1 and described second detection signal GEAR2 chooses the size of the load of each described delay cell 1131 automatically, by the bandwidth of phase-locked loop circuit 11 described in the load Automatic Optimal of choosing each described delay cell 1131 of different size.
As shown in Figure 9, be the delay cell structure chart of voltage controlled oscillator of phase-locked loop circuit of the embodiment of the present invention.
Each described delay cell 1131 comprises the first gain circuitry, the second gain circuitry, the first current source, the second current source and load.
Described first gain circuitry is made up of a PMOS and a NMOS tube, and the input of described first gain circuitry is positive input terminal INP, output is negative output terminal OUTN.
Described second gain circuitry is made up of a PMOS and a NMOS tube, and the input of described second gain circuitry is negative input end INN, input is negative output terminal OUTN.
Described first gain circuitry forms differential amplifier circuit together with being coupled in described second gain circuitry.Described first current source and described second current source respectively lotus root are connected on described first gain circuitry and described second gain circuitry, and the size of current of described first current source and described second current source is all controlled by described control voltage VCTRL.
The load of each described delay cell 1131 comprises the first load 113A, the second load 113B in parallel and the 3rd load 113C.
Described first load 113A comprises the 3rd NMOS tube M3 and the 4th NMOS tube M4, source electrode all ground connection of described 3rd NMOS tube M3 and described 4th NMOS tube M4, the grid that the drain electrode of described 3rd NMOS tube M3 connects the grid of described 4th NMOS tube M4, the drain electrode of described 4th NMOS tube M4 meets described 3rd NMOS tube M3; The drain electrode of described 3rd NMOS tube M3 meets the negative output terminal OUTN of described delay cell 1131, the drain electrode of described 4th NMOS tube M4 meets the positive output end OUTP of described delay cell 1131.
Described second load 113B comprises the 5th NMOS tube M5 and the 6th NMOS tube M6, source electrode all ground connection of described 5th NMOS tube M5 and described 6th NMOS tube M6, the grid that the drain electrode of described 5th NMOS tube M5 connects the grid of described 6th NMOS tube M6, the drain electrode of described 6th NMOS tube M6 meets described 5th NMOS tube M5; The drain electrode of described 5th NMOS tube M5 connects the source electrode of the 7th NMOS tube M7, the drain electrode of described 7th NMOS tube M7 is connected with described negative output terminal OUTN, and the drain electrode of described 6th NMOS tube M6 connects the source electrode of the 8th NMOS tube M8, the drain electrode of described 8th NMOS tube M8 meets described positive output end OUTP; The grid of described 7th NMOS tube M7 and described 8th NMOS tube M8 all meets described first detection signal GEAR1, and described first detection signal GEAR1 controls the break-make of described second load 113B.Source electrode and the source electrode of described 8th NMOS tube M8 of described 7th NMOS tube M7 are also connected the grid of a NMOS tube respectively, and the source and drain of this NMOS tube all ground connection forms an electric capacity.
Described 3rd load 113C comprises the 9th NMOS tube M9 and the tenth NMOS tube M10, source electrode all ground connection of described 9th NMOS tube M9 and described tenth NMOS tube M10, the grid that the drain electrode of described 9th NMOS tube M9 connects the grid of described tenth NMOS tube M10, the drain electrode of described tenth NMOS tube M10 meets described 9th NMOS tube M9; The drain electrode of described 9th NMOS tube M9 connects the source electrode of the 11 NMOS tube M11, the drain electrode of described 11 NMOS tube M11 is connected with described negative output terminal OUTN, described tenth NMOS tube M10 drain electrode connects the source electrode of the 12 NMOS tube M12, the drain electrode of described 12 NMOS tube M12 meets described positive output end OUTP; The grid of described 11 NMOS tube M11 and described 12 NMOS tube M12 all meets described second detection signal GEAR2, and described second detection signal GEAR2 controls the break-make of described 3rd load 113C.Described 11 NMOS tube M11 and the source electrode of described 12 NMOS tube M12 are also connected the grid of a NMOS tube respectively, and the source and drain of this NMOS tube all ground connection forms an electric capacity.
The break-make of the break-make and the described 3rd load 113C of described second detection signal GEAR2 control that control described second load 113B by described first detection signal GEAR1 can regulate the size of the load of each described delay cell 1131, thus the bandwidth in selected operating frequency interval of phase-locked loop circuit 11 described in energy Automatic Optimal.
Described in embodiment of the present invention Automatic Optimal, the principle of the bandwidth of phase-locked loop circuit 11 is as follows:
One, when described low pass filter 114 does not comprise the second electric capacity C2, described low pass filter 114 is Jie's system, and its transfer function is:
Z ( s ) = Rp + 1 sCp - - - ( 1 )
The open-loop transfer function of described phase-locked loop circuit 11 is:
H o ( s ) = IpKvco 2 πCp 1 + sRpCp s - - - ( 2 )
Wherein: for the gain of described phase frequency detector 111, Ip is the size of current of the current source of described charge pump 112, can be regulated the size of Ip, therefore also can regulate described open-loop transfer function by described first detection signal GEAR1 and described second detection signal GEAR2.Because the bandwidth of described phase-locked loop circuit 11 is determined by described open-loop transfer function, therefore described first detection signal GEAR1 and described second detection signal GEAR2 can realize the optimization of the bandwidth of described phase-locked loop circuit 11.
Kvco is the gain of described voltage controlled oscillator 113, the size of Kvco can be realized by the size of the load regulating each described delay cell 1131, and the break-make of break-make and the described 3rd load 113C of described second detection signal GEAR2 control that the embodiment of the present invention controls described second load 113B by described first detection signal GEAR1 can regulate the size of the load of each described delay cell 1131.Therefore last, described first detection signal GEAR1 and described second detection signal GEAR2 can realize the optimization of the bandwidth of described phase-locked loop circuit 11.
In above-mentioned formula, Rp is the size of described resistance, and Cp is the size of described first electric capacity Cp.The value of Z (s) can realize by regulating the parameter of Rp and Cp.Described first detection signal GEAR1 and described second detection signal GEAR2 can the size of regulating resistance Rp in embodiments of the present invention, thus can realize the optimization of the bandwidth of described phase-locked loop circuit 11.
In order to make described phase-locked loop circuit 11 energy steady operation and bandwidth optimization, the phase shift of loop when gain is 0dB of described voltage controlled oscillator 113 must be made to be less than 180 degree.In the described low pass filter 114 of Jie's system, a resistance Rp that the first electric capacity Cp connects can introduce a zero point, realizes phase lead compensation, realizes the requirement of described phase-locked loop circuit 11 energy steady operation and bandwidth optimization.
On the first electric capacity Cp after series resistance Rp, loop stably may be worked, but bring another one problem simultaneously.Have rising control signal UP signal to come, when described charge pump 112 charges to the resistance Rp of the series connection of described low pass filter 114 and the first electric capacity Cp, due to the existence of resistance Rp, described control voltage VCTRL can produce a upwards saltus step at every turn; During charging complete, control voltage VCTRL again can saltus step equally downwards, and therefore control voltage VCTRL will constantly fluctuate.Even if under the situation of locking, due to the reason such as mismatch of charging and discharging currents, control voltage VCTRL also can be made to fluctuate.The shake that phase-locked loop circuit 11 will be made like this to export increases.The resistance Rp of series connection, the first electric capacity Cp fluctuation of the second electric capacity C2 energy inhibitory control voltage VCTRL in parallel is given in described low pass filter 114.
Two, when described low pass filter 114 is parallel with described second electric capacity C2, described low pass filter 114 is two Jie's systems, and its transfer function is:
Z ( s ) = ( Rp + 1 sCp ) | | 1 SC 2 = 1 + sRpCp s ( C 2 + Cp + sRp C 2 Cp ) - - - ( 2 )
If T 1 = Rp C 2 Cp C 2 + Cp , T 2＝RpCp； ω z = T 2 - 1 , ω p = T 1 - 1 = ω z ( 1 + Cp C 2 ) , Formula (3) just can be rewritten as:
Z ( s ) = 1 Cp + C 2 s T 2 + 1 s ( s T 1 + 1 ) = 1 Cp + C 2 s ω z + 1 s ( s ω p + 1 ) - - - ( 4 )
The open-loop transfer function of described phase-locked loop circuit 11 can be tried to achieve again:
H o ( s ) = Ip 2 π Kvco Cp + C 2 s ω z + 1 s 2 ( s ω p + 1 ) - - - ( 5 )
Make the loop energy steady operation of described voltage controlled oscillator 113, the phase margin of the open-loop transfer function of loop must be made to be greater than certain value, the baud schematic diagram analyzing described low pass filter and loop is known, if Wp is too close to Wz, phase margin very littlely will be difficult to steady operation, and generally getting C2 is that about 1/10th of Cp makes limit away from zero point.From frequency-domain analysis, due to adding of the second electric capacity C2, make described low pass filter add a limit, obviously it more effectively can suppress the noise of high frequency.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (8)

1. a self-adapting changeable bandwidth phase-locked loop, is characterized in that: comprise a phase-locked loop circuit, an adaptation control circuit, a threshold voltage generation circuit;
Described phase-locked loop circuit comprises phase frequency detector, charge pump, low pass filter and voltage controlled oscillator;
Described threshold voltage generation circuit is used for providing two threshold voltage signals to described adaptation control circuit, and wherein first threshold voltage signal is greater than Second Threshold voltage signal;
Described adaptation control circuit is used for detecting the control voltage of described voltage controlled oscillator, described adaptation control circuit compares described control voltage and described first threshold voltage signal and exports the first detection signal, and described adaptation control circuit compares described control voltage and described Second Threshold voltage signal and exports the second detection signal;
Described first detection signal and described second detection signal are input to charge pump, voltage controlled oscillator and low pass filter three modules in described phase-locked loop circuit, and automatically select the parameter of described charge pump, described voltage controlled oscillator and described low pass filter, make the bandwidth Automatic Optimal of described phase-locked loop circuit.
2. self-adapting changeable bandwidth phase-locked loop as claimed in claim 1, is characterized in that: the current source of described charge pump comprises charging current source and discharging current source; Described electric charge delivery side of pump is received on described low pass filter, and the current source of described charge pump carries out discharge and recharge to described low pass filter and exports described control voltage; Described first detection signal and described second detection signal to be input in described charge pump and automatically to choose the described charging current source of described charge pump and the size in described discharging current source, by choosing the bandwidth of phase-locked loop circuit described in the described charging current source of different size and described discharging current source Automatic Optimal.
3. self-adapting changeable bandwidth phase-locked loop as claimed in claim 2, it is characterized in that: described charging current source is a multipath current-source, comprise the first reference current, first via output current, the second road output current and the 3rd road output current, output in described low pass filter after described first via output current, described second road output current and described 3rd road output current merge; Described second road output current is connected in series the first PMOS, and described first PMOS grid connects the inversion signal of described first detection signal, is controlled the break-make of described second road output current by described first detection signal; Described 3rd road output current is connected in series the second PMOS, and described second PMOS grid connects the inversion signal of described second detection signal, is controlled the break-make of described 3rd road output current by described second detection signal;
Described discharging current source is a multipath current-source, comprise the 4th road output current, the 5th road output current and the 6th road output current, output in described low pass filter after described 4th road output current, described 5th road output current and described 6th road output current merge; Described 5th road output current is connected in series the first NMOS tube, and described first NMOS tube grid connects described first detection signal, is controlled the break-make of described 5th road output current by described first detection signal; Described 6th road output current is connected in series the second NMOS tube, and described second NMOS tube grid connects described second detection signal, is controlled the break-make of described 6th road output current by described second detection signal.
4. self-adapting changeable bandwidth phase-locked loop as claimed in claim 1, it is characterized in that: described low pass filter comprises and is series at resistance between described control voltage and ground and the first electric capacity, and described resistance is connected with described control voltage, described first electric capacity is connected with ground; Described first detection signal and described second detection signal to be input in described low pass filter and automatically to choose the parameter of described low pass filter, the parameter of described low pass filter comprise the size of described resistance, the size of the first electric capacity; By the bandwidth of phase-locked loop circuit described in the parameter automatic optimization of choosing the described low pass filter of different size.
5. self-adapting changeable bandwidth phase-locked loop as claimed in claim 4, it is characterized in that: described low pass filter also comprises the second electric capacity, described second electric capacity is connected between described control voltage and ground, described resistance and described first electric capacity of described second electric capacity and series connection form parallel-connection structure, and the parameter of described low pass filter also comprises the size of described second electric capacity.
6. the self-adapting changeable bandwidth phase-locked loop as described in claim 4 or 5, is characterized in that: described resistance is connected in series by the first resistance, the second resistance and the 3rd resistance and forms; Two ends first switch in parallel of described second resistance, described first switch is controlled by described first detection signal, and described in when described first switch cuts out, the second resistance is shorted; The two ends second switch in parallel of described 3rd resistance, described second switch is controlled by described second detection signal, and described in when described second switch is closed, the 3rd resistance is shorted.
7. self-adapting changeable bandwidth phase-locked loop as claimed in claim 1, it is characterized in that: the ring retard that described voltage controlled oscillator is connected to form by multiple delay cell forms, described first detection signal and described second detection signal to be input in each described delay cell and automatically to choose the size of the load of each described delay cell, by the bandwidth of phase-locked loop circuit described in the load Automatic Optimal of choosing each described delay cell of different size.
8. self-adapting changeable bandwidth phase-locked loop as claimed in claim 7, is characterized in that: the load of each described delay cell comprises the first load in parallel, the second load and the 3rd load;
Described first load comprises the 3rd NMOS tube and the 4th NMOS tube, source electrode all ground connection of described 3rd NMOS tube and described 4th NMOS tube, the grid that the drain electrode of described 3rd NMOS tube connects the grid of described 4th NMOS tube, the drain electrode of described 4th NMOS tube connects described 3rd NMOS tube; The drain electrode of described 3rd NMOS tube connects the negative output terminal of described delay cell, the drain electrode of described 4th NMOS tube connects the positive output end of described delay cell;
Described second load comprises the 5th NMOS tube and the 6th NMOS tube, source electrode all ground connection of described 5th NMOS tube and described 6th NMOS tube, the grid that the drain electrode of described 5th NMOS tube connects the grid of described 6th NMOS tube, the drain electrode of described 6th NMOS tube connects described 5th NMOS tube; The drain electrode of described 5th NMOS tube connects the source electrode of the 7th NMOS tube, the drain electrode of described 7th NMOS tube is connected with described negative output terminal, and the drain electrode of described 6th NMOS tube connects the source electrode of the 8th NMOS tube, the drain electrode of described 8th NMOS tube connects described positive output end; The grid of described 7th NMOS tube and described 8th NMOS tube all connects described first detection signal, and described first detection signal controls the break-make of described second load;
Described 3rd load comprises the 9th NMOS tube and the tenth NMOS tube, source electrode all ground connection of described 9th NMOS tube and described tenth NMOS tube, the grid that the drain electrode of described 9th NMOS tube connects the grid of described tenth NMOS tube, the drain electrode of described tenth NMOS tube connects described 9th NMOS tube; The drain electrode of described 9th NMOS tube connects the source electrode of the 11 NMOS tube, the drain electrode of described 11 NMOS tube is connected with described negative output terminal, described tenth NMOS tube drain electrode connects the source electrode of the 12 NMOS tube, the drain electrode of described 12 NMOS tube connects described positive output end; The grid of described 11 NMOS tube and described 12 NMOS tube all connects described second detection signal, and described second detection signal controls the break-make of described 3rd load.
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CN108075773B (en) * 2016-11-14 2021-04-02 中芯国际集成电路制造(上海)有限公司 Starting circuit for phase-locked loop and phase-locked loop
CN109639272B (en) * 2018-12-14 2023-06-09 北京时代民芯科技有限公司 Self-adaptive broadband phase-locked loop circuit
CN111917412B (en) * 2020-08-17 2022-06-03 成都华微电子科技股份有限公司 Programmable charge pump circuit for bandwidth adjustable phase locked loop

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095288A (en) * 1989-11-13 1992-03-10 Telefonaktiebolaget L M Ericsson Phase-locked loop having a variable bandwidth
KR20050007821A (en) * 2003-07-11 2005-01-21 삼성탈레스 주식회사 Phase locked loop circuit having adaptive variable bandwidth
CN101030781A (en) * 2006-01-17 2007-09-05 三星电子株式会社 Sigma-delta fractional-n phase locked loop for reducing lock time and frequency error
CN101204012A (en) * 2005-06-21 2008-06-18 Nxp股份有限公司 Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops
CN101588177A (en) * 2009-06-22 2009-11-25 中国科学院微电子研究所 Digital locking indicator, phase-locked loop frequency synthesizer and wireless transceiver
CN201444630U (en) * 2009-07-29 2010-04-28 浪潮电子信息产业股份有限公司 Phase-locked loop circuit with adjustable frequency range
CN101807920A (en) * 2010-03-10 2010-08-18 东南大学 Self-adaptive frequency calibration frequency synthesizer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080095269A1 (en) * 2006-10-24 2008-04-24 Emmanouil Frantzeskakis Method and System for Digital Tracking in Direct and Polar Modulation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095288A (en) * 1989-11-13 1992-03-10 Telefonaktiebolaget L M Ericsson Phase-locked loop having a variable bandwidth
KR20050007821A (en) * 2003-07-11 2005-01-21 삼성탈레스 주식회사 Phase locked loop circuit having adaptive variable bandwidth
CN101204012A (en) * 2005-06-21 2008-06-18 Nxp股份有限公司 Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops
CN101030781A (en) * 2006-01-17 2007-09-05 三星电子株式会社 Sigma-delta fractional-n phase locked loop for reducing lock time and frequency error
CN101588177A (en) * 2009-06-22 2009-11-25 中国科学院微电子研究所 Digital locking indicator, phase-locked loop frequency synthesizer and wireless transceiver
CN201444630U (en) * 2009-07-29 2010-04-28 浪潮电子信息产业股份有限公司 Phase-locked loop circuit with adjustable frequency range
CN101807920A (en) * 2010-03-10 2010-08-18 东南大学 Self-adaptive frequency calibration frequency synthesizer

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