CN111917412B - Programmable charge pump circuit for bandwidth adjustable phase locked loop - Google Patents
Programmable charge pump circuit for bandwidth adjustable phase locked loop Download PDFInfo
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- CN111917412B CN111917412B CN202010826340.5A CN202010826340A CN111917412B CN 111917412 B CN111917412 B CN 111917412B CN 202010826340 A CN202010826340 A CN 202010826340A CN 111917412 B CN111917412 B CN 111917412B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Abstract
The invention relates to a programmable charge pump circuit for a bandwidth-adjustable phase-locked loop, which relates to an integrated circuit and comprises a low-pass filter, a charge pump core circuit, a charge pump biasing circuit, a control circuit and a pull-UP and pull-down circuit, wherein the control circuit is provided with an UP signal input end, a DN signal input end and a control signal output end, the charge pump biasing circuit outputs bias voltages Vbp and Vbn to the charge pump core circuit and also outputs a pull-UP control voltage Vbc to the pull-UP and pull-down circuit, a Vctrl signal end of the charge pump core circuit outputs a first control signal to the pull-UP and pull-down circuit through the low-pass filter, and the first control signal becomes a second control signal output to the charge pump biasing circuit through a resistor. The invention can effectively inhibit the nonideal effects of charge sharing, clock feed-through and the like and enhance the current matching property.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
With the development of the FPGA technology, higher requirements are put on clock signals. The phase-locked loop circuit is used as a core circuit of a clock management module (CMT) and has higher and higher requirements on the performance, and the charge pump circuit is used as an important component module of the phase-locked loop, so that the performance of the phase-locked loop is directly influenced, and further the performance characteristics of a system are influenced.
Fig. 1 shows a conventional charge pump circuit, which is composed of a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, and a low pass filter LPF. The PMOS transistor M1 and the NMOS transistor M4 are respectively used as a charging current source and a discharging current source, the PMOS transistor M2 and the NMOS transistor M3 are respectively used as a charging switch tube and a discharging switch tube, and the low-pass filter converts a current signal into a voltage signal and provides the voltage signal to a post-stage circuit. When the PMOS tube M2 is turned on and the NMOS tube M3 is turned off, the charge pump circuit is charged through the low-pass filter; when the PMOS tube M2 is turned off and the NMOS tube M3 is turned on, the charge pump circuit discharges electricity through the low-pass filter; when the PMOS transistor M2 and the NMOS transistor M3 are both turned off, the output voltage of the low pass filter remains unchanged. The charge pump circuit with the structure has many non-ideal effects, such as a charge sharing effect, a clock feed-through effect and the like, which can cause current mismatch of the charge pump circuit, so that the input noise of a later stage circuit is increased, and the circuit performance is affected.
Disclosure of Invention
The invention aims to solve the technical problem of providing a programmable charge pump circuit with good matching performance for a bandwidth-adjustable phase-locked loop.
The invention adopts the technical scheme that the programmable charge pump circuit for the bandwidth-adjustable phase-locked loop is characterized by comprising a low-pass filter, a charge pump core circuit (201), a charge pump bias circuit (202), a control circuit (203) and a pull-up and pull-down circuit (204),
the control circuit (203) has an UP signal input terminal and a DN signal input terminal, and a control signal output terminal for outputting a control signal to the charge pump core circuit (201),
the charge pump bias circuit (202) outputs bias voltages Vbp and Vbn to the charge pump core circuit (201) and also outputs a pull-up control voltage Vbc to the pull-up and pull-down circuit (204),
the Vctrl signal terminal of the charge pump core circuit (201) outputs a first control signal Vctrl1 to the pull-down circuit (204) through the low-pass filter, and the first control signal Vctrl1 becomes a second control signal Vctrl2 to the charge pump bias circuit (202) through a resistor R.
The control circuit (203) comprises:
UP signal input ends connected to the 4 UP signal switches, wherein the output of each UP signal switch is divided into two paths, one path is directly output, the other path is output through a phase inverter to form 8 paths of UP signal output ends which are respectively a first path of UP signal end (UP1), a second path of UP signal end (UP2), a third path of UP signal end (UP3),
-the fourth path of UP signal terminal (UP4) and the first path of UP inverted signal terminal (UP1), the second path of UP inverted signal-in-U-UP signal terminal UP signal and UP signal terminal (UP signal and UP (UP, and UP, UP, and UP, inverted, and UP, and UP, UP
A terminal (UP2), a third UP inverse signal terminal (UP3), and a fourth UP inverse signal terminal (UP 4);
the DN signal input end is connected to the 4 DN signal switches, the output of each DN signal switch is divided into two paths, one path is directly output, and the other path is output through the phase inverter; form 8 paths of DN output ends which are respectively a first path of DN signal end (DN1), a second path of DN signal end (DN2), a third path of DN signal end (DN3),
- (fourth path DN signal end (DN4) and first path DN inverse signal end (DN1), second path DN inverse believe- (Y) - (Y-H) -C-H-C-H-C-H-
A number terminal (DN2), a third DN inverting signal terminal (DN3), and a fourth DN inverting signal terminal (DN 4);
the switch control signal generator comprises a switch control signal input end and 8 switch control signal output ends, wherein each switch control signal output end is connected to the control end of one signal switch, and each signal switch comprises an UP signal switch and a DN signal switch. The switch control signal generator can adopt a decoder with 3-path input-8-path output.
The charge pump core circuit (201) comprises:
a first PMOS transistor (P1) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a first PMOS switching tube (S1);
a second PMOS transistor (P2) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a second PMOS switching tube (S2);
a third PMOS transistor (P3) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a fourth PMOS switching tube (S4);
a fourth PMOS transistor (P4) having its gate connected to V of the charge pump bias circuit (202)bpAn output terminal having a source connected to a power supply VDD and a drain connected to a firstA source electrode of a six PMOS switching tube (S6);
a fifth PMOS transistor (P5) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of an eighth PMOS switching tube (S8);
a first PMOS switch tube (S1) having its gate connected to GND and its drain as VmirrorA signal output terminal connected to V of the charge pump bias circuit (202)mirrorA signal input terminal;
a second PMOS switch tube (S2), the grid of which is connected with the first path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a third PMOS switch tube (S3), the grid of which is connected with the first path UP signal end, the drain of which is connected with the drain of the second PMOS tube (P2), and the source of which is connected with the output end of the unit gain BUFFER BUFFER;
a fourth PMOS switch tube (S4), the grid of which is connected with the second path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a fifth PMOS switch tube (S5), having a gate connected to the second path of UP signal, a drain connected to the drain of the third PMOS tube (P3), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
a sixth PMOS switch (S6), having a gate connected to the third UP inverter signal terminal and a drain connected to the Vctrl signal terminal;
a seventh PMOS switch tube (S7), having a gate connected to the third UP signal terminal, a drain connected to the drain of the fourth PMOS tube (P4), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
an eighth PMOS switch (S8), having a gate connected to the fourth UP inverted signal terminal and a drain connected to the Vctrl signal terminal;
a ninth PMOS switch tube (S9), having a gate connected to the fourth UP signal terminal, a drain connected to the drain of the fifth PMOS tube (P5), and a source connected to the output terminal of the unit gain BUFFER BUFFER;
a first NMOS transistor (N1), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the tenth NMOS switch transistor (S10);
a second NMOS transistor (N2), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the eleventh NMOS switch transistor (S11);
a third NMOS transistor (N3), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the thirteenth NMOS switch transistor (S13);
a fourth NMOS transistor (N4), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the fifteenth NMOS switch transistor (S15);
a fifth NMOS transistor (N5), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the seventeenth NMOS switch transistor (S17);
a tenth NMOS switch tube (S10), its gate is connected to the power VDD, and its drain is connected to V of the charge pump bias circuit (202)mirrorA signal terminal;
an eleventh NMOS switch tube (S11), having a gate connected to the DN signal terminal of the first path and a drain connected to the Vctrl signal terminal;
a twelfth NMOS switch tube (S12), having a gate connected to the first DN inverted signal end, a source connected to the source of the eleventh NMOS tube (N11), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a thirteenth NMOS switch tube (S13), having a gate connected to the DN signal terminal of the second path and a drain connected to the Vctrl signal terminal;
a fourteenth NMOS switch tube (S14), having a gate connected to the second path DN inverted signal end, a source connected to the source of the thirteenth NMOS tube (N13), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a fifteenth NMOS switch (S15), having a gate connected to the DN signal terminal of the third channel and a drain connected to the Vctrl signal terminal;
a sixteenth NMOS switch tube (S16), having a gate connected to the third DN inverse signal terminal, a source connected to the source of the fifteenth NMOS tube (N15), and a drain connected to the output terminal of the unity gain BUFFER BUFFER;
a seventeenth NMOS switch tube (S17), having a gate connected to the fourth DN signal terminal and a drain connected to the Vctrl signal terminal;
an eighteenth NMOS switch tube (S18), the gate of which is connected to the fourth DN inverted signal end, the source of which is connected to the source of the seventeenth NMOS tube (N17), and the drain of which is connected to the output end of the unit gain BUFFER BUFFER;
and the positive input end of the unit gain BUFFER BUFFER is connected with the Vctrl signal end, and the negative input end of the unit gain BUFFER BUFFER is connected with the output end.
The charge pump bias circuit (202) comprises:
the grid electrode of the first starting PMOS tube (MS1) is grounded, the source electrode of the first starting PMOS tube is connected with the power supply VDD, and the drain electrode of the first starting PMOS tube (MS2) is connected with the source electrode of the second starting PMOS tube;
a second starting PMOS tube (MS2), the grid of which is connected with the Vbn signal end, and the drain of which is connected with the drain of the third starting PMOS tube (MS 3);
a third starting NMOS tube (MS3), wherein the grid electrode of the third starting NMOS tube is connected with the Vbn signal end, and the source electrode of the third starting NMOS tube is grounded;
a fourth start-up NMOS transistor (MS4), wherein the grid electrode is connected with the drain electrode of the third start-up NMOS transistor (MS3), the source electrode is grounded, and the drain electrode is connected with a fourth reference point;
the grid electrode of the first current source PMOS tube (MB1) is connected with a fourth reference point, the source electrode of the first current source PMOS tube is connected with the power supply VDD, and the drain electrode of the first current source NMOS tube (MB2) is connected with the drain electrode of the second current source NMOS tube;
a second current source NMOS tube (MB2), wherein the grid electrode and the drain electrode of the second current source NMOS tube are connected with the Vbn signal end, and the source electrode of the second current source NMOS tube is grounded;
the grid electrode and the drain electrode of the third current source PMOS tube (MB3) are connected with the drain electrode of the fourth current source NMOS tube (MB4), and the source electrode of the third current source PMOS tube is connected with the power supply VDD;
a fourth current source NMOS transistor (MB4), having a gate connected to the first reference point a and a source connected to the source of the sixth current source NMOS transistor (MB 6);
a grid electrode and a drain electrode of the fifth current source PMOS tube (MB5) are connected with a drain electrode and a fourth reference point of the sixth current source NMOS tube (MB6), and a source electrode of the fifth current source PMOS tube is connected with the power supply VDD;
a sixth current source NMOS transistor (MB6), the gate of which is connected to the second reference point B, and the source of which is connected to the drain of the seventh current source NMOS transistor (MB 6);
a seventh current source NMOS tube (MB7), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
an eighth current source PMOS tube (MB8), the grid of which is connected with the fourth reference point, the source of which is connected with the power supply VDD, and the drain of which is connected with the first reference point A;
a ninth current source PMOS tube (MB9), the grid of which is connected with the fourth reference point, the source of which is connected with the power supply VDD, and the drain of which is connected with the second reference point B;
a tenth current source NMOS transistor (MB10), wherein the grid electrode is connected with a fourth reference point, the source electrode is connected with a power supply VDD, and the drain electrode is connected with a first reference point A;
an eleventh current source NMOS tube (MB11), wherein the grid electrode is connected with the second reference point, and the source electrode and the drain electrode are grounded;
a twelfth bias PMOS tube (MB12), the source electrode of which is connected with the power supply VDD, and the grid electrode and the drain electrode of which are connected with the drain electrode of the thirteenth bias NMOS tube (MB 13);
a thirteenth bias NMOS transistor (MB13), wherein the source thereof is connected to the drain of the sixteenth bias NMOS transistor (MB16), and the gate thereof is connected to the signal terminal Vctrl 2;
a fourteenth bias PMOS tube (MB14), the source of which is connected with the power supply VDD, the grid of which is connected with the grid of the twelfth bias PMOS tube (MB12), and the drain of which is connected with the drain of the fifteenth bias NMOS tube (MB15) and the Vbp signal end;
a fifteenth bias NMOS (MB15) having a source connected to the source of the fifteenth bias NMOS and a drain connected to the drain of the sixteenth bias NMOS (MB16), and a gate connected to the Vmror signal terminal;
a sixteenth bias NMOS transistor (MB16), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
a seventeenth bias PMOS tube (MB17), the source of which is connected with the power VDD, the grid of which is connected with the Vbp signal end, and the drain of which is connected with the drain of the nineteenth bias NMOS tube (MB 19);
the source and the drain of the eighteenth bias PMOS tube (MB18) are connected with the drain of the nineteenth bias NMOS tube (MB19), and the gate of the eighteenth bias PMOS tube is connected with the Vbp signal end;
a nineteenth bias NMOS transistor (MB19), the grid of which is connected with the Vbn signal end, and the source of which is grounded;
a twentieth bias PMOS tube (MB20), the grid electrode of which is connected with the Vbn signal end, the source electrode of which is connected with the power supply VDD, and the drain electrode of which is connected with the Vbc signal end;
the twenty-first bias NMOS transistor (MB21) has a drain connected to the Vbc signal terminal, a gate connected to the Vbp signal terminal, and a source connected to ground.
The invention can effectively inhibit the nonideal effects of charge sharing, clock feed-through and the like, enhance the current matching property, and simultaneously enable the current of the charge pump circuit to be adjustable, thereby adjusting the bandwidth of the phase-locked loop circuit where the charge pump circuit is located; in addition, the control voltage output by the charge pump is kept in a proper range through the pull-up and pull-down circuit, and the phase-locked loop can be locked more quickly.
Drawings
Fig. 1 is a schematic diagram of the prior art.
Fig. 2 is a schematic structural diagram of the present invention.
Fig. 3 is a circuit diagram of the control circuit of the present invention.
Fig. 4 is a circuit diagram of the bias circuit of the present invention.
Fig. 5 is a current matching curve for the charge pump circuit of the present invention.
Detailed Description
For convenience of reading with reference to the figures, in the embodiments, a shorthand way of example is to invert the third DN signal to the signal terminal
Is abbreviated as
The first PMOS transistor P1 is abbreviated as PMOS transistor P1, for the same reason.
As shown in fig. 2, the present invention includes a charge pump core circuit 201, a charge pump bias circuit 202, a control circuit 203, and a pull-up and pull-down circuit 204.
The input end of the control circuit 203 is connected with output signals UP and DN of a phase frequency detector of a preceding stage circuit and configuration signals CONF1, CONF2 and CONF3, eight groups of complementary control signals are output after passing through a series of internal inverters
And
to the charge pump core circuitry 201.
Indicating an inversion of UP 4.
The UP signal is output through an inverter and a buffer
Wherein UP 1-UP 4 are in phase with UP,
inverse to UP; DN can be processed in the same way.
Referring to fig. 2 and 3, each of the eight signal paths has a switch, and CONF1, CONF2, and CONF3 are converted into eight-bit control signals by decoding, and the eight switches are respectively controlled to be turned on or off, so as to control whether the four branches in 201 operate normally (P2, S2, S11, and N2 are charge pump first branches, P3, S4, S13, and N3 are charge pump third branches, P4, S6, S15, and N4 are charge pump third branches, and P5, S8, S17, and N5 are charge pump fourth branches).
If the four branches work simultaneously, the actual charging and discharging current of the charge pump is equal to the total current. The fewer the working branches are, the smaller the actual current of the charge pump is, so that the effect of flexibly adjusting the charge and discharge current of the charge pump is achieved.
The pull-UP and pull-down circuit 204 is composed of a comparator circuit COMP, a pull-UP BUFFER circuit BUFFER _ UP, a pull-down BUFFER circuit BUFFER _ DN, a pull-UP PMOS transistor M _ UP and a pull-down NMOS transistor M _ DN. Wherein, the input terminals of the comparator circuit COMP are respectively connected with the output V of the low-pass filterctrl1And an external reference voltage VrefThe output end is connected with the input of the pull-down BUFFER circuit BUFFER _ DN; the input end of the pull-UP BUFFER circuit BUFFER _ UP is connected with the output V of the charge pump bias circuit 202bcThe output end is connected with the grid electrode of the pull-UP PMOS tube M _ UP; the output end of the pull-down BUFFER circuit BUFFER _ DN is connected with the grid electrode of the pull-down NMOS tube M _ DN; the source electrode of the pull-UP PMOS tube M _ UP is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the pull-down NMOS tube M _ DN and connected with the power supply VDDctrl2And the source electrode of the pull-down NMOS tube M _ DN is grounded GND at the output end.
As shown in fig. 3, the charge pump core circuit (201) includes:
a first PMOS transistor (P1) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a first PMOS switching tube (S1);
a second PMOS transistor (P2) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a second PMOS switching tube (S2);
a third PMOS transistor (P3) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a fourth PMOS switching tube (S4);
a fourth PMOS transistor (P4) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a sixth PMOS switching tube (S6);
a fifth PMOS transistor (P5) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of an eighth PMOS switching tube (S8);
a first PMOS switch tube (S1) having its gate connected to GND and its drain as VmirrorA signal output terminal connected to V of the charge pump bias circuit (202)mirrorA signal input terminal;
a second PMOS switch tube (S2), the grid of which is connected with the first path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a third PMOS switch tube (S3), the grid of which is connected with the first path UP signal end, the drain of which is connected with the drain of the second PMOS tube (P2), and the source of which is connected with the output end of the unit gain BUFFER BUFFER;
a fourth PMOS switch tube (S4), the grid of which is connected with the second path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a fifth PMOS switch tube (S5), the grid of which is connected with the second path of UP signal end, the drain of which is connected with the drain of the third PMOS tube (P3), and the source of which is connected with the output end of the unit gain BUFFER BUFFER;
a sixth PMOS switch (S6), having a gate connected to the third UP inverter signal terminal and a drain connected to the Vctrl signal terminal;
a seventh PMOS switch tube (S7), having a gate connected to the third UP signal terminal, a drain connected to the drain of the fourth PMOS tube (P4), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
an eighth PMOS switch (S8), having a gate connected to the fourth UP inverted signal terminal and a drain connected to the Vctrl signal terminal;
a ninth PMOS switch tube (S9), having a gate connected to the fourth UP signal terminal, a drain connected to the drain of the fifth PMOS tube (P5), and a source connected to the output terminal of the unit gain BUFFER BUFFER;
a first NMOS transistor (N1), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the tenth NMOS switch transistor (S10);
a second NMOS transistor (N2), wherein the gate of the second NMOS transistor is connected with the Vbn signal end of the charge pump bias circuit (202), the source of the second NMOS transistor is grounded GND, and the drain of the second NMOS transistor is connected with the source of the eleventh NMOS switch transistor (S11);
a third NMOS transistor (N3), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the thirteenth NMOS switch transistor (S13);
a fourth NMOS transistor (N4), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the fifteenth NMOS switch transistor (S15);
a fifth NMOS transistor (N5), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the seventeenth NMOS switch transistor (S17);
a tenth NMOS switch tube (S10), its gate is connected to the power VDD, and its drain is connected to V of the charge pump bias circuit (202)mirrorA signal terminal;
an eleventh NMOS switch tube (S11), having a gate connected to the DN signal terminal of the first path and a drain connected to the Vctrl signal terminal;
a twelfth NMOS switch tube (S12), having a gate connected to the first DN inverted signal end, a source connected to the source of the eleventh NMOS tube (N11), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a thirteenth NMOS switch tube (S13), having a gate connected to the DN signal terminal of the second path and a drain connected to the Vctrl signal terminal;
a fourteenth NMOS switch tube (S14), having a gate connected to the second path DN inverted signal end, a source connected to the source of the thirteenth NMOS tube (N13), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a fifteenth NMOS switch (S15), having a gate connected to the third DN signal terminal and a drain connected to the Vctrl signal terminal;
a sixteenth NMOS switch tube (S16), having a gate connected to the third DN inverted signal terminal, a source connected to the source of the fifteenth NMOS tube (N15), and a drain connected to the output terminal of the unity gain BUFFER BUFFER;
a seventeenth NMOS switch tube (S17), having a gate connected to the fourth DN signal terminal and a drain connected to the Vctrl signal terminal;
an eighteenth NMOS switch tube (S18), the gate of which is connected to the fourth DN inverted signal end, the source of which is connected to the source of the seventeenth NMOS tube (N17), and the drain of which is connected to the output end of the unit gain BUFFER BUFFER;
and the positive input end of the unit gain BUFFER BUFFER is connected with the Vctrl signal end, and the negative input end of the unit gain BUFFER BUFFER is connected with the output end.
As shown in fig. 4, the charge pump bias circuit 202 is composed of a start-up circuit 401, a self-bias current source 402, and a bias circuit 403. The method specifically comprises the following steps:
the grid electrode of the first starting PMOS tube (MS1) is grounded, the source electrode of the first starting PMOS tube is connected with the power supply VDD, and the drain electrode of the first starting PMOS tube (MS2) is connected with the source electrode of the second starting PMOS tube;
a second starting PMOS tube (MS2), the grid of which is connected with the Vbn signal end, and the drain of which is connected with the drain of the third starting PMOS tube (MS 3);
a third starting NMOS tube (MS3), wherein the grid electrode of the third starting NMOS tube is connected with the Vbn signal end, and the source electrode of the third starting NMOS tube is grounded;
a fourth start-up NMOS transistor (MS4), wherein the grid electrode is connected with the drain electrode of the third start-up NMOS transistor (MS3), the source electrode is grounded, and the drain electrode is connected with a fourth reference point;
the grid electrode of the first current source PMOS tube (MB1) is connected with a fourth reference point, the source electrode of the first current source PMOS tube is connected with the power supply VDD, and the drain electrode of the first current source NMOS tube (MB2) is connected with the drain electrode of the second current source NMOS tube;
a second current source NMOS tube (MB2), wherein the grid and the drain are connected with the Vbn signal end, and the source is grounded;
a grid electrode and a drain electrode of the third current source PMOS tube (MB3) are connected with a drain electrode of the fourth current source NMOS tube (MB4), and a source electrode of the third current source PMOS tube is connected with a power supply VDD;
a fourth current source NMOS transistor (MB4), the gate of which is connected to the first reference point A, and the source of which is connected to the source of the sixth current source NMOS transistor (MB 6);
a grid electrode and a drain electrode of the fifth current source PMOS tube (MB5) are connected with a drain electrode and a fourth reference point of the sixth current source NMOS tube (MB6), and a source electrode of the fifth current source PMOS tube is connected with the power supply VDD;
a sixth current source NMOS transistor (MB6), the gate of which is connected to the second reference point B, and the source of which is connected to the drain of the seventh current source NMOS transistor (MB 6);
a seventh current source NMOS tube (MB7), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
an eighth current source PMOS tube (MB8), the grid of which is connected with the fourth reference point, the source of which is connected with the power supply VDD, and the drain of which is connected with the first reference point A;
a ninth current source PMOS tube (MB9), wherein the grid electrode is connected with a fourth reference point, the source electrode is connected with a power supply VDD, and the drain electrode is connected with a second reference point B;
a tenth current source NMOS transistor (MB10), wherein the grid electrode is connected with a fourth reference point, the source electrode is connected with a power supply VDD, and the drain electrode is connected with a first reference point A;
an eleventh current source NMOS tube (MB11), wherein the grid electrode is connected with the second reference point, and the source electrode and the drain electrode are grounded;
a twelfth bias PMOS tube (MB12), the source electrode of which is connected with the power supply VDD, and the grid electrode and the drain electrode of which are connected with the drain electrode of the thirteenth bias NMOS tube (MB 13);
a thirteenth bias NMOS transistor (MB13), wherein the source thereof is connected to the drain of the sixteenth bias NMOS transistor (MB16), and the gate thereof is connected to the signal terminal Vctrl 2;
a fourteenth bias PMOS tube (MB14), the source of which is connected with the power supply VDD, the grid of which is connected with the grid of the twelfth bias PMOS tube (MB12), and the drain of which is connected with the drain of the fifteenth bias NMOS tube (MB15) and a Vbp signal end;
a fifteenth bias NMOS (MB15) having a source connected to the source of the fifteenth bias NMOS and a drain connected to the drain of the sixteenth bias NMOS (MB16), and a gate connected to the Vmror signal terminal;
a sixteenth bias NMOS transistor (MB16), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
a seventeenth bias PMOS tube (MB17), the source of which is connected with the power VDD, the grid of which is connected with the Vbp signal end, and the drain of which is connected with the drain of the nineteenth bias NMOS tube (MB 19);
the source and the drain of the eighteenth bias PMOS tube (MB18) are connected with the drain of the nineteenth bias NMOS tube (MB19), and the gate of the eighteenth bias PMOS tube is connected with the Vbp signal end;
a nineteenth bias NMOS transistor (MB19), the grid of which is connected with the Vbn signal end, and the source of which is grounded;
a twentieth bias PMOS tube (MB20), the grid electrode of which is connected with the Vbn signal end, the source electrode of which is connected with the power supply VDD, and the drain electrode of which is connected with the Vbc signal end;
the twenty-first bias NMOS transistor (MB21) has a drain connected to the Vbc signal terminal, a gate connected to the Vbp signal terminal, and a source connected to ground.
Referring to fig. 2, the capacitor network (two capacitors C1, C2 and resistor R) constitutes a low pass filter.
The working principle of the invention is as follows:
the charge pump bias circuit 202 provides bias voltages for the P-type current source and the N-type current source of the charge pump core circuit 201. As shown in FIG. 4, for the self-bias current source 402, the gate-source voltages V of the PMOS transistor MB8 and the PMOS transistor MB9GSThe voltages of the node A and the node B are equal due to the clamping action of the operational amplifier (composed of a PMOS tube MB3, an NMOS tube MB4, a PMOS tube MB5, an NMOS tube MB6 and an NMOS tube MB7), so that a branch where the PMOS tube MB8 and the PMOS tube MB9 are located respectively generates an equal current as a reference current, and the current can be changed by adjusting the value of the resistor Rn; the generated reference current is then copied to a later stage circuit for use by a current mirror circuit composed of a PMOS transistor MB1 and an NMOS transistor MB 2. The PMOS tube MB3 and the PMOS tube MB5 are connected in a diode mode, so that the gain of the operational amplifier is low, and the stability of a loop is improved. In addition, a start-up circuit is added because the circuit has degeneracy points. When the power supply is powered on, if VbnAnd when the voltage is lower, the PMOS tube MS2 is conducted, the NMOS tube MS4 is also conducted, so that the PMOS tube MB1, the PMOS tube MB8 and the PMOS tube MB9 are all conducted, and the circuit is driven to get rid of degeneracy points.
V of the Charge Pump core Circuit 201, as shown in FIG. 3ctrlAnd VmirrorBy forming a negative feedback circuit with the bias circuit 403, so that VctrlAnd VmirrorThe voltages are equal, thereby greatly enhancing the current matching of the charge pump. Meanwhile, by changing the values of the configuration signals CONF1, CONF2, and CONF3 of the control circuit 203, it is possible to freely control
And
the four branches of the charge pump are controlled to be opened or closed, so that the charge and discharge current of the charge pump is changed, and the function of adjusting the bandwidth of the whole phase-locked loop is achieved. The PMOS switch tube S3, the PMOS switch tube S5, the PMOS switch tube S7, the PMOS switch tube S9, the NMOS switch tube S12, the NMOS switch tube S14, the NMOS switch tube S16, the NMOS switch tube S18 and the unit gain BUFFER BUFFER eliminate the charge sharing effect in a bootstrap mode. The specific working principle is illustrated by taking a branch where a PMOS tube P2, a PMOS switch tube S2, an NMOS switch tube S11 and an NMOS tube N2 are located as an example: because the grid control signals of the PMOS switch tube S2 and the PMOS switch tube S3 are complementary, the grid control signals of the NMOS switch tube S11 and the NMOS switch tube S12 are complementary; when the PMOS switch tube S2 and the NMOS switch tube S11 are disconnected, the PMOS switch tube S3 and the NMOS switch tube S12 are connected, and the source voltages of the PMOS switch tube S2 and the NMOS switch tube S11 are kept at V through the unit gain BUFFER BUFFERctrlA voltage; when the PMOS switch tube S2 and the NMOS switch tube S11 are turned on and the PMOS switch tube S3 and the NMOS switch tube S12 are turned off, the sources of the PMOS switch tube S2 and the NMOS switch tube S11 are not charged or discharged, so that the charge sharing effect is eliminated.
As shown in fig. 2, the control voltage V is applied when the whole charge pump circuit is not yet operating, i.e. the phase-locked loop is still in the capture phasectrl2At a low potential, a control signal V is generated by the bias circuit 403bcThen, a low level is output through the BUFFER circuit BUFFER _ UP, so that the pull-UP PMOS tube M _ UP is conducted to Vctrl2And charging is carried out, so that the duration of the capturing phase is shortened, and the locking speed of the phase-locked loop is accelerated. It should be noted that when V isctrl2When the voltage is in a low potential in a certain range, the pull-up effect can be triggered. When the control voltage Vctrl1 is too high (higher than the reference voltage V)ref) ComparatorThe circuit COMP outputs a high level, and the pull-down NMOS transistor M _ DN is turned on by the pull-down BUFFER circuit BUFFER _ DN, so that the voltage Vctrl1 is reduced. Through the action of the pull-up and pull-down circuit, the control voltage can be within a proper range, so that the rear-stage voltage-controlled oscillator works within a reasonable range.
According to the invention, the charge-discharge current of the total charge pump can be adjusted through the variable resistor Rn in the self-bias current source 402; by changing the configuration points CONF1, CONF2, and CONF3, the operating states of four branches of the charge pump core circuit 201 are controlled to change the magnitude of the charge and discharge current (not exceeding the total charge and discharge current) of the actual operation of the charge pump, so that the loop bandwidth of the phase-locked loop in which the charge pump is located is adjusted, and the effect of programmable bandwidth is achieved. The charge pump circuit shown in fig. 1 cannot flexibly adjust the charging and discharging current according to the requirement.
The invention keeps the control voltage output by the charge pump in a proper range through the pull-up and pull-down circuit, and enables the phase-locked loop where the charge pump is positioned to be locked more quickly. The charge pump circuit shown in fig. 1 does not have this function.
The charge pump circuit improves the charge-discharge current matching performance. Fig. 5 is a current matching simulation diagram of the charge and discharge current of the charge pump circuit of the present invention. Simulation results show that the current mismatch is less than 0.2 muA when the output voltage is 0.4V-0.8V, and the matching performance is good. However, the charge-discharge current mismatch of the charge pump circuit shown in fig. 1 is generally larger than 3 μ a, which shows that the charge pump circuit of the present invention greatly improves the current matching performance.
Claims (3)
1. Programmable charge pump circuit for a bandwidth adjustable phase locked loop comprising a low pass filter, a charge pump core circuit (201), a charge pump bias circuit (202), a control circuit (203) and a pull-up and pull-down circuit (204),
the control circuit (203) has an UP signal input terminal and a DN signal input terminal, and a control signal output terminal for outputting a control signal to the charge pump core circuit (201),
the charge pump bias circuit (202) outputs bias voltages Vbp and Vbn to the charge pump core circuit (201), and also outputs a pull-up control voltage Vbc to the pull-up/down circuit (204),
a Vctrl signal end of the charge pump core circuit (201) outputs a first control signal Vctrl1 to the pull-down circuit (204) through a low-pass filter, and the first control signal Vctrl1 becomes a second control signal Vctrl2 which is output to the charge pump bias circuit (202) through a resistor R;
the charge pump core circuit (201) comprises:
a first PMOS transistor (P1) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a first PMOS switching tube (S1);
a second PMOS transistor (P2) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a second PMOS switching tube (S2);
a third PMOS transistor (P3) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a fourth PMOS switching tube (S4);
a fourth PMOS transistor (P4) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of a sixth PMOS switching tube (S6);
a fifth PMOS transistor (P5) having its gate connected to V of the charge pump bias circuit (202)bpThe source of the output end is connected with a power supply VDD, and the drain of the output end is connected with the source of an eighth PMOS switching tube (S8);
a first PMOS switch tube (S1) having its gate connected to GND and its drain as VmirrorA signal output terminal connected to V of the charge pump bias circuit (202)mirrorA signal input terminal;
a second PMOS switch tube (S2), the grid of which is connected with the first path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a third PMOS switch tube (S3), having a gate connected to the first UP signal terminal, a drain connected to the drain of the second PMOS tube (P2), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
a fourth PMOS switch tube (S4), the grid of which is connected with the second path of UP inverted signal end, and the drain of which is connected with the Vctrl signal end;
a fifth PMOS switch tube (S5), the grid of which is connected with the second path of UP signal end, the drain of which is connected with the drain of the third PMOS tube (P3), and the source of which is connected with the output end of the unit gain BUFFER BUFFER;
a sixth PMOS switch (S6), having a gate connected to the third UP inverter signal terminal and a drain connected to the Vctrl signal terminal;
a seventh PMOS switch tube (S7), having a gate connected to the third UP signal terminal, a drain connected to the drain of the fourth PMOS tube (P4), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
an eighth PMOS switch (S8), having a gate connected to the fourth UP inverted signal terminal and a drain connected to the Vctrl signal terminal;
a ninth PMOS switch tube (S9) having a gate connected to the fourth UP signal terminal, a drain connected to the drain of the fifth PMOS tube (P5), and a source connected to the output terminal of the unity gain BUFFER BUFFER;
a first NMOS transistor (N1), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the tenth NMOS switch transistor (S10);
a second NMOS transistor (N2), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the eleventh NMOS switch transistor (S11);
a third NMOS transistor (N3), having a gate connected to the Vbn signal terminal of the charge pump bias circuit (202), a source connected to the ground level GND, and a drain connected to the source of the thirteenth NMOS switch transistor (S13);
a fourth NMOS transistor (N4), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the fifteenth NMOS switch transistor (S15);
a fifth NMOS transistor (N5), the gate of which is connected to the Vbn signal terminal of the charge pump bias circuit (202), the source of which is grounded GND, and the drain of which is connected to the source of the seventeenth NMOS switch transistor (S17);
a tenth NMOS switch tube (S10) having its gate connected to the power supplyVDD, whose drain is connected to V of the charge pump bias circuit (202)mirrorA signal terminal;
an eleventh NMOS switch tube (S11), having a gate connected to the DN signal terminal of the first path and a drain connected to the Vctrl signal terminal;
a twelfth NMOS switch tube (S12), having a gate connected to the first DN inverted signal end, a source connected to the source of the eleventh NMOS tube (N11), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a thirteenth NMOS switch tube (S13), having a gate connected to the DN signal terminal of the second path and a drain connected to the Vctrl signal terminal;
a fourteenth NMOS switch tube (S14), having a gate connected to the second path DN inverted signal end, a source connected to the source of the thirteenth NMOS tube (N13), and a drain connected to the output end of the unit gain BUFFER BUFFER;
a fifteenth NMOS switch (S15), having a gate connected to the DN signal terminal of the third channel and a drain connected to the Vctrl signal terminal;
a sixteenth NMOS switch tube (S16), having a gate connected to the third DN inverted signal terminal, a source connected to the source of the fifteenth NMOS tube (N15), and a drain connected to the output terminal of the unity gain BUFFER BUFFER;
a seventeenth NMOS switch tube (S17), having a gate connected to the fourth DN signal terminal and a drain connected to the Vctrl signal terminal;
an eighteenth NMOS switch tube (S18), the gate of which is connected to the fourth DN inverted signal end, the source of which is connected to the source of the seventeenth NMOS tube (N17), and the drain of which is connected to the output end of the unit gain BUFFER BUFFER;
and the positive input end of the unit gain BUFFER BUFFER is connected with the Vctrl signal end, and the negative input end of the unit gain BUFFER BUFFER is connected with the output end.
2. The programmable charge pump circuit for a bandwidth adjustable phase locked loop of claim 1, wherein the control circuit (203) comprises:
UP signal input ends connected to the 4 UP signal switches, wherein the output of each UP signal switch is divided into two paths, one path is directly output, the other path is output through a phase inverter to form 8 paths of UP signal output ends which are respectively a first path of UP signal end (UP1)A second UP signal terminal (UP2), a third UP signal terminal (UP3), a fourth UP signal terminal (UP4) and a first UP inverse signal terminal (UP)
) The second path of UP inverse signal terminal (
) And the third UP inverse signal terminal
) The fourth UP inverse signal terminal (
）；
The DN signal input end is connected to the 4 DN signal switches, the output of each DN signal switch is divided into two paths, one path is directly output, and the other path is output through the phase inverter; form 8 paths of DN output ends which are respectively a first path of DN signal end (DN1), a second path of DN signal end (DN2), a third path of DN signal end (DN3), a fourth path of DN signal end (DN4) and a first path of DN inverted signal end (DN4)
) A second DN inverse signal end (
) And a third DN inverse signal end (
) A fourth DN inverse signal terminal (
）；
The switch control signal generator comprises a switch control signal input end and 8 switch control signal output ends, wherein each switch control signal output end is connected to the control end of one signal switch, and each signal switch comprises an UP signal switch and a DN signal switch.
3. The programmable charge pump circuit for a bandwidth adjustable phase locked loop of claim 1, wherein the charge pump bias circuit (202) comprises:
the grid electrode of the first starting PMOS tube (MS1) is grounded, the source electrode of the first starting PMOS tube is connected with the power supply VDD, and the drain electrode of the first starting PMOS tube is connected with the source electrode of the second starting PMOS tube (MS 2);
a second starting PMOS tube (MS2), the grid of which is connected with the Vbn signal end, and the drain of which is connected with the drain of the third starting PMOS tube (MS 3);
a third start-up NMOS transistor (MS3), wherein the grid electrode of the third start-up NMOS transistor is connected with the Vbn signal end, and the source electrode of the third start-up NMOS transistor is grounded;
a fourth start-up NMOS transistor (MS4), wherein the grid electrode is connected with the drain electrode of the third start-up NMOS transistor (MS3), the source electrode is grounded, and the drain electrode is connected with a fourth reference point;
the grid electrode of the first current source PMOS tube (MB1) is connected with a fourth reference point, the source electrode of the first current source PMOS tube is connected with the power supply VDD, and the drain electrode of the first current source NMOS tube (MB2) is connected with the drain electrode of the second current source NMOS tube;
a second current source NMOS tube (MB2), wherein the grid and the drain are connected with the Vbn signal end, and the source is grounded;
the grid electrode and the drain electrode of the third current source PMOS tube (MB3) are connected with the drain electrode of the fourth current source NMOS tube (MB4), and the source electrode of the third current source PMOS tube is connected with the power supply VDD;
a fourth current source NMOS transistor (MB4), the gate of which is connected to the first reference point A, and the source of which is connected to the source of the sixth current source NMOS transistor (MB 6);
a gate and a drain of the fifth current source PMOS tube (MB5) are connected with the drain and a fourth reference point of the sixth current source NMOS tube (MB6), and a source of the fifth current source PMOS tube is connected with the power supply VDD;
a sixth current source NMOS transistor (MB6), the gate of which is connected to the second reference point B, and the source of which is connected to the drain of the seventh current source NMOS transistor (MB 6);
a seventh current source NMOS tube (MB7), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
an eighth current source PMOS tube (MB8), wherein the grid electrode is connected with the fourth reference point, the source electrode is connected with the power supply VDD, and the drain electrode is connected with the first reference point A;
a ninth current source PMOS tube (MB9), the grid of which is connected with the fourth reference point, the source of which is connected with the power supply VDD, and the drain of which is connected with the second reference point B;
a tenth current source NMOS transistor (MB10), wherein the grid electrode is connected with a fourth reference point, the source electrode is connected with a power supply VDD, and the drain electrode is connected with a first reference point A;
an eleventh current source NMOS tube (MB11), wherein the grid electrode is connected with the second reference point, and the source electrode and the drain electrode are grounded;
a twelfth bias PMOS tube (MB12), the source electrode of which is connected with the power supply VDD, and the grid electrode and the drain electrode of which are connected with the drain electrode of the thirteenth bias NMOS tube (MB 13);
a thirteenth bias NMOS transistor (MB13), wherein the source thereof is connected to the drain of the sixteenth bias NMOS transistor (MB16), and the gate thereof is connected to the signal terminal Vctrl 2;
a fourteenth bias PMOS tube (MB14), the source of which is connected with the power supply VDD, the grid of which is connected with the grid of the twelfth bias PMOS tube (MB12), and the drain of which is connected with the drain of the fifteenth bias NMOS tube (MB15) and the Vbp signal end;
a fifteenth bias NMOS (MB15) having a source connected to the source of the fifteenth bias NMOS and a drain connected to the drain of the sixteenth bias NMOS (MB16), and a gate connected to the Vmror signal terminal;
a sixteenth bias NMOS transistor (MB16), wherein the grid electrode is connected with the Vbn signal end, and the source electrode is grounded;
a seventeenth bias PMOS tube (MB17), the source of which is connected with the power VDD, the grid of which is connected with the Vbp signal end, and the drain of which is connected with the drain of the nineteenth bias NMOS tube (MB 19);
the source and the drain of the eighteenth bias PMOS tube (MB18) are connected with the drain of the nineteenth bias NMOS tube (MB19), and the gate of the eighteenth bias PMOS tube is connected with the Vbp signal end;
a nineteenth bias NMOS transistor (MB19), the grid of which is connected with the Vbn signal end, and the source of which is grounded;
a twentieth bias PMOS tube (MB20), the grid electrode of which is connected with the Vbn signal end, the source electrode of which is connected with the power supply VDD, and the drain electrode of which is connected with the Vbc signal end;
the twenty-first bias NMOS transistor (MB21) has a drain connected to the Vbc signal terminal, a gate connected to the Vbp signal terminal, and a source connected to ground.
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