KR20050007821A - Phase locked loop circuit having adaptive variable bandwidth - Google Patents

Abstract

PURPOSE: A phase locked loop(PLL) circuit provided with an adaptive variable bandwidth is provided to supply the adaptive variable bandwidth by differently controlling the PLL bandwidth for each of the lock transition period and the lock stabilization period. CONSTITUTION: A phase locked loop(PLL) circuit provided with an adaptive variable bandwidth includes a phase/frequency detector(310), a lock detector(360), a charge pump circuit(320), a loop filter(330), a voltage controlled oscillator(340) and a frequency divider(350). The phase/frequency detector generates the up/down signal corresponding to the phase difference. The lock detector generates the lock/unlock state decision signal by analyzing the pulse width and the pulse generation time period of the up/down signal. The charge pump circuit charges and discharges to the predetermined reference current level in response to the up/down signal. The loop filter filters the input signal in response to the lock/unlock state determination signal by inputting the signal outputted from the charge pump circuit. The voltage controlled oscillator outputs the oscillation frequency in response to the voltage of signal outputted from the loop filter. And, the frequency divider divides the frequency of signal outputted from the voltage controlled oscillator into a predetermined constant value and outputs the divided feedback signal to the phase/frequency detector.

Description

Phase locked loop circuit having adaptive variable bandwidth

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly, to a phase locked loop circuit having an adaptive variable bandwidth that adaptively varies the PLL loop bandwidth to improve noise with shortening the lock time.

A phase locked loop (PLL) circuit detects a phase difference between an input signal and an output signal, and controls the phase of the output signal generator by a voltage proportional thereto to equalize the phase of the output signal with the phase of the input signal. As an operating device to be used, it is mainly used as a frequency oscillation source of each radio transmission and receiver.

As a technique related to a general phase locked loop, Korean Laid-Open Patent Publication No. 2002-0042032, Korean Laid-Open Patent Publication 2002-0090753, Korean Laid-Open Patent Publication 2002-0022918 and the like are known.

Korean Patent Laid-Open Publication No. 2002-0042032 describes a technology related to a charge pump circuit having a fixed pump gain among phase locked loop circuits, and Korean Patent Laid-Open Publication No. 2002-0090753 discloses a technology related to a phase / frequency detection circuit among phase locked loop circuits. Korean Patent Laid-Open Publication No. 2002-0022918 describes a lock detection technique among phase locked loop circuits.

1 shows a configuration of a general phase-locked loop circuit, and compares the phase of the reference signal f _{r with} the phase of the feedback signal f _v and outputs the phase difference, and operates until the value becomes zero. The charge pump circuit 120 receives the phase difference, that is, the up (DN) or down (DN) output from the phase / frequency detector 110 and the phase / frequency detector 110, which repeatedly executes the switching. ), A voltage controlled oscillator for varying the oscillation frequency according to the voltage of the signal input from the loop filter 130 and the loop filter 130 passing only a specific band required among the frequency bands of the signal output from the charge pump circuit 120 ( 140, the frequency divider 150 divides the frequency of the output signal of the voltage controlled oscillator 140 at 1 / N and feeds it back to the phase / frequency detector 110.

In the conventional phase-locked loop circuit, when a frequency and a frequency band to be used in the design process are determined, the PLL loop bandwidth is fixed to a constant value B0 as shown in FIG. 2.

However, the PLL loop bandwidth affects lock transition time and noise performance. In other words, if the PLL loop bandwidth is determined to be relatively narrow, the noise performance is improved, but there is a disadvantage in that the lock transition time for transition to a stable synchronization state becomes long. On the other hand, if the PLL loop bandwidth is relatively wide, the lock transition time may be shortened, but the noise may be affected.

Therefore, the PLL design method according to the related art has a problem in that the PLL loop bandwidth is fixedly designed so that the lock transition time and the noise performance cannot be improved together.

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a phase locked loop circuit having an adaptive variable bandwidth by controlling PLL loop bandwidths differently for each lock transition period and lock stable period of a PLL.

1 is a configuration diagram of a general phase locked loop circuit.

2 illustrates loop band characteristics of a phase locked loop circuit according to the related art.

3 is a block diagram of a phase locked loop circuit having an adaptive variable bandwidth according to the present invention.

4 (a) to 4 (e) are timing diagrams of main signals applied to the present invention.

FIG. 5 is a detailed block diagram of the charge pump circuit of FIG. 3.

FIG. 6 illustrates a current signal output from the charge pump circuit of FIG. 3.

FIG. 7 is a detailed circuit diagram of the loop filter of FIG. 3.

8 illustrates loop band characteristics of a phase locked loop circuit having an adaptive variable bandwidth according to the present invention.

In order to achieve the above technical problem, a phase locked loop circuit having an adaptive variable bandwidth according to the present invention, in a phase locked loop circuit, inputs a feedback signal output from a reference signal and a frequency divider, and thus, the reference signal and the feedback signal. A phase / frequency detector for generating an up / down signal corresponding to the phase difference, a pulse width and a pulse generation time interval of the up / down signal by analyzing a phase difference of A charge pump circuit for charging or discharging around a predetermined reference current level according to the up / down signal by applying a detector, a charge pump gain value determined according to the lock / unlock state determination signal, and a signal output from the charge pump circuit To input an input signal with a frequency characteristic determined according to the lock / unlock state determination signal. A loop filter for filtering, a voltage controlled oscillator for varying the oscillation frequency according to the voltage of the signal output from the loop filter and a frequency of the signal output from the voltage controlled oscillator are divided into predetermined constant values, and the divided feedback signal It characterized in that it comprises a frequency divider for outputting to the phase / frequency detector.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, a phase locked loop circuit having an adaptive variable bandwidth according to the present invention includes a phase / frequency detector 310, a charge pump circuit 320, a loop filter 330, and a voltage controlled oscillator 340. , Frequency divider 350 and lock detector 360.

The phase / frequency detector 310 is composed of a plurality of logic circuit elements, and compares the phase of the reference signal f _{r with} the phase of the feedback signal f _v and outputs the phase difference.

Assume that the reference signal f _r and the feedback signal f _v are input to the phase / frequency detector 310 at the same timing as 4 (a) and (b), respectively.

Then, if the reference signal is faster in phase than the feedback signal, the phase / frequency detector 310 generates an UP pulse as shown in FIG. On the other hand, when the reference signal is slower in phase than the feedback signal, a down (DN) pulse as shown in FIG. 4 (d) is generated during the phase difference.

The lock detector 360 inputs an up / down pulse corresponding to the phase difference signal output from the phase / frequency detector 310 to determine whether the lock detector 360 is in a locked state or an unlocked state. It is effective to design the lock state by detecting the width of the up or down pulse and the time interval between occurrences. That is, it is determined as a locked state when an up or down pulse of less than M nsec is generated or no up / down pulse is generated for more than N cycles or more. Here, the N value and the M value are determined in consideration of the precision required by the system to which the phase locked loop circuit is applied. In an embodiment of the present invention, N = 3, M = 15nsec. The lock / unlock state determination signal LD is shown in Fig. 4E.

The charge pump circuit 320 applies the charge pump gain value determined according to the logic value of the lock / unlock state determination signal LD, and charges or centers around the reference current level based on the phase difference signal (up / down pulse). The discharge is output to the loop filter 330.

A detailed block diagram of the charge pump circuit 320 is shown in FIG.

The reference current supply unit 320-1 is a circuit block for supplying a reference current Ico for generating a reference voltage for controlling the frequency and phase of the oscillation signal of the voltage controlled oscillator 340.

The charge pump gain determiner 320-3 is a circuit block that determines the charge pump gain Kφ related to the level of the charge or discharge voltage in the section where the up / down pulse is generated. That is, when the logic value of the lock / unlock state determination signal LD transitions to the lock state having a high value, the charge pump gain value is determined as the first gain value in the up / down pulse generation period, and the lock is performed. If the logic value of the unlock state determination signal LD is in the UNLOCK state having a low value, the second gain value having a gain greater than the first gain value in the up / down pulse generation period is charged. Determine the pump gain value.

The charge / discharge switching unit 320-2 inputs a reference current Ico generated by the reference current supply unit 320-1 and a charge pump gain value determined by the charge pump gain determination unit 320-3 to output a phase / frequency. Charge or discharge switching is performed by a level corresponding to the charge pump gain value determined based on the reference current Ico according to the up pulse or the down pulse DN output from the detector 310.

That is, the signal output from the charge pump circuit 320 will be described with reference to FIG. 6 as follows.

Since the UP pulse is generated in the T1 section and the down (DN) pulse is generated in the T2 section, the charge pump circuit 320 outputs the reference current Ico in sections other than the T1 and T2 sections.

In the periods T1 and T2, the charge pump gain determiner 320-3 is charged or discharged at a level corresponding to the charge pump gain value determined by the charge pump gain determiner 320-3.

When the logic value of the lock / unlock state determination signal LD is in a locked state having a high value, the reference current Ico may be centered by a level corresponding to the first gain value in the T1 and T2 periods. Charging or discharging, and when the logic value of the lock / unlock state determination signal LD is in the UNLOCK state having a low value, the b-level corresponding to the second gain value in the T1 and T2 intervals is used. Charge or discharge around the reference current (Ico).

Above, the charge pump gain Kφ has a property that is proportional to the loop bandwidth of the phase locked loop circuit. Thus, it can be seen that the loop bandwidth of the phase locked loop circuit is increased when in the unlocked state as compared to when in the locked state.

The loop filter 330 is a circuit block which inputs an output signal of the charge pump circuit 320 and filters only signals of a desired band and outputs them to the voltage controlled oscillator 340.

As illustrated in FIG. 7, the loop filter 330 includes a plurality of capacitors C1 to C4, a plurality of resistors R1 to R3, and switches S1 and S2 as an example.

Capacitors C1 and C2 are each designed with different capacitances and are also designed with different values of resistors R1 and R2. This is to change the frequency band by switching and changing the values of the resistors and capacitors, which are circuit elements constituting the loop filter 330.

That is, in the locked state (LD; HIGH), the resistors and capacitors are switched in the switches (S1, S2) to minimize the frequency band, and in the unlocked state (LD; LOW), the switches (S1, S2) Switch the resistor and capacitor values at to maximize the frequency band.

The voltage controlled oscillator 340 outputs a variable oscillation frequency according to the voltage of the signal input from the loop filter 330.

The signal fvco output from the voltage controlled oscillator 340 divides the frequency at 1 / N in the frequency divider 350 and feeds it back to the phase / frequency detector 310.

Accordingly, according to the present invention, the charge pump gain of the charge pump circuit 320 of the phase locked loop circuit and the frequency characteristic of the loop filter 330 may be controlled according to the lock / unlock state detected by the lock detector 360. It became possible.

That is, when the phase locked loop circuit is in an unlocked state, that is, in an initial non-synchronized section or a frequency transition section, as shown in FIG. 8, the loop bandwidth can be maximized to B2 to minimize the lock time.

In addition, when the phase locked loop circuit is in the locked state, that is, in the period in the synchronous stable state, as shown in FIG. 8, the loop bandwidth is minimized to B1 to minimize the noise effect.

Specific embodiments shown and described in the accompanying drawings are only to be understood as an example of the present invention, not to limit the scope of the invention, but also within the scope of the technical spirit described in the present invention in the technical field to which the present invention belongs As various other changes may occur, it is obvious that the invention is not limited to the specific constructions and arrangements shown or described.

As described above, according to the present invention, by controlling the loop frequency band of the phase locked loop circuit to be changed according to the lock / unlock state, the effect of shortening the lock time and minimizing the noise effect is generated.

Claims (5)

In a phase locked loop circuit, A phase / frequency detector configured to input a feedback signal output from a reference signal and a frequency divider to compare a phase difference between the reference signal and the feedback signal to generate an up / down signal corresponding to the phase difference; A lock detector for analyzing a pulse width and a pulse generation time interval of the up / down signal to generate a lock / unlock state determination signal; A charge pump circuit configured to charge or discharge around a predetermined reference current level according to the up / down signal by applying a charge pump gain value determined according to the lock / unlock state determination signal; A loop filter inputting a signal output from the charge pump circuit and filtering an input signal with a frequency characteristic determined according to the lock / unlock state determination signal; A voltage controlled oscillator for varying and outputting an oscillation frequency according to a voltage of a signal output from the loop filter; And And a frequency divider dividing the frequency of the signal output from the voltage controlled oscillator to a predetermined constant value and outputting the divided feedback signal to the phase / frequency detector. The lock detector of claim 1, wherein the lock detector generates a lock state determination signal when the pulse width of the up / down signal is less than a predetermined threshold value continuously for a predetermined cycle, and generates an unlock state determination signal otherwise. A phase locked loop circuit having an adaptive variable bandwidth. The method of claim 1, wherein the charge pump circuit A reference current supply unit for supplying a reference current for generating a reference voltage for controlling the frequency and phase of the oscillation signal of the voltage controlled oscillator; When the lock state determination signal is applied from the lock detector, the charge pump gain value is determined by the first gain value, and when the unlock state determination signal is applied, the charge is obtained by the second gain value having a gain greater than the first gain value. A charge pump gain determiner configured to determine a pump gain value; And And a charge / discharge switching unit configured to charge or discharge the reference current by a level corresponding to the charge pump gain value determined by the charge pump gain determiner based on the reference current in a section where the up / down signal is generated. A phase locked loop circuit having an adaptive variable bandwidth, characterized in that. The second bandwidth of claim 1, wherein the loop filter determines the frequency characteristic as the first bandwidth when the lock state determination signal is applied, and the second bandwidth wider than the first bandwidth when the unlock state determination signal is applied. A phase locked loop circuit having an adaptive variable bandwidth, characterized in that determined by. The phase locked loop circuit of claim 1, wherein the loop filter varies frequency characteristics by switching resistors and capacitors constituting the filter according to an input lock / unlock state determination signal. .