KR102316443B1 - Delay locked circuit and method of controlling delay range for delay locked loop - Google Patents

Abstract

The delay lock circuit for controlling the delay range of the delay lock loop _{detects a phase difference between an external clock signal (CLK REF} ) and an internal clock signal and generates an UP signal or a DOWN signal corresponding to the phase difference. sensing unit; a charge pump unit for outputting a current signal by increasing or decreasing the current according to the UP signal or the DOWN signal; a loop filter unit for outputting the current signal output from the charge pump unit as a control voltage signal (V _{CONT ) from which a high frequency component is removed;} a delay extension unit receiving the external clock signal (CLK _REF ) and the control voltage signal (V _CONT ) and outputting a delayed extension voltage signal (V _{DE );} a code controller configured to generate a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT );} and a voltage-controlled delay unit formed of a plurality of delay cells and outputting a delayed internal clock signal CLK _{D by changing a delay value of the internal clock according to the binary control code.} Accordingly, a wide operating range can be realized by actively controlling the delay range of the delay lock loop according to the period of the reference clock signal.

Description

DELAY LOCKED CIRCUIT AND METHOD OF CONTROLLING DELAY RANGE FOR DELAY LOCKED LOOP

The present invention relates to a delay lock circuit and method for controlling a delay range of a delay lock loop, and more particularly, to a communication IC supporting various data rates, particularly a delay lock for controlling a delay range of a delay lock loop for visible light communication It relates to circuits and methods.

Data rates of visible light communication vary from Mbps to Gbps, and clock signals in MHz to GHz units are required to sample and process input data.

A conventional delay locked loop (DLL) for controlling the clock signal is a voltage controlled delay (VCDL) composed of a phase detector (PD), a charge pump (CP), a loop filter (LF), and a delay cell (DC). line) is composed of

The reference clock signal is input to the PD and VCDL, and the PD detects a phase difference between the reference clock signal and the VCDL output clock signal. The CP increases or decreases the current according to the output signal of the PD to output the current in the form of a current, and the control voltage signal is supplied to the VCDL to adjust the delay time of the VCDL output signal.

Since the delay lock loop (DLL) has a negative feedback structure, the entire circuit operates so that the phase difference between the reference clock signal and the VCDL output clock becomes 0.

When the delay lock loop (DLL) operates normally, the total delay time of VCDL is equal to one cycle time of the reference clock. Therefore, the reference clock and the VCDL output clock are synchronized with a delay time of one period. One of the factors that determine the normal operation and the abnormal operation of the delay lock loop (DLL) is the minimum delay time and maximum delay time of VCDL with respect to the control voltage, that is, the maximum/minimum delay range.

If the period (1/frequency) of the reference clock has a period greater than the maximum delay time of the maximum/minimum delay range of the VCDL, even with the maximum delay value of the VCDL, the delay lock loop (DLL) is less than one period of the clock. ) cannot be locked.

Conversely, if the period of the reference clock is smaller than the minimum delay value of the VCDL, the delay lock loop (DLL) is locked in N periods (N = 2 or more) because it deviates from one period of the reference clock even if the VCDL has the minimum delay value. This causes a problem called harmonic lock.

US 2008/0136478 A1 US 2008/0315927 A1 US 0756136 B1 JP 4692855 B2

Accordingly, the technical problem of the present invention was conceived in this regard, and an object of the present invention is to actively change the maximum/minimum delay range of the output signal of the voltage control delay unit VCDL as the cycle of the reference clock signal changes to delay the delay. It is to provide a delay lock circuit that controls the delay range of the lock loop.

Another object of the present invention is to provide a method for controlling a delay range of a delay lock loop using the delay lock circuit.

A delay lock circuit for controlling a delay range of a delay lock loop according to an embodiment of the present invention for realizing the object of the present invention _{detects the phase difference between the external clock signal (CLK REF} ) and the internal clock signal corresponding to the phase difference a phase detection unit for generating an up (UP) signal or a down (DOWN) signal; a charge pump unit for outputting a current signal by increasing or decreasing the current according to the UP signal or the DOWN signal; a loop filter unit for outputting the current signal output from the charge pump unit as a control voltage signal (V _{CONT ) from which a high frequency component is removed;} a delay extension unit receiving the external clock signal (CLK _REF ) and the control voltage signal (V _CONT ) and outputting a delayed extension voltage signal (V _{DE );} a code controller configured to generate a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT );} and a voltage-controlled delay unit formed of a plurality of delay cells and outputting a delayed internal clock signal CLK _{D by changing a delay value of the internal clock according to the binary control code.}

In an embodiment of the present invention, the delay extender includes: a plurality of delay cells outputting the delayed external clock signal DCLK of the external clock signal CLK _{REF when the control voltage signal V CONT is input;} a comparator for outputting a phase difference between the external clock signal CLK _REF and the delayed external clock signal DCLK as a voltage pulse V _{X ;} an inverter unit outputting a constant current signal according to the voltage pulse (V _{X );} and charging or discharging a charge corresponding to the current signal to a capacitor to generate the delayed extension voltage signal (V _DE ), and when the binary control code is changed, set the delayed extension voltage signal (V _DE ) to a preset voltage value and a delayed extension voltage signal generator initializing to .

In an embodiment of the present invention, the code control unit compares the values of the control voltage signal V _CONT and the delayed extension voltage signal V _DE with the driving voltage VDD and the ground voltage GND, respectively. hysteresis comparator; First and second ANDs for outputting a value of the driving voltage VDD when the comparison values of the plurality of hysteresis comparators are within a preset range, and outputting a value of the ground voltage GND when out of a preset range gate; and an accumulator that generates a code change signal that changes the binary control code when the first and second AND gates do not respectively output the ground voltage GND.

In an embodiment of the present invention, when the code change signal is generated, the accumulator controls the binary control when _{an external clock signal CLK REF having a higher frequency than an operation region of the voltage control delay unit VCDL is input.} a register for reducing the delay value of the internal clock by setting all codes (CD<2:0>) to 0; _{and when the external clock signal CLK REF} having a lower frequency than the operating region of the voltage control delay unit VCDL is input, the binary control code CD<2:0> is increased to increase the delay value of the internal clock signal. It may include an accumulator that increases the .

In a method for controlling a delay range of a delay lock loop according to an embodiment of the present invention for realizing another object of the present invention, _{a phase difference between an external clock signal (CLK REF} ) and an internal clock signal is detected and the up corresponding to the phase difference generating a (UP) signal or a down (DOWN) signal; outputting a current signal by increasing or decreasing the current according to the UP signal or the DOWN signal; outputting the output current signal as a control voltage signal V _CONT from which a high frequency component is removed; receiving the external clock (CLK _REF ) and the control voltage signal (V _CONT ) and outputting a delayed extension voltage signal (V _{DE );} generating a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT ); and outputting a delayed internal clock signal CLK D} by changing a delay value of the internal clock according to the binary control code.

According to the delay lock circuit for controlling the delay range of the delay lock loop, a wide frequency range can be secured by generating a binary control code and extending the minimum/maximum delay range using the generated binary control code. Accordingly, both a case where a low frequency is required and a case where a high frequency is required can be used.

In addition, since the maximum/minimum delay range of the output signal can be actively controlled as the period of the reference clock signal is changed, a wide operating range can be secured in a device to which the present invention is applied.

1 is a block diagram of a delay lock circuit for controlling a delay range of a delay lock loop according to the present invention.
FIG. 2 is a circuit diagram of the delay extension unit of FIG. 1 according to an exemplary embodiment.
FIG. 3 is a pulse diagram illustrating voltage pulse values of the delay extension unit according to FIG. 2 .
4 is a graph illustrating outputs of a control voltage signal and a delayed extension voltage signal in a low frequency mode when the delay lock circuit according to the present invention operates normally.
5 is a graph illustrating outputs of a control voltage signal and a delayed extension voltage signal in a low frequency mode when the delay lock circuit according to the present invention operates abnormally.
6 is a graph illustrating outputs of a control voltage signal and a delayed extension voltage signal in a high frequency mode when the delay lock circuit according to the present invention operates normally.
7 is a graph illustrating outputs of a control voltage signal and a delayed extension voltage signal in a high frequency mode when the delay lock circuit according to the present invention operates abnormally.
8 is a classification table according to the reference frequency REF and the VCDL operating region of the _{external clock signal CLK REF} shown in FIGS. 4 to 7 .
9 is a circuit diagram of a delay cell included in the voltage-controlled delay unit of FIG. 1 according to an exemplary embodiment.
10 is a circuit diagram of the code control unit of FIG. 1 according to an embodiment.
11 is a circuit diagram of an accumulator of FIG. 10 according to an embodiment.
12 is a graph showing the delay _{of the control voltage signal V CONT} according to the binary control code in the delay lock circuit according to the present invention.
13 is a graph showing a simulation result (100 MHz, low frequency mode) in a normal operation in the delay lock circuit according to the present invention.
14 is a graph showing a simulation result (1 GHz, high frequency mode) in a normal operation in the delay lock circuit according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0023] Reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein with respect to one embodiment may be embodied in other embodiments without departing from the spirit and scope of the invention. In addition, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the invention, if properly described, is limited only by the appended claims, along with all scope equivalents to those claimed. Like reference numerals in the drawings refer to the same or similar functions throughout the various aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a block diagram of a delay lock circuit for controlling a delay range of a delay lock loop according to the present invention.

The present invention compensates for the limitation of the delay range by the control voltage of the existing analog delay locked loop (DLL). To this end, after detecting a frequency, a control code is generated by the code controller. The generated control code controls the delay lock loop to be locked by changing the delay range of the voltage control delay unit VCDL.

1, the delay lock circuit (1, hereinafter, delay lock circuit) for controlling the delay range of the delay lock loop according to the present invention is a delay lock loop 10 and a delay extension unit 30, Frequency Detector for Delay range Extension; FDDE) and a code controller (50, code controller).

According to an embodiment of the present invention, the delay lock loop 10 includes a phase detector 100, a phase detector 100, a charge pump 300, a loop filter 500, a loop filter LF, and a voltage. It may include a controlled delay unit 700 (Voltage Controlled Delay Line; VCDL).

The phase detection unit 100 detects _{a phase difference between an external clock signal CLK REF} provided as a reference clock and an internal clock signal, and generates an UP signal or a DOWN signal corresponding to the phase difference between the two signals. make it The generated UP signal or DOWN signal is transmitted to the charge pump unit 300 .

The charge pump unit 300 may be implemented as a kind of current switch, and increases or decreases the current according to the UP signal or the DOWN signal to output the current in the form of a current. The current signal output from the charge pump unit 300 passes through the loop filter unit 500 which is a low-pass filter and is output as _{a control voltage signal V CONT from which the high frequency component is removed.}

_{The control voltage signal V CONT} output from the loop filter unit 500 is input to the voltage control delay unit 700 and the code control unit 50 , and the voltage control delay unit 700 controls the internal clock. By changing the delay value, the overall delay value of the delay lock circuit 1 is changed.

The delay extension unit 30 receives the external clock signal CLK _REF and the control voltage signal V _CONT to generate a delay range extension voltage signal V _DE.

When the delay extension voltage signal V _{DE generated by the delay extension unit 30 and the control voltage signal V CONT} output from the loop filter unit 500 are transmitted to the code control unit 50 , the code control unit Reference numeral 50 generates a binary control code for controlling the delay range of the internal clock output from the voltage controlled delay unit 700 .

The binary control code is unidirectional and increments. For example, the binary control code is composed of 3 digits and may increase to 000, 001, 010, 011, 100, 101, 110, 111. However, this is only an example and it may have a binary control code of two or more digits, and as the number of digits increases, the delay range of the internal clock may be more finely controlled.

The generated binary control code is applied to the voltage control delay unit 700 to control the delay range of the internal clock, and output the _{delayed internal clock signal CLK D .}

FIG. 2 is a circuit diagram of the delay extension unit of FIG. 1 according to an exemplary embodiment.

2 , the delay extension unit 30 according to an embodiment of the present invention includes a delay cell 310, a delay cell, a comparator 330, an inverter unit 350, a current starved inverter, and a delay extension voltage. It may be configured as a signal generator 370 .

The delay extension unit 30 receives the external clock signal CLK _REF and the control voltage signal V _CONT and outputs a delayed extension voltage signal V _{DE .} In the delay extension unit 30 , a plurality of delay cells 310 may be connected in series, and although two delay cells are illustrated in FIG. 2 , the delay cells may be increased or decreased as necessary.

In addition, the delay cell 310 may have the same configuration as the delay cells constituting the voltage control delay unit 700 , and the external clock signal CLK _REF is delayed _{by the control voltage signal V CONT .} value can be changed.

It said external clock signal (CLK _REF) that when passing through the plurality of delay cells 310, the delay to the external clock signal (CLK _REF) is generated, delayed external clock signal, the external clock signal (CLK _REF) delay occurs (DCLK).

The comparator 330 may be configured as an XOR gate, and serves as a phase detector. The external clock signal CLK _REF and the delayed external clock signal DCLK are compared, and a phase difference between the two signals is output as a _{voltage pulse V X .}

The inverter unit 350 serves as a charge pump and outputs a constant current corresponding thereto according to the value of _{the voltage pulse V X .} In FIG. 2 , V _P and V _N are bias voltages that allow a constant current to always flow through the PMOS and the NMOS.

_{The delayed extension voltage signal generator 370 generates the delayed extension voltage signal V DE} by charging or discharging a charge corresponding to the current signal to a capacitor, and when the binary control code is changed, the delayed extension voltage The signal V _DE is initialized to a preset voltage value.

FIG. 3 is a pulse diagram illustrating voltage pulse values of the delay extension unit according to FIG. 2 . 4 to 5 are graphs illustrating outputs of a control voltage signal and a delayed extension voltage signal according to the present invention.

When the entire delay lock circuit 1 operates normally (locked state), the pulse width of the _{voltage pulse V X is equal to half the period as shown in FIG. 3A .} Therefore, since I _P : I _N = 1:1, the delayed extension voltage signal V _DE has a stable value as shown in FIGS. 4 and 6 .

When the entire delay lock circuit 1 operates abnormally (unlocked state), the pulse width of the _{voltage pulse V X is not constant as shown in FIGS. 3B and 3C .} Accordingly, the delayed extension voltage signal V _DE moves to the ground voltage GND or the driving voltage VDD as shown in FIGS. 5 and 7 . At this time, the code control unit 50 is updated and generates a code change signal for changing the binary control code.

The delayed extension voltage signal generating unit 370 may be implemented as a low pass filter (LPF), and charges or discharges a charge corresponding to the output of the inverter unit 350 in a capacitor. As a result, the delayed extension voltage signal V _DE may be generated.

For example, a low-pass filter may be used to reduce a voltage change of the loop filter in a loop filter including a single capacitor having a conventional structure. In addition, the amount of capacitance can be adjusted by using a switched capacitor using _{CD/CD B <2>.} Through this, it is possible to reduce the bandwidth of the delay lock loop 10 in the low frequency mode.

When the entire delay lock circuit 1 is in an abnormal operation, the delayed extension voltage signal V _DE has a ground voltage GND or a driving voltage VDD value. Whenever the control code is changed, the delayed extension voltage signal V _DE may be controlled to start at a stable voltage value.

For example, using RST _H and RST _L as switch inputs, the initial voltage of the delayed extension voltage signal V _DE is converted to an intermediate value (eg, 0.9V) of the operating voltage (eg, 1.8V). can be initialized.

_{A table summarizing the case classification according to the reference frequency REF of the} external clock signal CLK REF presented in FIGS. 4 to 7 and the VCDL operation region is shown in FIG. 8 .

Referring to FIG. 8 , as shown in FIG. 4 , the reference frequency REF is input as a low frequency of 100 MHz or less, and the voltage control delay unit VCDL operating region is also in a low frequency mode of 100 MHz or less.

In this case, the delay lock circuit 1 is in a normal operating state, and the control voltage signal V _CONT and the delay extension voltage signal V _DE output from the loop filter unit 500 have stable values. Accordingly, the code control unit 50 does not generate a code change signal, and the delay lock circuit 1 maintains the current state.

On the other hand, as shown in FIG. 5 , the reference frequency REF is input at a low frequency of 100 MHz or less, and the operating region of the voltage control delay unit VCDL is a high frequency mode of 1 GHz or more.

In this case, the delay lock circuit 1 is in an abnormal operating state, the control voltage signal V _CONT output from the loop filter unit 500 converges to the driving voltage VDD value, and the delay extension voltage signal V _DE is It converges to the ground voltage (GND) value. Accordingly, the code control unit 50 generates a code change signal.

As shown in FIG. 6 , the reference frequency REF is input as a high frequency of 1 GHz or more, and the operating region of the voltage control delay unit VCDL is a high frequency mode of 1 GHz or more.

In this case, the delay lock circuit 1 is in a normal operating state, and the control voltage signal V _CONT and the delay extension voltage signal V _DE output from the loop filter unit 500 have stable values. Accordingly, the code control unit 50 does not generate a code change signal, and the delay lock circuit 1 maintains the current state.

On the other hand, as shown in FIG. 7 , the reference frequency REF is input at a high frequency of 1 GHz or more, and the operating region of the voltage control delay unit VCDL is a low frequency mode of 100 MHz or less.

In this case, the delay lock circuit 1 is in an abnormal operating state, and the control voltage signal V _CONT and the delay extension voltage signal V _DE output from the loop filter unit 500 converge to the driving voltage VDD value. . Accordingly, the code control unit 50 generates a code change signal.

9 is a circuit diagram according to an embodiment of a delay cell (DC) included in the voltage controlled delay unit of FIG. 1 .

Referring to FIG. 9 , a circuit constituting the voltage control delay unit 700 as an embodiment of the delay cell DC 701 is implemented using an inverter (current starved inverter). Although only one delay cell DC of FIG. 9 is illustrated, two or more delay cells DC may be connected as needed.

_{V CP} of the upper switch is a bias voltage that causes the upper PMOS to operate as a current source. At this time, the flowing currents are proportional to the Width/Length of each PMOS.

Each delay cell DC receives the external clock signal CLK _REF or the output signal of the previous delay cell DC through the input terminal IN, and the output signal of each delay cell DC through the output terminal OUT. Output, finally the delayed internal clock signal (CLK _D ).

In addition, each delay cell DC adds a switch that receives the binary control code output from the code control unit 50 as an input, and adjusts the amount of current according to the binary control code to control the internal clock signal CLK _D . You can change the delay value.

When the binary control code increases, the upper and lower switches of the inverter are turned off, the amount of current decreases, and the delay time of the voltage control delay unit VCDL gradually increases. Accordingly, when all of the binary control codes CD<2:0> are 1, the current is minimized and the delay demonstration is longest.

10 is a circuit diagram of the code control unit of FIG. 1 according to an embodiment. 11 is a circuit diagram of an accumulator of FIG. 10 according to an embodiment.

Referring to FIG. 10 , the code control unit 50 may include a plurality of hysteresis comparators 511 , 512 , 513 , 514 , first and second AND gates 531 and 533 , and an accumulator 550 . .

The plurality of hysteresis comparators 511 , 512 , 513 , and 514 compare the values of the control voltage signal V _CONT and the delayed extension voltage signal V _DE with the driving voltage VDD and the ground voltage GND respectively. Compare.

The first and second AND gates 531 and 533 output a value of the driving voltage VDD when the comparison values of the plurality of hysteresis comparators 511 , 512 , 513 , and 514 are within a preset range, and If it is out of the set range, the value of the ground voltage (GND) is output.

When both the first and second AND gates output the ground voltage GND, the accumulator 550 does not generate a code change signal and maintains the previous state. Otherwise, the accumulator 550 generates a code change signal for changing the binary control code.

11, the accumulator 550 is the 1 AND output (RST _B) and an external clock signal of the AND gate 531, the output (RST _A) an input to receive the adder 551 and the 2 AND gate 533 of the It may include a register 553 for receiving an external clock signal (CLK _REF) in _(REF CLK).

The code control unit 50 receives the delayed extension voltage signal V _{DE output from the delay extension unit 30 and the control voltage signal V CONT} output from the loop filter unit 500 as inputs.

When the values of the control voltage signal V _CONT and the delayed extension voltage signal V _DE are close to the values of the driving voltage VDD and the ground voltage GND to be compared, respectively, the hysteresis comparators 511, 512, A driving voltage VDD is generated as an output of 513 and 514, otherwise a ground voltage GND is generated.

When the delay lock circuit 1 operates normally, the outputs RST _A and RST _{B of} the first and second AND gates 531 and 533 all have a ground voltage GND value, so the binary control code remains unchanged and retains its previous state.

On the other hand, when the delay lock circuit 1 operates abnormally, it can be divided into two situations. 1) In the low frequency mode, a _{high frequency is input to the external clock signal CLK REF} , and 2) In the high frequency mode, a low frequency is input to the _{external clock signal CLK REF .}

_{Since the delay value of the internal clock signal CLK D} increases as the binary control code increases, in situation 1), the delay time needs to be decreased, so that the output RST _B of the second AND gate 533 is stored in the register ( 553) to make the binary control code CD<2:0> all 0 (because it has unidirectionality).

2) In this situation, since the delay time should be increased, the output RST _A of the first AND gate 531 operates the adder 551 to increase the binary control code CD<2:0>.

Accordingly, the binary control code generated according to the operating state may change the delay value of the output signal of each delay cell DC of the voltage control delay unit VCDL.

12 is a graph showing the delay _{of the control voltage signal V CONT} according to the binary control code in the delay lock circuit according to the present invention.

12, as the binary control code CD<2:0> increases to 000, 001, 010, 011, 100, 101, 110, 111, the delay time according to the _{control voltage signal V CONT increases.} can be checked

13 is a graph showing a simulation result (100 MHz, low frequency mode) in a normal operation in the delay lock circuit according to the present invention. 14 is a graph showing a simulation result (1 GHz, high frequency mode) in a normal operation in the delay lock circuit according to the present invention.

Referring to FIG. 13 _{, when 100 MHz is input as an external clock signal (CLK REF} ), the binary control code CD<2:0> continues to increase and when a specific code is reached, it can be seen that the delay lock circuit is locked. have.

Referring to FIG. 14 , when _{1 GHz is input as the external clock signal CLK REF} , it can be seen that the delay lock circuit is directly locked in the binary control code 000, which is the high frequency mode.

A delay locked loop (DLL) method is divided into an analog and a digital method, and the difference between the two types of delay locked loop (DLL) is in the configuration of the voltage control delay unit (VCDL). In the analog delay lock loop (DLL) _{, the delay value is continuously changed by the control voltage signal (V CONT} ), and the digital delay lock loop (DLL) selects a delay cell corresponding to the detected phase difference step by step will change to

Due to this difference, the analog type has good jitter characteristics of the voltage control delay unit (VCDL), but the locking time is long, and the digital type has a fast locking time, but the jitter characteristics are not good.

The circuit proposed in the present invention uses both the analog method and the digital method using codes, so the locking time is shorter than that of the existing analog method (All Analog), and the jitter characteristic is lower than that of the existing digital method (All Digital). great. In addition, by extending the minimum/maximum delay range using a binary control code, a wide frequency range is provided, so that it can be used both when a low frequency is required and when a high frequency is required.

In a memory with a wide range of operating frequencies, the range of tracking the delay of a delay lock loop (DLL) is important. The lower the operating voltage, the smaller the voltage range controlled by the delay lock loop (DLL). Therefore, it is difficult to fabricate a chip having an operating range of several hundred MHz to several GHz in the existing structure. However, a wide operating range can be obtained by controlling the delay range using the circuit proposed in the present invention.

Although described above with reference to the embodiments, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below You will understand.

Since the present invention can extend and control the delay range of the delay lock loop (DLL), it can be applied to a communication system, a high-speed data transmission/reception circuit, or a home appliance such as a TV, and is particularly usefully applicable to a display interface such as a DDI.

1: Delay lock circuit
10: Lazy Lock Loop
30: delay extension
50: code control
100: phase detection unit
300: charge pump unit
500: loop filter unit
700: voltage control delay unit
310: delay cell
330: comparison unit
350: inverter unit
370: delay extension voltage signal generator
701: delay cell
511, 512, 513, 514: hysteresis comparator
531, 533: AND gate
550: accumulator
551: Adder
553: register

Claims (5)

a phase detection unit detecting a phase difference between an external clock signal (CLK _REF ) and an internal clock signal and generating an UP signal or a DOWN signal corresponding to the phase difference;
a charge pump unit for outputting a current signal by increasing or decreasing the current according to the UP signal or the DOWN signal;
a loop filter unit for outputting the current signal output from the charge pump unit as a control voltage signal (V _{CONT ) from which a high frequency component is removed;}
a delay extension unit receiving the external clock signal (CLK _REF ) and the control voltage signal (V _CONT ) and outputting a delayed extension voltage signal (V _{DE );}
a code controller configured to generate a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT );} and
a voltage control delay unit formed of a plurality of delay cells and outputting a delayed internal clock signal (CLK _{D ) by changing the delay value of the internal clock according to the binary control code;}
The code control unit,
a plurality of hysteresis comparators comparing values of the control voltage signal (V _CONT ) and the delayed extension voltage signal (V _DE ) with values of a driving voltage (VDD) and a ground voltage (GND), respectively;
First and second ANDs for outputting a value of the driving voltage VDD when the comparison values of the plurality of hysteresis comparators are within a preset range, and outputting a value of the ground voltage GND when out of a preset range gate; and
and an accumulator that generates a code change signal for changing the binary control code when the first and second AND gates do not output a value of the ground voltage GND, respectively; Delay lock circuit to control the range.
The method of claim 1, wherein the delay extension unit,
a plurality of delay cells outputting the delayed external clock signal DCLK of the external clock signal CLK _REF when the control voltage signal V _{CONT is input;}
a comparator for outputting a phase difference between the external clock signal CLK _REF and the delayed external clock signal DCLK as a voltage pulse V _{X ;}
an inverter unit outputting a constant current signal according to the voltage pulse (V _{X );} and
A charge corresponding to the current signal is charged or discharged in a capacitor to generate the delayed extension voltage signal V _DE , and when the binary control code is changed, the delayed extension voltage signal V _DE is set to a preset voltage value. A delay lock circuit for controlling a delay range of a delay lock loop, comprising: a delay extension voltage signal generator to initialize.
delete The method of claim 1 , wherein the accumulator comprises:
When the code change signal is generated,
_{When the external clock signal CLK REF} having a higher frequency than the operating region of the voltage control delay unit VCDL is input, the binary control codes CD<2:0> are all set to 0 to delay the internal clock register to decrement the value; and
_{When the external clock signal CLK REF} having a lower frequency than the operating region of the voltage control delay unit VCDL is input, the binary control code CD<2:0> is increased to increase the delay value of the internal clock signal. A delay lock circuit for controlling a delay range of a delay lock loop, comprising: an accumulator for increasing.
detecting a phase difference between an external clock signal (CLK _REF ) and an internal clock signal and generating an UP signal or a DOWN signal corresponding to the phase difference;
outputting a current signal by increasing or decreasing the current according to the UP signal or the DOWN signal;
outputting the output current signal as a control voltage signal V _CONT from which a high frequency component is removed;
receiving the external clock signal (CLK _REF ) and the control voltage signal (V _CONT ) and outputting a delayed extension voltage signal (V _{DE );}
generating a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT );} and
_{outputting a delayed internal clock signal (CLK D} ) by changing the delay value of the internal clock according to the binary control code;
Generating a binary control code based on the delayed extension voltage signal (V _DE ) and the control voltage signal (V _{CONT ) comprises:
comparing values of the control voltage signal V CONT} and the delayed extension voltage signal V _DE with values of a driving voltage VDD and a ground voltage GND, respectively, using a plurality of hysteresis comparators;
Outputting a value of the driving voltage VDD when the comparison value of the hysteresis comparator is within a preset range using the first and second AND gates, and outputting a value of the ground voltage GND when it is out of the preset range ;
Code for changing the binary control code using an accumulator in other cases, without generating a code change signal when the first and second AND gates do not respectively output the ground voltage GND A delay lock method for controlling a delay range of a delay lock loop, comprising: generating a change signal.

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