KR100370243B1 - Phase locked loop circuit including fast frequency lock control circuit and method for reducing frequency lock time thereof - Google Patents

Abstract

A phase locked loop circuit and a method of reducing the frequency lock time thereof are disclosed that reduce the frequency lock time and also improve the characteristics. The phase locked loop circuit according to the present invention is characterized by having a phase detector, a loop filter, a voltage controlled oscillator, and a divider, in particular a fast frequency lock control circuit. The fast frequency lock control circuit breaks the connection between the phase detector and the loop filter at the initial power on of the phase locked loop circuit and supplies constant current to the loop filter or discharges it from the loop filter for a predetermined period of time. Connect the loop filter. Therefore, since the constant current is supplied to the loop filter or is discharged from the loop filter for a predetermined time in the state in which the phase-locked loop is opened at the initial stage of power-on, there is an advantage that the frequency lock is performed quickly. In addition, once the frequency is locked, phase noise and reference spur may be reduced by reducing the current flowing through the charge pump in the phase detector in the closed loop state, that is, reducing the loop bandwidth.

Description

Phase locked loop circuit including fast frequency lock control circuit and method for reducing frequency lock time

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly, to a phase locked loop circuit and a method of reducing the frequency lock time for reducing frequency lock time and improving characteristics.

The phase locked loop circuit compares the phase of a reference clock signal and a signal fed back from a voltage controlled oscillator (VCO) and synchronizes the phase thereof, and is used in various applications such as a communication system. A conventional conventional phase-locked loop circuit, as shown in FIG. 1, compares the phase of the reference clock signal fr and the feedback clock signal fv to detect a phase difference 11 and a loop filter. 13, a voltage controlled oscillator (VCO) generating an output clock signal fo and varying the frequency of the output clock signal fo in response to the output voltage Vc of the loop filter 13. And a divider 17 for dividing the output clock signal fo at a predetermined division ratio N to provide a divided clock signal as the feedback clock signal fv.

Meanwhile, in the conventional phase-locked loop circuit illustrated in FIG. 1, a method generally used to reduce the frequency lock time is a method of varying loop bandwidth by adjusting a part of loop parameter values. However, this method has a disadvantage in that the frequency lock time cannot be sufficiently reduced, and thus a method for further reducing the frequency lock time is required.

Accordingly, an object of the present invention is to provide a phase locked loop circuit which reduces frequency lock time and improves characteristics.

Another object of the present invention is to provide a method for reducing the frequency lock time of a phase locked loop circuit.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional phase locked loop circuit.

2 is a block diagram of a phase locked loop circuit according to a preferred embodiment of the present invention.

3 and 4 are circuit diagrams showing a first embodiment of the fast frequency lock control circuit shown in FIG.

5 and 6 are circuit diagrams showing a second embodiment of the fast frequency lock control circuit shown in FIG.

The phase locked loop circuit according to the present invention for achieving the above technical problem has a phase detector, a loop filter, a voltage controlled oscillator, a divider, and in particular, a fast frequency lock control circuit. It is done.

The phase detector detects a phase difference by comparing a phase of a reference clock signal and a feedback clock signal. The fast frequency lock control circuit disconnects the connection between the phase detector and the loop filter at the initial power on of the phase locked loop circuit and supplies a constant current to the loop filter for a predetermined time or from the loop filter. And then connect the phase detector and the loop filter. The voltage controlled oscillator generates an output clock signal and varies the frequency of the output clock signal in response to the output voltage of the loop filter. The divider divides the output clock signal at a predetermined division rate to provide a divided clock signal as the feedback clock signal.

According to a preferred embodiment, the fast frequency lock control circuit includes a constant current source having one end connected to a first reference voltage, a first switch connected between the other end of the constant current source and the loop filter, the phase detector and the loop. A second switch connected between filters, and in response to input data and a control clock signal, the first switch is turned on and the second switch is turned off during the predetermined time and the first switch is turned off after the predetermined time. And a control circuit for turning off and turning on the second switch.

Preferably, the input data is the same data as the frequency division ratio of the frequency divider, and the control clock signal is the same signal as the reference clock signal. In addition, the control circuit is preferably implemented using a lock detection counter provided in the phase locked loop circuit, the constant current source is preferably implemented using a charge pump provided in the phase detector.

According to another preferred embodiment, the fast frequency lock control circuit comprises: a first constant current source having one end connected to a first reference voltage, a first switch connected between the other end of the first constant current source and the loop filter, the phase A second switch connected between a detector and the loop filter, a second constant current source having one end connected to a second reference voltage, a third switch connected between the other end of the second constant current source and the loop filter, and the loop filter; A fourth switch connected between the voltage controlled oscillator, and in response to input data and a control clock signal, one of the first switch and the third switch is turned on for a predetermined time and the second switch and the fourth switch are turned on. And a control circuit for turning off the switch and turning off the first switch and the third switch after the predetermined time and turning on the second switch and the fourth switch.

Preferably, the input data is the same data as the frequency division ratio of the frequency divider, and the control clock signal is the same signal as the reference clock signal. In addition, the control circuit is preferably implemented using a lock detection counter provided in the phase locked loop circuit, and the first and second constant current sources are preferably implemented using a charge pump provided in the phase detector. .

According to another aspect of the present invention, there is provided a method of reducing a frequency lock time of a phase locked loop circuit, the phase detector detecting a phase difference by comparing a phase of a reference clock signal and a feedback clock signal, a loop filter, and an output clock signal. A voltage controlled oscillator which generates and varies the frequency of the output clock signal in response to the output voltage of the loop filter, and divides the output clock signal at a predetermined division ratio to provide a divided clock signal as the feedback clock signal. A method of reducing a frequency lock time of a phase locked loop circuit having a period, the method comprising: disconnecting a connection between the phase detector and the loop filter at an initial stage of power-on of the phase locked loop circuit and applying a constant current to the loop filter for a predetermined time. Supplying or discharging from the loop filter; And connecting the phase detector and the loop filter after the predetermined time.

According to a preferred embodiment, supplying the constant current to the loop filter includes: generating the constant current; And in response to an input data and a control clock signal, connecting a connection between said constant current path and said loop filter during said predetermined time and disconnecting a connection between said phase detector and said loop filter.

Preferably, the input data is the same data as the frequency division ratio of the frequency divider, and the control clock signal is the same signal as the reference clock signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram of a phase locked loop circuit according to a preferred embodiment of the present invention.

2, a phase locked loop circuit according to a preferred embodiment of the present invention comprises a phase detector 21, a loop filter 25, a voltage controlled oscillator 27, and a divider 29, in particular a frequency. A fast frequency lock control circuit (FFLC) 23 is provided to reduce the lock time.

The phase detector 21 detects the phase difference by comparing the phase of the reference clock signal fr and the feedback clock signal fv. The fast frequency lock control circuit 23 disconnects the connection between the phase detector 21 and the loop filter 25 at the initial power on of the phase locked loop circuit and loops the constant current for a predetermined time Δt. After supplying to the filter 25, the phase detector 21 and the loop filter 25 are connected. In other words, the fast frequency lock control circuit 23 flows the constant current I through the loop filter 25 for a predetermined time? T calculated using the input data DATA and the system parameters, thereby outputting the output clock signal. The control voltage Vc required by the voltage controlled oscillator 27 is forced to obtain a desired target frequency of (fo).

The voltage controlled oscillator 27 generates an output clock signal fo and varies the frequency of the output clock signal fo in response to the output voltage of the loop filter 25, that is, the control voltage Vc. The divider 29 divides the output clock signal fo at a predetermined division ratio N to provide a divided clock signal as the feedback clock signal fv.

3 and 4 are circuit diagrams showing a first embodiment of the fast frequency lock control circuit shown in FIG. 3 illustrates a case where the loop filter is a first order loop filter 25A, and FIG. 4 illustrates a case where the loop filter is a second order loop filter 25B.

3 and 4, the fast frequency lock control circuit 23A according to the first embodiment includes a loop and the other end of the constant current source I and the constant current source I having one end connected to the power supply voltage VCC. A first switch sw1 connected between the filters 25A and 25B, a second switch sw2 connected between the phase detector 21 and the loop filters 25A and 25B, and a control circuit 231. .

The control circuit 231 turns on the first switch sw1 and turns off the second switch sw2 for a predetermined time DELTA t in response to the input data DATA and the control clock signal CLK. Accordingly, current is supplied to the loop filters 25A and 25B for a predetermined time DELTA t. In addition, the control circuit 231 turns off the first switch sw1 and turns on the second switch sw2 after a predetermined time? T.

In this case, the input data DATA is preferably the same data as the frequency division ratio N of the frequency divider 29 shown in FIG. 2, and the control clock signal CLK is the reference clock signal fr shown in FIG. 2. It is preferable that it is the same signal as. However, any data applied externally may be used as the input data DATA, and another arbitrary clock signal may be used as the control clock signal CLK.

Meanwhile, the control circuit 231 may be implemented using a lock detection counter provided in the phase locked loop circuit, and the constant current source I may be implemented using a charge pump provided in the phase detector 21.

Hereinafter, a method of reducing the frequency lock time of the phase locked loop circuit according to the present invention will be described in detail with reference to FIGS. 2 to 4. In the phase synthesizer loop type frequency synthesizer, the frequency fo of the output clock signal is obtained by the following equation (1).

fo = N * fr

Here, the natural number N is a value determined by the input data DATA and fr is the frequency of the reference clock signal. In addition, the input-output relational expression of the voltage controlled oscillator 27 is expressed by the following equation (2).

fo = Kv * Vc

Here Kv represents the gain of the voltage controlled oscillator 27 and Vc represents the output voltage of the loop filter 25, that is, the control voltage Vc.

As can be seen from Equation (2), Kv is a value uniquely determined by the voltage controlled oscillator 27, so that a control voltage Vc necessary for this to obtain a desired frequency fo is input to the voltage controlled oscillator 27. Should be.

In the conventional phase-locked loop circuit, the control voltage Vc is determined by a negative feedback operation in a state where the phase-locked loop is closed. On the other hand, in the phase-locked loop circuit according to the present invention, the control necessary for the high-speed frequency lock control circuit 23 to make the phase-locked loop an open loop at the initial power-on and to obtain a desired frequency fo in this state In order to generate the voltage Vc, the constant current I is passed through the loop filter 25 for a predetermined time DELTA t.

As shown in FIG. 3, when the loop filter is configured as the primary loop filter 25A, when the constant current I flows to the loop filter 25A for a time Δt, the voltage change ΔVc across the capacitor C is shown. Can be expressed by the following equation (3).

Vc2-Vc1 = ΔVc = ΔQ / C = I * Δt / C

Here, Vc1 represents an initial state value of the control voltage Vc and Vc2 represents a later state value of the control voltage Vc. Q represents the amount of charge stored in the capacitor C during the time Δt by the constant current I. Therefore, time (DELTA) t is calculated | required as following Formula (4) by Formula (1)-(3).

Δt = C * Δfo / Kv * I = C * fr * ΔN / Kv * I = K * ΔN

As can be seen from Eq. (4), the time DELTA t is calculated by N when the parameters C, fr, Kv and I are determined. N is a value determined by the input data DATA and preferably equal to the frequency division ratio N of the frequency divider 29.

In more detail, in the present invention, the control circuit 231 of the fast frequency lock control circuit 23 receives the input data DATA and the control clock signal CLK corresponding to N, and receives the first switch during the time? T. sw1) is turned on and the second switch sw2 is turned off. As a result, the connection between the phase detector 21 and the loop filter 25 is broken so that the phase locked loop is opened and in this state, the constant current I is supplied to the loop filter 25 for a time? T. Therefore, the control voltage Vc necessary to obtain the desired frequency fo is generated and provided to the voltage controlled oscillator 27.

After the time? T, the control circuit 231 turns off the first switch sw1 and turns on the second switch sw2, so that the connection between the phase detector 21 and the loop filter 25 is again Connected, the phase-lock loop is closed and returns to normal.

On the other hand, when the loop filter is composed of a secondary loop filter 25B as shown in FIG. 4, the time Δt is derived as shown in Equation 4 below, and a detailed derivation process is omitted.

Δt = (C1 + C2) * fr * ΔN / Kv * I = K * ΔN

As described above, in the phase-locked loop circuit according to the present invention, the constant current I is supplied to the loop filter 25 for a predetermined time (Δt) with the phase-locked loop open at the initial stage of power-on. Therefore, there is an advantage that the frequency lock is made faster. In addition, since the constant current I is a current for the frequency lock only in the open loop state, the frequency lock can be made faster by increasing the constant current I regardless of the loop stability.

In addition, in the phase-locked loop circuit according to the present invention, once the frequency is locked, phase noise and reference stimulus are reduced by reducing the current flowing through the charge pump in the phase detector 21 in the closed loop state, that is, reducing the loop bandwidth. (Reference Spur) can be reduced.

5 and 6 are circuit diagrams showing a second embodiment of the fast frequency lock control circuit shown in FIG. 5 illustrates a case where the loop filter is a first order loop filter 25A, and FIG. 4 illustrates a case where the loop filter is a second order loop filter 25B.

5 and 6, the fast frequency lock control circuit 23B according to the second embodiment includes a first constant current source I1 and a first constant current source I1 having one end connected to a power supply voltage VCC. A first switch sw1a connected between the other end of the loop filter and the loop filters 25A and 25B, a second switch sw2a connected between the phase detector 21 and the loop filters 25A and 25B, and a ground voltage VSS. And a third switch sw1b connected between the other end of the second constant current source I2 and the loop filters 25A and 25B, and a control circuit 231A. . A fourth switch sw2b is connected between the loop filters 25A and 25B and the voltage controlled oscillator 27.

The control circuit 231A is configured to input data DATA and to increase the control voltage Vc when the later state value Vc2 of the control voltage Vc is greater than the initial state value Vc1 of the control voltage Vc. In response to the control clock signal CLK, the first switch sw1a is turned on, the third switch sw1b is turned off, and the second switch sw2a and the fourth switch sw2b are turned on for a predetermined time? T. Off. Accordingly, current is supplied to the loop filters 25A and 25B for a predetermined time DELTA t.

In addition, the control circuit 231A inputs the data DATA to lower the control voltage Vc when the later state value Vc2 of the control voltage Vc is smaller than the initial state value Vc1 of the control voltage Vc. And in response to the control clock signal CLK, the first switch sw1a is turned off and the third switch sw1b is turned on for a predetermined time? T, and the second switch sw2a and the fourth switch sw2b are turned on. Off. As a result, current is discharged from the loop filters 25A and 25B for a predetermined time DELTA t.

After the predetermined time [Delta] t, the control circuit 231A turns off the first switch sw1a and the third switch sw1b and turns on the second switch sw2a and the fourth switch sw2b.

The reason why the second switch sw2a and the fourth switch sw2b are turned off for a predetermined time DELTA t, that is, during the operation period of the fast frequency lock control circuit 23B, is because This is to reduce power consumption by preventing the phase detector 21, the voltage controlled oscillator 27, and the divider 29 from being operated other than the 23B) and the loop filters 25A and 25B.

As described above, the high-speed frequency lock control circuit 23B according to the second embodiment of the present invention has only the case where the later state value Vc2 of the control voltage Vc is larger than the initial state value Vc1 of the control voltage Vc. In addition, there is an advantage that can be applied even when the later state value Vc2 of the control voltage Vc is smaller than the initial state value Vc1 of the control voltage Vc.

On the other hand, the input data DATA is preferably the same data as the frequency division ratio N of the frequency divider 29 shown in FIG. 2 as in the first embodiment, and the control clock signal CLK is shown in FIG. It is preferable that it is the same signal as the reference clock signal fr. However, any data applied externally may be used as the input data DATA, and another arbitrary clock signal may be used as the control clock signal CLK.

In addition, the control circuit 231A may be implemented using a lock detection counter provided in the phase locked loop circuit, and the first constant current source I1 and the second constant current source I2 may be provided in the phase detector 21. It can be implemented using.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the phase-locked loop circuit according to the present invention has the advantage of reducing the frequency lock time and improving the characteristics by providing the fast frequency lock control circuit.

Claims (15)

A phase detector for detecting a phase difference by comparing a phase of a reference clock signal and a feedback clock signal; Loop filter; Disconnect power between the phase detector and the loop filter at the initial power on and supply constant current to or discharge from the loop filter for a predetermined time, and then connect the phase detector and the loop filter. A high speed frequency lock control circuit; A voltage controlled oscillator generating an output clock signal and varying a frequency of the output clock signal in response to an output voltage of the loop filter; And And a divider which divides the output clock signal at a predetermined division rate and provides a divided clock signal as the feedback clock signal. The method of claim 1, wherein the fast frequency lock control circuit, A constant current source having one end connected to the first reference voltage; A first switch connected between the other end of the constant current source and the loop filter; A second switch connected between the phase detector and the loop filter; And Control to turn on the first switch and turn off the second switch during the predetermined time in response to an input data and a control clock signal; turn off the first switch and turn on the second switch after the predetermined time. A phase locked loop circuit comprising a circuit. 3. The phase-lock loop of claim 2, wherein the input data is data equal to a frequency division ratio of the frequency divider. The phase locked loop circuit of claim 2, wherein the control clock signal is the same signal as the reference clock signal. 3. The phase locked loop circuit of claim 2, wherein the control circuit is implemented using a lock detection counter provided in the phase locked loop circuit. The phase locked loop circuit of claim 2, wherein the constant current source is implemented by using a charge pump provided in the phase detector. The method of claim 1, wherein the fast frequency lock control circuit, A first constant current source having one end connected to the first reference voltage; A first switch connected between the other end of the first constant current source and the loop filter; A second switch connected between the phase detector and the loop filter; A second constant current source having one end connected to the second reference voltage; A third switch connected between the other end of the second constant current source and the loop filter; A fourth switch connected between the loop filter and the voltage controlled oscillator; And In response to an input data and a control clock signal, one of the first switch and the third switch is turned on for a predetermined time, the second switch and the fourth switch are turned off, and after the predetermined time And a control circuit for turning off the switch and the third switch and turning on the second switch and the fourth switch. 8. The phase-lock loop of claim 7, wherein the input data is the same data as the frequency division ratio of the frequency divider. The phase locked loop circuit of claim 7, wherein the control clock signal is the same signal as the reference clock signal. 8. The phase locked loop circuit of claim 7, wherein the control circuit is implemented using a lock detection counter provided in the phase locked loop circuit. 8. The phase locked loop circuit as claimed in claim 7, wherein the first constant current source and the second constant current source are implemented using a charge pump provided in the phase detector. A phase detector for detecting a phase difference by comparing a phase of a reference clock signal and a feedback clock signal, a loop filter, an output clock signal, and a voltage controlled oscillator varying the frequency of the output clock signal in response to an output voltage of the loop filter; And a frequency divider for dividing the output clock signal at a predetermined frequency division ratio to provide a divided clock signal as the feedback clock signal, wherein the frequency lock time of the phase locked loop circuit is reduced. Disconnecting the phase detector and the loop filter at an initial stage of power-on of the phase-locked loop circuit and supplying or discharging a constant current to the loop filter for a predetermined time; And Connecting said phase detector and said loop filter after said predetermined time. The method of claim 12, wherein supplying the constant current to the loop filter, Generating the constant current; And In response to an input data and a control clock signal, connecting a connection between said constant current path and said loop filter during said predetermined time and disconnecting a connection between said phase detector and said loop filter. A method of reducing the frequency lock time of a synchronous loop circuit. 15. The method of claim 13, wherein the input data is data equal to the frequency division ratio of the divider. The method of claim 13, wherein the control clock signal is the same signal as the reference clock signal.