JPH11274922A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed phase synchronization locking, with respect to a phase locked loop(PLL) that synchronizes the phase of the output signal of a voltage controlled oscillator with the phase of an input signal. SOLUTION: A phase comparator 5 compares the phase of an input signal with the phase of a frequency dividing output signal which results from frequency-dividing the output of a voltage-controlled oscillator 1 with a frequency divider 6, and an output signal from the phase comparator is used for the control voltage of the voltage-controlled oscillator 1 in the phase-locked loop. The phase-locked loop circuit is provided with a lock control section 8 that controls 1st and 2nd changeover circuits 2, 3 in such a way that whether or not a frequency of an input signal is higher or lower than the center frequency is discriminated in the locking, a control voltage VCw with a lower limit frequency is selected when it is higher, or a control voltage VCh with a higher limit frequency is selected when it is lower, and the selected control voltage is given to the voltage-controlled oscillation 1 in place of the control voltage from the loop filter 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop having improved stability. Phase locked loop (PLL; Phase
Look Loop) includes a voltage controlled oscillator and a phase comparator, and controls the output signal phase of the voltage controlled oscillator to be synchronized with the input signal phase. It is desired to shorten the pull-in time of the phase synchronization circuit.

[0002]

2. Description of the Related Art FIG. 7 is an explanatory diagram of a conventional phase locked loop circuit, in which 51 is a voltage controlled oscillator (VCO), 52 is a switching circuit, 53 is a loop filter (LPF) having a small time constant,
54 is a loop filter (LPF) having a large time constant, 55
Is a phase comparator, 56 is a frequency divider, and 57 is a synchronization detector.

The output signal of the voltage controlled oscillator 51 is divided by a frequency divider 5
6, the phase of the divided output signal is compared with the phase of the input signal by a phase comparator 55, and the phase comparison output signal is passed through a loop filter 53 having a small time constant or a loop filter 54 having a large time constant. Thus, the output signal phase of the voltage controlled oscillator 51 is controlled so as to synchronize the frequency-divided output signal phase with the input signal phase.

A synchronization detecting section 57 determines whether or not a phase lock-in state has occurred based on the phase comparison output signal of the phase comparator 55 and the like, and selects a loop filter 53 having a small time constant during the phase lock-in operation. When the switching circuit 52 is controlled to perform the phase synchronization pull-in state, the switching circuit 52 is controlled to select the loop filter 54 having a large time constant, and the phase synchronization of the phase synchronization circuit (PLL) is performed. It is intended to speed up the pull-in and to stabilize the operation in the phase-locked pull-in state.

However, the free-running frequency of the voltage-controlled oscillator 51 when starting the phase lock pull-in is generally the upper limit frequency or the lower limit frequency of the operating range, and the free-running frequency and the input signal frequency are different. In the case of approximation, since the phase difference is small and the free-running frequency is not stabilized, the phase comparison output signal of the phase comparator 55 has a small value and fluctuates. Even if the filter 53 is connected, it is difficult to reduce the time required for pulling in the phase synchronization.

Therefore, a configuration shown in FIG. 8 has been proposed. In the figure, 61 is a voltage controlled oscillator (VCO),
62 is a switching circuit, 63 is a control voltage forming unit including a loop filter, 64 is a triangular wave generator, 65 is a phase comparator, 66
Is a frequency divider, 67 is a synchronization detection unit, and 68 is a storage unit.

In the phase lock-in state, the switching circuit 62 is switched to the state shown in the drawing, and the phase of the frequency-divided output signal of the frequency divider 66 and the input signal are compared by the phase comparator 65. The output signal is used as the control voltage of the voltage controlled oscillator 61 via the control voltage forming unit 63 including the loop filter. The control voltage at that time is sequentially updated and stored in the storage unit 68.

When the input signal is interrupted, the phase comparison output signal of the phase comparator 65 indicates that the phase comparison output signal has a large phase difference and fluctuates. Control is performed so as to switch from the control voltage forming section 63 to the triangular wave generator 64. Thereby,
The triangular wave control voltage is input to the voltage control oscillator 61, and the output signal frequency is scanned according to the triangular wave control voltage.

Therefore, when the input signal is restored and input, the phase of the input signal is compared with the phase of the frequency-divided output signal of the frequency divider 66 (which changes according to the triangular wave control signal) by the phase comparator 65. The synchronization detector 67 detects the phase comparison output signal when the phases match, switches the switching circuit 62 to the control voltage forming unit 63, and sets the control voltage stored in the storage unit 68 as the initial value. The voltage is input to the forming unit 63, and the control voltage according to the initial value is
To shift from the initial value to the phase lock-in state.

FIG. 9 is an explanatory diagram of the triangular wave control voltage for pull-in. In FIG.
A triangular wave control voltage that changes in a triangular wave form between the maximum voltage and the minimum voltage VCmin with a period Ta is generated.
When the phase is out of phase due to input signal disconnection or the like, the switching circuit 6
2 to the voltage-controlled oscillator 61. For example, if the triangular wave control voltage is input to the voltage-controlled oscillator 61 before the time t1 due to the input signal disconnection and the input signal is restored and input to the phase comparator 65 at the time t1, then the time At t1, the triangular wave control voltage is changing toward the minimum voltage VCmin,
Next, the voltage changes from the minimum voltage VCmin to the maximum voltage VCmax.

Then, based on the phase comparison output signal when the input signal phase and the frequency-divided output signal phase substantially coincide with each other, the synchronization detecting section 67 detects the phase synchronization pull-in, and the triangular wave generator 64
The switching circuit 62 is switched to the control voltage forming unit 63 side.
For example, when the rate of change (phase difference change rate) of the phase comparison output signal becomes substantially zero, the synchronization detecting unit 67 can be configured to determine that the phase synchronization has been lost and the phase synchronization has been pulled in.

The switching circuit 62 is switched to the control voltage forming section 63, and the initial value from the storage section 68 is input to the control voltage forming section 63, and the control voltage of the voltage controlled oscillator 61 is changed from the initial value according to the phase difference. Value. Then, at time t2, the rate of change of the phase comparison output signal becomes substantially zero, the control voltage corresponding thereto becomes stable, and the phase lock-in state is established.

When the rate of change of the phase comparison output signal increases at time t3 due to an input signal interruption or the like, the synchronization detecting section 67
Determines that the phase is out of synchronization, controls the switching circuit 62,
The control voltage generator 63 switches to the triangular wave generator 64. Thereby, the triangular wave control voltage from the triangular wave generator 64 is input to the voltage controlled oscillator 61, and the output signal phase of the voltage controlled oscillator 61 changes according to the triangular wave control voltage.

[0014]

In the prior art configuration for switching the time constant of a loop filter, for example, as shown in FIG. 7, a small time constant is applied to the phase difference between the input signal and the frequency-divided output signal at the start of phase synchronization pull-in. By using a loop filter, the output signal phase of the voltage controlled oscillator 51 is controlled at a high speed. However, when the frequency difference between the input signal and the frequency-divided output signal at the start of the phase lock pull-in is small, there is a problem that the time required to shift to the phase lock pull-in state becomes long.

The configuration for inputting the triangular wave control voltage shown in FIG. 8 forcibly changes the control voltage of the voltage controlled oscillator 61 into a triangular wave shape at the start of phase lock pull-in.
The cycle Ta of the triangular wave control voltage is sufficiently longer than the cycle of the input signal. Therefore, the time required from the start of the phase lock pull-in to the phase lock pull-in state is the worst case in which the period Ta is close to one cycle Ta of the triangular wave control voltage. There are issues that need to be addressed. SUMMARY OF THE INVENTION It is an object of the present invention to increase the speed of phase locking by a relatively simple configuration.

[0016]

According to the present invention, there is provided a phase locked loop circuit comprising: (1) an input signal phase and a voltage controlled oscillator (VCO) 1;
Is compared by a phase comparator 5 with a signal phase obtained by dividing the output signal by the frequency divider 6, and a comparison output signal of the phase comparator 5 is passed through a loop filter (LPF) 4 to a control voltage of the voltage controlled oscillator 1. It is determined whether the frequency of the input signal is higher or lower than the center frequency. If the frequency is higher, the control voltage VCw of the lower limit frequency for pull-in is selected. Control voltage VCh
And a pull-in control unit 8 which switches the selected control voltage for pull-in to the control voltage via the loop filter 4 and inputs the voltage to the voltage-controlled oscillator 1 at the time of synchronous pull-in.

(2) The pull-in control unit 8 switches the control voltage VCh of the upper limit frequency or the control voltage VCw of the lower frequency selected for pull-in for a certain period of time during synchronization pull-in, and inputs the voltage to the voltage-controlled oscillator 1. Can be provided.

(3) The pull-in control section 8 supplies the voltage-controlled oscillator 1 with the control voltage VC of the center frequency at the start of the synchronization pull-in.
c, a first counter that counts a high-level (or low-level) period of the input signal using the output signal of the voltage-controlled oscillator as a clock signal, and a frequency divider 6 that divides the output signal of the voltage-controlled oscillator. The second counter that counts the high-level (or low-level) period of the frequency-divided output signal and the count values of the first and second counters are compared, and the input signal frequency is higher or lower than the center frequency. And a frequency determination unit that determines whether the frequency is low.

(4) A phase comparison window within a predetermined range is formed from the rising phase or the falling phase of the input signal, and when the rising phase or the falling phase of the divided output signal exists in the phase comparison window. It is possible to include a synchronization detection control unit 7 that determines that synchronization has been pulled in and performs control to input a control voltage via the loop filter 4 to the voltage controlled oscillator 1.

(5) Under the control of the pull-in control unit 8 or the synchronization detection control unit 7, the first control voltage is switched between the control voltage via the loop filter 4 and the control voltage at the time of pull-in and input to the voltage controlled oscillator 1. The first switching circuit 2 switches the central frequency control voltage VCc, the upper limit frequency control voltage VCh, and the lower limit frequency control voltage VCw to the voltage controlled oscillator 1 under the control of the switching circuit 2 and the pull-in control unit 8. And a second switching circuit 3 in addition to the above.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of an embodiment of the present invention, wherein 1 is a voltage controlled oscillator (VCO), 2, 3 are first and second switching circuits, and 4 is a loop filter (LPF). ),
5 is a phase comparator, 6 is a frequency divider, 7 is a synchronization detection control unit, 8
Is the pull-in control unit, VCc is the control voltage of the center frequency, VC
h indicates the control voltage of the upper limit frequency, and VCw indicates the control voltage of the lower limit frequency.

For example, if the input signal frequency is 8 kHz,
Assuming that the oscillation frequency of the voltage controlled oscillator 1 is 5 MHz, the frequency divider 6 has a frequency division ratio of 1/625. If the input signal and the frequency-divided output signal are rectangular wave signals, the phase comparator 5 can be constituted by a logic circuit including a NAND circuit and a flip-flop. When the phase of the divided output signal is delayed with respect to the input signal phase, for example, the output signal phase of the voltage controlled oscillator 1 is controlled to be advanced by passing a high-level phase delay detection signal through the loop filter 4. When the voltage is increased, and conversely, when the divided output signal phase is advanced with respect to the input signal phase, the output signal phase of the voltage controlled oscillator 1 is reduced by passing the low-level phase advance detection signal through the loop filter 4. Lower the control voltage to delay.

The synchronization detection control unit 7 receives the input signal and the frequency-divided output signal of the frequency divider 6 and forms a phase comparison window based on the rising or falling phase of the input signal. When the rising phase or the falling phase of the frequency-divided output signal exists in the window, it is possible to use a configuration in which it is determined that the synchronization is pulled in. Further, similarly to the conventional example, it is also possible to adopt a configuration in which the phase lock-in state is detected when the rate of change of the phase comparison output signal of the phase comparator 5 becomes small.

The pull-in controller 8 counts a high level period or a low level period of the input signal using the output signal of the voltage controlled oscillator 1 as a clock signal.
By counting the double-level period or the low-level period of the frequency-divided output signal, comparing the respective count values, and inputting the control voltage VCc of the center frequency to the voltage-controlled oscillator 1 at the start of synchronization pull-in. Is determined to be higher or lower than the center frequency, and the second switching circuit 3 is controlled. It is also possible to apply a configuration in which it is determined whether the frequency of the input signal is higher or lower than the center frequency by comparing it with another reference value.

At the start of the synchronization pull-in when the power is turned on or when the input signal is restored, the pull control unit 8 controls the switching of the first switching circuit 2 from the loop filter 4 side to the second switching circuit 3 side, Further, the second switching circuit 3 controls the control voltage V at the center frequency.
Switching control is performed so as to select Cc. Thereby, the control voltage VCc of the center frequency is input to the voltage controlled oscillator 1. For example, if the control voltage of the voltage controlled oscillator 1 is 0 to
Assuming that the voltage can be changed in the range of 5 V, a control voltage of 2.5 V is selected and input to the voltage controlled oscillator 1.

Therefore, the output signal of the voltage controlled oscillator 1 is used as a clock signal (for example, 5 MHz), the high level period of the input signal (for example, a rectangular wave signal of 8 kHz ± Δf) is counted, and the divided output signal (for example, For example, 8 kHz
By counting the high-level period of the square wave signal) and comparing the count values, it is possible to determine whether the input signal is higher or lower than the center frequency. In this case, it is not necessary to set the center frequency accurately. Therefore, the frequency determination unit that determines whether the input signal frequency is higher or lower than the center frequency can be realized with a relatively simple configuration.

As described above, the pull-in control unit 8 controls the second switching circuit 3 to control the control voltage VCc of the center frequency for determining whether the input signal frequency at the start of the synchronization pull-in is higher or lower than the center frequency. When the input signal frequency is higher than the center frequency, the control voltage VCw of the lower limit frequency is selected when the input signal frequency is higher than the center frequency, and when the input signal frequency is lower than the center frequency, the control voltage VCh of the upper limit frequency is changed. The second switching circuit 3 is controlled so as to make a selection.

Thereby, the voltage controlled oscillator 1 is controlled so that the difference between the frequency of the divided output signal and the frequency of the input signal is increased.
The first switching circuit 2 is controlled after a predetermined time period by a timer or the like of the pull-in control unit 8 or by a synchronization pull-in determination by the phase synchronization detection control unit 7.
Side to perform steady-state phase synchronization control. Note that the first and second switching circuits 2 and 3 can be configured using switching elements such as field effect transistors.

FIG. 2 is an explanatory view of a main part of the pull-in control unit according to the embodiment of the present invention, wherein 11 and 12 are first and second counters, 13 is a frequency judgment unit, 14 is a switching control unit, and 15 is The pull-in start determination control unit 16 is a switching circuit. The switching circuit 16 includes the first and second switching circuits 2 and 3 in FIG.
And a switching element such as a transistor. The voltage control oscillator VCO has a control voltage via a loop filter LPF, a center frequency reference voltage VCc, an upper limit frequency control voltage VCh, and a lower limit frequency. In this case, the switching control unit 14 switches and inputs the control voltage VCw.

The pull-in start determination control section 15 determines the start of synchronous pull-in based on a power-on signal or an input signal Fin, and inputs a control signal to the switching control section 14. As a result, the switching control unit 14 switches the switching circuit 16 from the state shown in the figure to the control voltage VCc at the center frequency and inputs the same to the voltage controlled oscillator VCO. For example, the control voltage V at the upper limit frequency
Ch is 4.5 V, and the control voltage VCw of the lower limit frequency is 0.5
Assuming that the control voltage is V, the control voltage of the center frequency should be 2.5 V.

The output signal Fc of the voltage controlled oscillator VCO is input as a clock signal to the clock terminal CK of the first and second counters 11 and 12, and the input signal Fin is input to the enable terminal E of the first counter 11. The frequency division output signal Fdv is input to the enable terminal E of the second counter 12, and the high level period of the input signal Fin and the frequency division output signal Fdv is counted up as a count enable period. The low level period can be counted up as a count enable period.

The frequency determination unit 13 determines whether the input signal Fin is higher or lower than the center frequency. At the start of the pull-in, the switching circuit 16 inputs the control voltage VCc of the center frequency to the voltage controlled oscillator VCO. Therefore, the divided output signal FdV also corresponds to the center frequency,
When the high level period is a count enable period, when the count value of the first counter 11 is larger than the count value of the second counter 12, the frequency of the input signal Fin at the start of the pull-in is higher than the center frequency. If the count value of the first counter 11 is smaller than the count value of the second counter 12,
The frequency of the input signal Fin can be determined to be lower than the center frequency.

The determination result of the frequency of the input signal Fin is input to the switching control unit 14. When the frequency of the input signal Fin is higher than the center frequency, the switching control unit 14 controls the switching circuit 16 to select the control voltage VCw having the lower limit frequency. Thereby, the oscillation frequency of the voltage controlled oscillator VCO changes rapidly from the center frequency to the lower limit frequency. Conversely, when the frequency of the input signal Fin is lower than the center frequency, the switching circuit 16 is controlled so as to select the control voltage VCh of the upper limit frequency. Thereby, the oscillation frequency of the voltage controlled oscillator VCO changes rapidly from the center frequency toward the upper limit frequency.

A timer is provided in the switching control unit 14 to control the control voltage VCh of the upper limit frequency or the control voltage VCw of the lower limit frequency.
After the switching circuit 16 is controlled so as to select, the switching circuit 16 is controlled such that the control voltage via the loop filter LPF is input to the voltage controlled oscillator VCO after a predetermined time. That is, when the frequency of the input signal Fin is higher than the center frequency, by controlling the oscillation frequency of the voltage controlled oscillator VCO to be the lower limit frequency, the frequency of the input signal Fin and the frequency of the divided output signal Fdv can be reduced. And when the frequency of the input signal Fin is lower than the center frequency, the oscillation frequency of the voltage-controlled oscillator VCO is controlled to be the upper limit frequency, so that the frequency of the input signal Fin and the divided output The difference from the frequency of the signal Fdv is increased.

By increasing the frequency difference in this way, the phase of the frequency-divided output signal Fdv can be rapidly pulled into the phase of the input signal Fin. As described above, after the control voltage VCh of the upper limit frequency or the control voltage VCw of the lower limit frequency is input to the voltage controlled oscillator VCO for a certain period of time by a timer or the like, the control voltage via the loop filter LPF is input to the voltage controlled oscillation VCO. Alternatively, the synchronization detection control unit 7 (see FIG. 1) detects that the lock-in state has occurred, and switches to input to the control voltage / voltage controlled oscillator VCO via the loop filter LPF.

FIG. 3 is an explanatory view of a main part of the synchronization detection control unit according to the embodiment of the present invention.
2 is an AND circuit constituting a phase comparison circuit, 23 is a switching control circuit, 24, 25, 27 are delay circuits (DL), 26,
28 is a flip-flop. The input signal Fin is input to the delay circuit 24 of the phase comparison window forming circuit 21 and the set terminal S of the flip-flop 24, and the frequency-divided output signal Fdv is input to the delay circuit 27 and the set terminal S of the flip-flop 28.

Since the input signal Fin via the delay circuits 24 and 25 is input to the reset terminal R of the flip-flop 26, a phase corresponding to the delay time by the delay circuits 24 and 25 is output from the output terminal Q of the flip-flop 26. The signal of the comparison window is output and input to the AND circuit 22. A delay circuit 27 is connected to the reset terminal R of the flip-flop 28.
, The signal corresponding to the delay time of the delay circuit 27 is output from the output terminal Q of the flip-flop 28, and the AND circuit 2
2 is input. That is, a signal of the rising phase of the frequency-divided output signal Fdv is output from the output terminal Q of the flip-flop 28, and when this signal is output in the phase comparison window, the output signal is "1". And the synchronization pull-in detection signal is output.

The switching control circuit 23 controls the first switching circuit 2 in FIG. 1. The switching control circuit 23 controls the first switching circuit 2 according to the synchronization pull-in detection signal from the AND circuit 22. The normal phase locked loop is formed by switching from the side to the loop filter 4 side.

FIGS. 4A and 4B are diagrams for explaining the operation of the synchronization detection control unit. FIG. 4A shows the input signal Fin, FIG. 4B shows the signal delayed by the delay circuit 24 having a delay time τ, and FIG.
(D) is an output signal of the flip-flop 26 set at the rising edge of the input signal Fin and reset by the signal from the delay circuit 25, that is, a signal indicating the phase comparison window. (E) is a divided output signal Fdv, (f) is a signal delayed by the delay circuit 27 having a delay time τ, (g) is set at the rising edge of the divided output signal Fdv, and is reset by a signal from the delay circuit 27. 5 shows the output signal of the flip-flop 28 that has been set.

That is, the phase comparison window forming circuit 21
A signal from the output terminal Q of the flip-flop 28, which forms a signal of the phase comparison window shown in FIG. 4D and corresponds to a rising differential output signal of the divided output signal Fdv, is shown in FIG.
When this signal is output in the phase comparison window, it can be determined that the synchronization is established. Note that a case where a phase comparison window is formed based on the rising phase of the input signal Fin, and it is determined whether or not the rising phase of the divided output signal Fdv falls within the phase comparison window to detect synchronization pull-in, Forming a phase comparison window based on the falling phase of the input signal Fin, determining whether the falling phase of the frequency-divided output signal Fdv falls within the phase comparison window, and detecting synchronization pull-in. It is also possible.

FIG. 5 is a diagram for explaining the operation when the power is turned on.
(A) shows a conventional example, (B) shows measured data in the embodiment of the present invention, (a) and (a) in (A) and (B) are input signals, and (b) is a divided output. A signal, (c) indicates a control voltage, and (d) indicates a power supply voltage. The input signal frequency is 8 kHz + 110 ppm, and this input signal frequency is shown in the case where it is close to the frequency-divided output signal frequency of the free-running frequency near the upper limit frequency of the voltage controlled oscillator 1.

In the conventional example of FIG. 5A, at time t0
As shown in (d), when the power supply voltage rises, the input signal is input to the phase comparator first, and the divided output signal is input to the phase comparator after the power supply voltage rises. In this state, the phase comparator determines that the phase of the frequency-divided output signal input later is delayed with respect to the input signal input earlier, and outputs a high-level delayed phase detection signal. . Therefore, the control voltage of the voltage controlled oscillator increases as shown in FIG.

In this case, the speed at which the output signal phase (divided output signal phase) of the voltage controlled oscillator advances corresponds to the difference between the input signal frequency and the frequency obtained by dividing the signal of the free running frequency of the voltage controlled oscillator. Becomes Therefore, even when the input signal phase shown in (a) immediately after the rise of the power supply voltage and the divided output signal phase shown in (b) are shifted by about 180 degrees, the time t
After the power supply voltage was raised to 0, it took ta ≒ 7.4 seconds to enter the phase synchronization pull-in state.

On the other hand, in the embodiment of the present invention shown in FIG. 2B, as in the conventional example shown in FIG.
When the power supply voltage rises to 0 as shown in (d), the phase comparator outputs a high-level phase delay detection signal as in the case of (A) described above, and the control voltage of the voltage-controlled oscillator ( It becomes higher as shown in c). At this time, for example, in FIG. 2, when a power-on signal is input to the pull-in start determination control unit 15, it is determined that the pull-in is to start, and the switching control unit 14 is controlled. The switching control unit 14 controls the switching circuit 16 to select the control voltage VCc of the center frequency and to input the control voltage VCc to the voltage controlled oscillator VCO.

As described above, it is determined whether the frequency of the input signal Fin is higher or lower than the center frequency. In this case, the frequency is 8 kHz + 110 ppm, which is higher than the center frequency. In accordance with the control voltage VC of the lower limit frequency by the switching control unit 14.
w is selected and input to the voltage controlled oscillator VCO. That is, the control voltage VCw of the lower limit frequency indicated by the mark * in (c) of FIG. 5B is input to the voltage controlled oscillator VCO for a certain period of time, and the frequency of the input signal Fin and the divided output signal Fd
The difference from the frequency of v becomes large, and the synchronization pull-in is tb ≒ 4
Seconds. That is, the time required for synchronization pull-in can be reduced by about 3.4 seconds as compared with the conventional example.

FIG. 6 is an explanatory diagram of the operation at the time of restoration from the interruption of the input signal. FIG. 6 shows actual measurement data when the frequency of the input signal restored from the interruption of the input signal is 8 kHz-90 ppm which is close to the lower limit frequency of the pull-in range. A) is a conventional example,
(B) shows an embodiment of the present invention. (A), (B)
(A) is an input signal, (b) is a divided output signal,
(C) shows the control voltage, and the power supply voltage (d) in FIG.
Is omitted.

In the conventional example of (A), as shown in (a) at time t0, when the input signal from the disconnected state is restored and input, the phase comparator outputs the divided output signal. Since the input signal is input first and the recovered input signal is input later,
It is determined that the phase of the divided output signal is ahead of the phase of the input signal. In this case, although the phase of the divided output signal and the phase of the input signal shown in (b) have a difference of about 180 degrees, the input signal frequency and the divided output signal frequency are almost similar. , The phase comparison output signal is as shown in (c), and the synchronization pull-in is tc ≒ 7.2 seconds.

On the other hand, in the embodiment of the present invention shown in (B), at time t0, the input signal is restored from the disconnected state as shown in (a) as in the case of the conventional example. In this case, it is determined whether the frequency of the input signal Fin is higher or lower than the center frequency. Since this case is lower, the control voltage VCh of the upper limit frequency is input to the voltage controlled oscillator VCO. That is, the control voltage VCh of the upper limit frequency indicated by the mark * in (c) of (B) is input to the voltage controlled oscillator VCO for a certain period of time, and the oscillation frequency of the voltage controlled oscillator VCO changes so as to be the upper limit frequency. The difference from the frequency of Fin increases. As a result, the pull-in speed was increased, and a synchronous pull-in state was established at td ≒ 2.8 seconds. That is, the time required for synchronization pull-in at the time of restoration of the input signal can be reduced by about 4.4 seconds as compared with the conventional example.

The present invention is not limited to the above-described embodiments, but can be variously added and changed. For example, the determination of the level relative to the center frequency of the input signal can be performed by a simple configuration. It is also possible to adopt a configuration in which another oscillator having an oscillation frequency substantially at the center frequency is provided.

[0050]

As described above, according to the present invention, the input signal phase is compared with the signal phase obtained by dividing the output signal of the voltage controlled oscillator 1 by the frequency divider 6 by the phase comparator 5, and this phase comparison is performed. A phase-locked loop that uses the comparison output signal of the input device 5 as a control voltage of the voltage controlled oscillator 1 via the loop filter 4 and determines whether the frequency of the input signal is higher or lower than the center frequency. The control voltage VCw of the lower limit frequency is selected, and if it is lower, the control voltage VCh of the upper limit frequency for pull-in is selected. It is provided with a pull-in control unit 8 for inputting to the control oscillator 1, and increases the difference between the input signal frequency and the frequency-divided output signal frequency at the start of synchronous pull-in such as when power is turned on or input signal is restored. By, there is an advantage that it is possible to speed up the pull-in.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a main part of a pull-in control unit according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of main parts of a synchronization detection control unit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation of a synchronization detection control unit.

FIG. 5 is an explanatory diagram of an operation when power is turned on.

FIG. 6 is an explanatory diagram of an operation at the time of recovery from a disconnection of an input signal.

FIG. 7 is an explanatory diagram of a conventional phase locked loop circuit.

FIG. 8 is a diagram illustrating a conventional phase locked loop circuit using a pull-in control voltage.

FIG. 9 is an explanatory diagram of a pull-in triangular wave control voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator (VCO) 2 1st switching circuit 3 2nd switching circuit 4 Loop filter (LPF) 5 Phase comparator 6 Divider 7 Synchronous detection control part 8 Retraction control part

Claims (5)

[Claims] 1. A phase comparator compares an input signal phase with a signal phase obtained by dividing an output signal of a voltage controlled oscillator by a frequency divider, and compares a comparison output signal of the phase comparator with the voltage through a loop filter. In the phase-locked loop as the control voltage of the control oscillator, it is determined whether the frequency of the input signal is higher or lower than the center frequency, and if it is higher, the control voltage of the lower limit frequency for pull-in is selected. A pull-in control unit that selects a control voltage of an upper limit frequency for the pull-in, switches the selected pull-in control voltage to a control voltage through the loop filter, and inputs the voltage to the voltage-controlled oscillator at the time of pull-in synchronously. And a phase synchronization circuit. 2. The control device according to claim 1, wherein the pull-in control unit switches the control voltage of the upper-limit frequency or the control voltage of the lower-limit frequency selected at the time of synchronization pull-in for a predetermined time and inputs the voltage to the voltage-controlled oscillator. 2. The phase synchronization circuit according to claim 1, further comprising: 3. The pull-in control unit inputs a control voltage having a center frequency to the voltage-controlled oscillator at the start of synchronization pull-in, and sets an output signal of the voltage-controlled oscillator as a clock signal to a high level of the input signal (or A first counter that counts a period of a low level, and a second counter that counts a high level (or low level) period of a frequency-divided output signal obtained by dividing the output signal of the voltage controlled oscillator by the frequency divider. 3. The apparatus according to claim 1, further comprising: a counter; and a frequency determination unit configured to compare the count values of the first and second counters to determine whether the input signal frequency is higher or lower than a center frequency. Phase synchronization circuit. 4. A phase comparison window in a predetermined range is formed from a rising phase or a falling phase of the input signal, and when a rising phase or a falling phase of the divided output signal exists in the phase comparison window. 2. The phase locked loop circuit according to claim 1, further comprising: a synchronization detection control unit that determines that synchronization has been pulled in and performs control for inputting a control voltage via the loop filter to the voltage controlled oscillator. 5. A first switching circuit that switches between a control voltage via the loop filter and a control voltage at the time of synchronization pull-in and inputs the voltage to the voltage-controlled oscillator under the control of the pull-in control unit or the synchronization detection control unit. A second switching to be applied to the first switching circuit by switching the control voltage of the center frequency, the control voltage of the upper limit frequency, and the control voltage of the lower limit frequency to the voltage controlled oscillator under the control of the pull-in control unit. 5. The phase-locked loop according to claim 1, further comprising a circuit.