JP7472561B2 - Oscillator Circuit - Google Patents

Description

The present invention relates to an oscillator circuit that performs high-speed frequency lock-up.

In radio devices that communicate by switching between multiple frequency channels, there is a demand for faster lock-up times in PLL circuits for frequency synthesizers. Generally, PLL circuits for frequency synthesizers use circuits that use charge pumps. However, in the case of PLL circuits that use charge pumps, there is a problem in that the capacitance of the loop filter capacitor prevents faster lock-up times.

Patent document 1 discloses a technique for accelerating PLL lockup by using a second charge pump to perform high-speed charging based on the results of comparing the current charging voltage with a reference voltage. Patent document 2 discloses a technique for accelerating PLL lockup by applying the difference voltage between the charge pump output voltage and the reference voltage to the output section of the charge pump.

Japanese Patent Application Laid-Open No. 11-27141 JP 2001-85996 A

In the circuits described in Patent Documents 1 and 2, it is necessary to set a reference voltage for each target frequency in advance, but since the relationship between the voltage and the oscillation frequency varies between components, adjustments may be required for each product in order to set the reference voltage with precision. In addition, since the relationship between the voltage and the oscillation frequency changes with temperature, it is difficult to always set an optimal reference voltage.

The present invention aims to provide an oscillator circuit that can achieve high-speed PLL lockup without the need to set a reference voltage for each target frequency.

The present invention provides an oscillator circuit comprising: a reference oscillator that outputs a reference signal; a PLL circuit that outputs a PLL control signal from a PLL control signal output unit; a first resistor connected to the PLL control signal output unit; a loop filter that integrates the PLL control signal to generate a control voltage signal; a voltage-controlled oscillator that generates a local signal based on the control voltage signal; and a buffer that applies the control voltage signal to the loop filter, the PLL circuit outputs the PLL control signal based on a comparison result between the reference signal and the local signal; and the buffer applies the control voltage signal to the connection between the first resistor and the first capacitor of the loop filter.

The present invention provides an oscillator circuit that can achieve high-speed PLL lockup without the need to set a reference voltage for each target frequency.

FIG. 1 is a block diagram showing an example of the configuration of an oscillator circuit according to the first embodiment. FIG. 2 is a block diagram for explaining the configuration of the PLL circuit. FIG. 3 is a diagram for explaining the operation of the oscillator circuit. FIG. 4 is an enlarged view of the vicinity of the switch OFF time in FIG. FIG. 5 is a block diagram showing an example of the configuration of an oscillator circuit according to the second embodiment. FIG. 6 is a diagram for explaining the operation of the oscillator circuit in the second embodiment. FIG. 7 is a block diagram showing a configuration example of an oscillator circuit according to the third embodiment. FIG. 8 is a diagram for explaining the operation of the oscillator circuit in the third embodiment. FIG. 9 is a block diagram showing an example in which the loop filter of the oscillator circuit in the first embodiment is replaced with another loop filter.

The following describes an embodiment of the present invention with reference to the drawings.

<Embodiment 1>
1 is a block diagram showing an example of the configuration of an oscillator circuit 100 according to this embodiment. The oscillator circuit 100 is an oscillator circuit that performs PLL (Phase Locked Loop) control using the oscillation frequency of a reference oscillator as a reference frequency, and controls the oscillation frequency of a voltage controlled oscillator by PLL control.

The oscillator circuit 100 includes a reference oscillator 12, a PLL circuit 14, a loop filter 16, a voltage controlled oscillator (VCO) 18, a buffer 20, a switch 22, and a second resistor 24. The loop filter 16 includes a first resistor 30, a first capacitor 32, and a second capacitor 34.

The reference oscillator 12 generates a reference signal Rs having a reference frequency of, for example, 19.2 MHz, and outputs it to the PLL circuit 14. The reference oscillator 12 is, for example, a temperature-compensated voltage-controlled crystal oscillator (VC-TCXO).

The PLL circuit 14 compares the reference signal Rs with the negative feedback signal Ns output from the VCO 18 in the loop, and outputs the comparison result as a PLL control signal. Specifically, the PLL circuit 14 appropriately divides the reference signal Rs and the negative feedback signal Ns, respectively, and compares their phases. Based on the comparison result, the PLL circuit 14 generates a control current pulse signal Ic, which is a PLL control signal for keeping the phase difference constant, and outputs it to the loop filter 16.

A specific example of the configuration of the PLL circuit 14 will be described with reference to FIG. 2. The PLL circuit 14 is, for example, a fractional frequency division PLL circuit (fractional-N type PLL circuit). The PLL circuit 14 includes a first frequency divider 40, a phase comparator 42, a second frequency divider 44, and a charge pump 46.

The first frequency divider 40 receives the local signal Ls output from the VCO 18 in the loop as a negative feedback signal Ns, divides the received negative feedback signal Ns by a division ratio of 1/N, and converts it into a negative feedback comparison signal NCs with a comparison frequency fn. For example, if the frequencies of the local signal Ls and the negative feedback signal Ns are 826.05 MHz and N=4130.25, the comparison frequency fn of the negative feedback comparison signal NCs is 200 kHz. The frequency divider 40 outputs the negative feedback comparison signal NCs to the phase comparator 42.

The second frequency divider 44 divides the reference signal Rs output from the reference oscillator 21 by a division ratio of 1/R and converts it into a reference comparison signal RCs with a comparison frequency fr. For example, if R=96, the comparison frequency fr of the reference comparison signal RCs is 200 kHz. The frequency divider 44 outputs the reference comparison signal RCs to the phase comparator 42.

The phase comparator 42 compares the comparison frequency fr of the reference comparison signal RCs with the comparison frequency fn of the negative feedback comparison signal NCs, and generates a phase difference pulse signal Ps of the comparison frequency fp.

Specifically, the phase comparator 42 compares the comparison frequency fr of the reference comparison signal RCs with the comparison frequency fn of the negative feedback comparison signal NCs, and adjusts the duty ratio of the phase difference pulse signal Ps to be smaller when the comparison frequency fn is higher than the comparison frequency fr. In addition, the phase comparator 42 adjusts the duty ratio of the phase difference pulse signal Ps to be larger when the comparison frequency fn is lower than the comparison frequency fr. The phase comparator 42 outputs the phase difference pulse signal Ps to the charge pump 46.

The phase comparator 42 also compares the phase of the reference comparison signal RCs and the negative feedback comparison signal NCs, and outputs a lock detect signal Ld. Specifically, the lock detect signal Ld is outputted as a Hi signal when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is outside a predetermined range, and as a Lo signal when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is within a predetermined range.

The charge pump 46 converts the phase difference pulse signal Ps into a control current pulse signal Ic and outputs it to the loop filter 16 .
The charge pump 46 functions as a PLL control signal output unit.

Returning to FIG. 1, the loop filter 16 converts the control current pulse signal Ic into a control voltage signal Vc and outputs it to the VCO 18 and the buffer 20. The loop filter 16 also removes unnecessary frequency components from the control current pulse signal Ic.

The VCO 18 generates and outputs a local signal Ls having a frequency of, for example, 826.05 MHz based on the control voltage signal Vc. The local signal Ls is input to the PLL circuit 14 as a negative feedback signal Ns. The buffer 20 outputs the control voltage signal Vc to the switch 22.

The switch 22 switches ON/OFF according to the lock detect signal Ld received from the PLL circuit 14. When the lock detect signal Ld is Hi, the switch 22 is ON, and when the lock detect signal Ld is Lo, the switch 22 is OFF. In other words, when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs compared by the PLL circuit 14 is outside a predetermined range, the switch 22 is ON, and when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is within a predetermined range, the switch 22 is OFF.

When the switch 22 is ON, the switch 22 applies the control voltage signal Vc received from the buffer 20 to the loop filter 16 via the second resistor 24. Specifically, the switch 22 applies the control voltage signal Vc to the connection between the first resistor 30 and the first capacitor 32 that constitute the loop filter 16 via the second resistor 24. This allows the control voltage signal Vc to be instantly applied to the first capacitor, thereby speeding up the operation of the charge pump.

For example, the first resistance value is 100 (Ω), the second resistance value is 10 (Ω), the capacitance value of the first capacitor is 4.7 (μf), and the capacitance value of the second capacitor is 0.1 (μf). Although not limited to these values, it is desirable that the first resistor has a sufficiently large resistance value compared to the second resistor. Furthermore, the second resistor may not be required. That is, the switch 22 may directly apply the control voltage signal Vc to the connection between the first resistor 30 and the first capacitor 32 that constitute the filter 16. It is also desirable that the first capacitor has a sufficiently large capacitance value compared to the second capacitor. The second capacitor may not be required.

The operation of the oscillator circuit 100 will be explained using Figure 3. Assume that the oscillation frequency of the local signal Ls is switched from f1 (MHz) to f2 (MHz). Figure 3(a) shows the ON/OFF operation of the switch 22, and Figure 3(b) shows the change in frequency of the local signal Ls output from the VCO 18. The solid line shows the change in frequency of the local signal Ls in this embodiment. For comparison, the dashed line shows the change in frequency of the local signal Ls when the control voltage signal Vc is not applied to the filter 16.

When the frequency switching operation of the local signal Ls starts at t0, the lock detect signal Ld output from the PLL circuit 14 goes Hi and the switch 22 turns ON. The PLL circuit 14 operates with the lock detect signal Ld kept Hi until the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs falls within a predetermined range, and when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs falls within the predetermined range at time t1, the lock detect signal Ld goes Lo and the switch 22 turns OFF. Thereafter, with the switch 22 in the OFF state, control is performed to further lock the phase between the reference comparison signal RCs and the negative feedback comparison signal NCs.

As shown in FIG. 3(b), by applying the control voltage signal Vc to the loop filter 16, the frequency of the local signal Ls can be changed more quickly compared to when the control voltage signal Vc is not applied, and therefore lockup can be accelerated.

Figure 4 is an enlarged view of the area around switch OFF time t1 in Figure 3. Until time t1, switch 22 is ON, so the frequency of local signal Ls changes at a steep slope, but after time t1, switch 22 turns OFF, so the frequency changes more gradually.

For comparison, the two-dot chain line shows the change in frequency when switch 22 is turned ON until the phase difference between reference comparison signal RCs and negative feedback comparison signal NCs completely disappears. As shown by the two-dot chain line, if switch 22 is turned ON until the phase difference between reference comparison signal RCs and negative feedback comparison signal NCs completely disappears, the frequency change is too sudden and the frequency change becomes excessive, and as a result, it takes a long time to lock up. For this reason, it is desirable to turn switch 22 OFF before the phase difference between reference comparison signal RCs and negative feedback comparison signal NCs completely disappears.

According to the oscillator circuit 100 of this embodiment, the PLL can be locked up at high speed by applying the control voltage signal Vc to the loop filter 16. In addition, there is no need to set a reference voltage for each target frequency. Furthermore, since the application of the control voltage signal Vc is stopped before the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is completely eliminated, the frequency is not changed excessively and the PLL can be locked up at high speed.

<Embodiment 2>
In the first embodiment, the switch 22 is turned OFF based on the lock detect signal Ld, which becomes Lo when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs falls within a predetermined range. In the second embodiment, however, the switch is turned OFF a predetermined time after the lock detect signal Ld becomes Lo.

The PLL circuit 14 is generally configured with an IC, in which case the Hi/Lo switching of the lock detect signal Ld is determined by the IC specifications. Therefore, there are cases where lockup can be speeded up by turning off the switch 22 a predetermined time after the lock detect signal Ld becomes Lo, rather than turning off the switch 22 immediately after the lock detect signal Ld becomes Lo.

Figure 5 shows an example of the configuration of an oscillator circuit 200 in this embodiment. The oscillator circuit 200 differs from the oscillator circuit 100 in Figure 1 in that a delay circuit 26 is added. The following will focus on the differences from the first embodiment. Configurations similar to those in the first embodiment are given the same reference numerals, and descriptions may be omitted.

The delay circuit 26 delays the lock detect signal Ld received from the PLL circuit 14 by a predetermined time and outputs it to the switch 22. FIG. 6 is a diagram showing the relationship between the operation of the switch 22 and the frequency of the local signal Ls, and is an enlarged diagram of the vicinity of the time when the switch 22 is turned OFF. The dotted line shows the change in the local signal Ls when the switch 22 is turned OFF at time t1 when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs falls within a predetermined range, and the solid line shows the change in the frequency of the local signal Ls when the switch 22 is turned OFF at time t12, which is a predetermined delay from time t1.

Compared to when the switch is turned off at time t1, when the switch is turned off at time t12, the PLL locks up faster. In this embodiment, compared to embodiment 1, the time when the switch 22 is turned off is delayed, so that the timing when the switch 22 is turned off can be optimized, and the PLL locks up faster. It is desirable to set the delay amount of the delay circuit 24 to an optimal amount depending on the timing when the lock detect signal Ld becomes Lo.

The oscillator circuit 200 of this embodiment is different from the oscillator circuit 100 described in the first embodiment in that it adds a configuration for delaying the lock detect signal Ld, making it possible to freely set the timing for ceasing to apply the control voltage signal Vc to the loop filter 16. Therefore, in addition to the effects described in the first embodiment, the oscillator circuit 200 of this embodiment has the effect of further speeding up the PLL lockup.

<Embodiment 3>
In the first and second embodiments, the switch 22 is turned OFF based on the lock detect signal Ld output from the PLL circuit 14, but in this embodiment, the switch 22 is switched ON/OFF based on the amount of change in the control voltage signal Vc.

Figure 7 shows an example of the configuration of an oscillator circuit 300 in this embodiment. The oscillator circuit 300 differs from the oscillator circuit 100 in Figure 1 in that a control voltage signal monitoring unit 28 is added, and the switch 22 is turned ON/OFF based on the output signal of the control voltage signal monitoring unit 28 instead of the lock detect signal Ld of the PLL 14. The following will focus on the differences from embodiment 1 or embodiment 2. The same reference numerals are used for the same configuration as embodiment 1 or embodiment 2, and the description may be omitted.

The control voltage signal monitoring unit 28 monitors the voltage value of the control voltage signal Vc received from the buffer 20 at predetermined time intervals, and switches the output between Hi and Lo depending on the amount of change in the control voltage signal Vc. Specifically, the control voltage signal monitoring unit 28 detects the voltage value of the control voltage signal Vc every 20 msec, monitors the amount of change in the control voltage signal Vc, and sets the output to Lo if the amount of change in the voltage value is less than or equal to a predetermined value three times in a row, and sets the output to Hi otherwise.

The interval at which the control voltage signal monitoring unit 28 monitors the voltage value of the control voltage signal Vc is not limited to 20 msec and may be set as appropriate. Furthermore, the method of determining the amount of change in the voltage value of the control voltage signal Vc is not limited to the above, and may be determined based on the average amount of change over multiple consecutive times, or based on the amount of change in the voltage value over three or fewer consecutive times or three or more consecutive times.

When setting the timing for turning off the switch 22 based on the lock detect signal Ld, the optimal setting value differs depending on the set frequency of the local signal Ls, so it is necessary to set it with a certain degree of leeway. In the method of this embodiment, which sets the timing for turning off the switch 22 based on the amount of change in the voltage value of the control voltage signal Vc, the timing for turning off the switch 22 can be set regardless of the set frequency of the local signal Ls, so a more suitable setting can be made.

Figure 8 shows the relationship between the operation of switch 22 and the frequency of local signal Ls, and is an enlarged view of the vicinity of the time when switch 22 is turned OFF. The solid line shows the change in frequency of local signal Ls when switch 22 is turned OFF at time t13 based on the output of control voltage signal monitor 28. For comparison, the dotted lines show the change in frequency of local signal Ls when the switch is turned OFF at time t1 in embodiment 1 and when the switch is turned OFF at time t12 in embodiment 2.

The oscillator circuit 300 of this embodiment is able to set the timing for stopping application of the control voltage signal Vc to the loop filter 16 based on the amount of change in the control voltage signal Vc, so that the timing for stopping application of the control voltage signal Vc to the loop filter 16 can be optimally set regardless of the set frequency of the local signal Ls. Therefore, in addition to the effects described in the first and second embodiments, the oscillator circuit 300 of this embodiment has the effect of further speeding up lockup.

In the explanation of the first and second embodiments, the lock detect signal Ld is Hi when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is outside a predetermined range, and is Lo when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is within a predetermined range. However, the lock detect signal Ld may be Lo when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is outside a predetermined range, and Hi when the phase difference between the reference comparison signal RCs and the negative feedback comparison signal NCs is within a predetermined range. In this case, the operation of the switch 22 may be reversed from that described above. Similarly, in the third embodiment, when the operation of the control voltage signal monitoring unit 28 is reversed from that described above, the operation of the switch 22 may be reversed from that described above.

(Modification)
The configuration of the loop filter 16 is not limited to the configurations described in each embodiment, and may be any filter that integrates the PLL control signal output from the PLL circuit 14 to generate the control voltage signal Vc. Fig. 9 shows an example of the configuration of an oscillation circuit 400 in which the loop filter 16 of the oscillation circuit 100 of the first embodiment is replaced with a loop filter 50 having a different configuration. In this case, too, the switch 22 applies the control voltage signal Vc to the connection between the first resistor 30 and the first capacitor 32. In the oscillation circuits 200 and 300, the loop filter 16 can also be replaced with the loop filter 50. Furthermore, the loop filter 16 may be configured using an operational amplifier, and various applications are possible.

The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention.

12 Reference signal oscillator 14 PLL circuit 16, 50 Loop filter 18 Voltage controlled oscillator 20 Buffer 22 Switch 24 Second resistor 26 Delay circuit 28 Control voltage signal monitor unit
30 First resistor 32 First capacitor 34 Second capacitor 40 First frequency divider
42 Second frequency divider 44 Phase comparator 46 Charge pump 100, 200, 300, 400 Oscillator circuit

Claims (4)

a reference oscillator that outputs a reference signal;
a PLL circuit that outputs a PLL control signal from a PLL control signal output unit;
a loop filter including a first resistor connected to the PLL control signal output unit and a first capacitor connected to the first resistor, the loop filter integrating the PLL control signal to generate a control voltage signal;
a voltage controlled oscillator for generating a local signal based on the control voltage signal;
a control voltage signal monitoring unit that determines whether or not a change amount of the control voltage signal is equal to or smaller than a predetermined value and outputs a determination result;
a switch that switches whether or not the control voltage signal is applied to a connection part of the first resistor and the first capacitor of the loop filter based on a determination result output by the control voltage signal monitoring part;
Equipped with
the PLL circuit outputs the PLL control signal based on a comparison result between the reference signal and the local signal;
when receiving a determination result that the amount of change in the control voltage signal is equal to or smaller than a predetermined value, the switch switches so as not to apply the control voltage signal to the loop filter;
The predetermined value is a value that can be set appropriately.
1. An oscillator circuit comprising: The control voltage signal monitoring unit monitors the voltage value of the control voltage signal at predetermined time intervals, and when the amount of change in the control voltage signal is equal to or less than the predetermined value multiple times in succession, determines that the amount of change in the control voltage signal is equal to or less than the predetermined value.
2. The oscillator circuit according to claim 1. The control voltage signal monitoring unit monitors the voltage value of the control voltage signal at predetermined time intervals, and when an average value of a plurality of consecutive changes in the control voltage signal is equal to or less than a predetermined value, determines that the change in the control voltage signal is equal to or less than a predetermined value.
2. The oscillator circuit according to claim 1. The loop filter is
a second capacitor connected between the PLL control signal output unit and ground;
3. The oscillator circuit according to claim 1, wherein the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.