CN110212894A - A kind of clock frequency switching circuit - Google Patents
A kind of clock frequency switching circuit Download PDFInfo
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- CN110212894A CN110212894A CN201910631644.3A CN201910631644A CN110212894A CN 110212894 A CN110212894 A CN 110212894A CN 201910631644 A CN201910631644 A CN 201910631644A CN 110212894 A CN110212894 A CN 110212894A
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- signal
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- clock
- frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Abstract
A kind of clock frequency switching circuit, including switching signal synchronous circuit, narrow-pulse generation circuit, clock source oscillator and switching tube.Switching tube is connected to the both ends of clock source oscillator energy-storage travelling wave tube；Switching signal synchronous circuit is synchronous with present clock source signal progress failing edge by the frequency error factor signal of acquisition, and the frequency error factor signal after synchronizing is input to narrow-pulse generation circuit and generates a narrow pulse signal, it is connected during burst pulse by the narrow pulse signal control switch pipe, so that energy-storage travelling wave tube discharges；The input terminal of clock source oscillator is connect with the output end of switching signal synchronous circuit, switches clock frequency according to the frequency error factor signal after synchronizing during burst pulse.In this manner it is ensured that clock when clock source carries out frequency error factor within the burst pulse time is low level, to be not in burr in frequency error factor movement.
Description
Technical field
The present invention relates to clock source technical fields, and in particular to a kind of clock frequency switching circuit.
Background technique
Each class of electronic devices, such as the communication equipment in wireless communication system, it usually needs using clock source as it is internal when
Between refer to.Under different application conditions, communication equipment may be needed using different clock frequencies, this is just needed to clock frequency
Rate switches over.
Currently, a kind of mode of switching clock frequency is: the clock signal of different frequency is generated by different clock sources,
Clock switching is realized by clock switch circuit again, when the characteristics of this mode is that how many different frequency just needs how many a
Zhong Yuan, structure is complicated and volume is big.The another way for switching clock frequency is to pass through frequency error factor in the same clock source
The frequency of circuit switching clock source, referring to Figure 1 and Fig. 2, wherein Fig. 1 is the structure of clock frequency switching circuit, and Fig. 2 is it
Corresponding logic chart, in this fashion, when switching signal then, to switch clock internal circuit, by changing oscillator
Parameter changes clock frequency, masks clock output before switching signal is arrived, then by timing recovery enable signal, no
Multiple clock sources are needed again, but this mode is easy to produce burr signal during switching frequency.
Summary of the invention
The application provides a kind of clock frequency switching circuit, to solve to be easy when switching clock frequency in the prior art
The problem of existing burr.
A kind of clock frequency switching circuit is provided in a kind of embodiment, including switching signal synchronous circuit, burst pulse generate
Circuit, clock source oscillator and switching tube；
The switching signal synchronous circuit includes first input end and the second input terminal, the first input end and second defeated
Enter end and be respectively used to frequency acquisition switching signal and present clock source signal, the switching signal synchronous circuit is used for the frequency
Rate switching signal carries out the synchronous of failing edge with present clock source signal, and the frequency error factor signal after being synchronized simultaneously exports；
The switching tube includes control terminal, first end and second end, and the first end and second end is separately connected clock source
The both ends of the energy-storage travelling wave tube of oscillator；
The input terminal of the narrow-pulse generation circuit is connect with the output end of switching signal synchronous circuit, for according to
Frequency error factor signal after synchronizing generates a narrow pulse signal, and the narrow pulse signal is input to the control of switching tube
End, control switch pipe are connected during burst pulse；
The input terminal of the clock source oscillator is connect with the output end of switching signal synchronous circuit, in the synchronization
Switch clock frequency under the control of frequency error factor signal afterwards.
According to the clock frequency switching circuit of above-described embodiment, switching signal synchronous circuit is by frequency error factor signal and currently
Clock source signals carry out the synchronization of failing edge, i.e., by failing edge frequency acquisition switching signal, then cut the frequency after synchronizing
It changes signal and is input to clock source oscillator, to control clock source oscillator switching clock frequency；Meanwhile narrow-pulse generation circuit meeting
A narrow pulse signal is generated according to the frequency error factor signal after synchronizing and inputs to switching tube, and control switch pipe is in the burst pulse phase
Between be connected so that the energy-storage travelling wave tube of clock source oscillator discharges, in this manner it is ensured that clock source carries out frequency within the burst pulse time
Clock when rate switches is low level, to be not in burr in switching action.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of clock frequency switching circuit in the prior art；
Fig. 2 is the logic chart of clock frequency switching circuit in the prior art；
Fig. 3 is the structural schematic diagram of the clock frequency switching circuit of an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of the clock frequency switching circuit of specific embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of switching signal synchronous circuit of the present invention；
Fig. 6 is a kind of structural schematic diagram of narrow-pulse generation circuit of the present invention；
Fig. 7 is a kind of corresponding logic chart of clock frequency switching circuit of specific embodiment of the present invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.It is herein component institute serialization number itself, such as " first ",
" second " etc. is only used for distinguishing described object, does not have any sequence or art-recognized meanings.
In embodiments of the present invention, when frequency error factor signal comes interim, switching signal synchronous circuit is by frequency error factor signal
It is synchronous that failing edge is carried out with present clock source signal, while a narrow pulse signal is generated by narrow-pulse generation circuit, with control
Switching tube processed is connected during burst pulse and the energy-storage travelling wave tube of clock source oscillator is made to discharge, when guaranteeing the switching of clock source oscillator
Clock when clock frequency is low level.
Embodiment one:
Referring to FIG. 3, being a kind of structural schematic diagram of clock frequency switching circuit provided in an embodiment of the present invention, the clock
Frequency switching circuit includes switching signal synchronous circuit 01, narrow-pulse generation circuit 02, clock source oscillator 03 and switching tube 04.
Wherein, switching signal synchronous circuit 01 includes first input end a1 and the second input terminal b1, first input end a1 and the second input
End b1 is respectively used to frequency acquisition switching signal and present clock source signal, and switching signal synchronous circuit 01 is used for frequency error factor
Signal carries out the synchronous of failing edge with present clock source signal, and the frequency error factor signal after being synchronized simultaneously exports；Switching tube 04
Including control terminal c2, first end a2 and second end b2, first end a2 and second end b2 are separately connected the storage of clock source oscillator 03
The both ends of energy element；The input terminal d of narrow-pulse generation circuit 02 is connect with the output end c1 of switching signal synchronous circuit 01, is used for
According to switching signal synchronous circuit 01 export synchronize after frequency error factor signal generate a narrow pulse signal, and by the narrow arteries and veins
The control terminal c2 that signal is input to switching tube 04 is rushed, control switch pipe 04 is connected during burst pulse, so that clock source oscillator
03 energy-storage travelling wave tube electric discharge；The input terminal of clock source oscillator 03 is connect with the output end c1 of switching signal synchronous circuit 01, is used
Switch clock frequency under the control of frequency error factor signal after synchronizing in what is exported in switching signal synchronous circuit 01.
In practical application, the energy-storage travelling wave tube of clock source oscillator 03 is generally capacitor.Switching tube 04 can be MOS (Metal
Oxide Semiconductor, Metal-oxide-semicondutor) pipe, at this point, the control terminal c2 of switching tube 04 is the grid of metal-oxide-semiconductor
Pole.Switching tube 04 is also possible to switching transistor, at this point, the control terminal c2 of switching tube 04 is the base stage of switching transistor.
Clock frequency switching circuit provided in this embodiment include switching signal synchronous circuit, narrow-pulse generation circuit, when
Clock source oscillator and switching tube, when frequency error factor signal comes temporarily, switching signal synchronous circuit is by frequency error factor signal and currently
Clock source signals carry out the synchronization of failing edge, i.e., by failing edge frequency acquisition switching signal, then cut the frequency after synchronizing
It changes signal and is input to clock source oscillator, to control clock source oscillator switching clock frequency；Meanwhile narrow-pulse generation circuit meeting
A narrow pulse signal is generated according to the frequency error factor signal after synchronizing and inputs to switching tube, and control switch pipe is in the burst pulse phase
Between be connected so that the energy-storage travelling wave tube of clock source oscillator discharges, in this manner it is ensured that clock source carries out frequency within the burst pulse time
Clock when rate switches is low level, to be not in burr in switching clock source frequency.Compared with prior art, this when
Clock frequency switching circuit does not need individual burr and eliminates circuit, does not need special frequency error factor enable signal, does not need yet
Corresponding enable signal timing circuit, circuit structure are simple.
Embodiment two:
Based on embodiment one, the present embodiment provides a kind of specific clock frequency switching circuits, referring to FIG. 4, Fig. 4 is this
The structural schematic diagram of clock frequency switching circuit, what is different from the first embodiment is that the clock frequency switching circuit of the present embodiment is also
Including output buffer 05, which connect with the output end of clock source oscillator 03, for vibrating to clock source
The output signal of device 03 carries out Buffer output (the OUT terminal output in Fig. 4), to increase the output driving of clock frequency switching circuit
Ability.In practical application, which can be made of two-stage phase inverter.In the present embodiment, clock source oscillator
03 energy-storage travelling wave tube is capacitor C1, and switching tube 04 is metal-oxide-semiconductor Q1.
Specifically, Fig. 5 shows a kind of structural schematic diagram of switching signal synchronous circuit 01, the switching signal synchronous circuit
Including failing edge trigger 11 and extracted circuit 12.Failing edge trigger 11 includes first end D and second end CLK, this
First input end a1 and second input terminal b1 of one end D and second end CLK respectively as switching signal synchronous circuit 01, the decline
The present clock source signal for frequency error factor signal and its second end CLK acquisition for being used to acquire its first end D along trigger 11
The synchronization of failing edge is carried out, and two paths of signals is exported to extracted circuit by its first output end Q and second output terminal Qn
12；Frequency error factor after extracted circuit 12 is used to synchronize from extraction in the two paths of signals that failing edge trigger 11 exports is believed
Number.In embodiments of the present invention, extracted circuit 12 can be to come out the signal extraction at the end Q as the frequency after synchronizing and cut
Change signal.Failing edge trigger 11 therein can be d type flip flop.
Fig. 6 shows a kind of structural schematic diagram of narrow-pulse generation circuit 02, which may include
Input buffer 21, delay capacitor C2, the first reverser 22, NAND gate 23 and the second reverser 24,23 He of NAND gate therein
Second reverser 24 constitutes AND gate circuit.Wherein, the output of the input terminal of input buffer 21 and switching signal synchronous circuit 01
C1 connection is held, for the frequency error factor signal after synchronizing to be buffered and exported；The first end of delay capacitor C2 is grounded, and second
End is connect with the output end of input buffer 21, is delayed for the output signal to input buffer 21；First reverser
22 include input terminal and output end, and input terminal connects the second end of delay capacitor C2, reversed for the signal after being delayed；With
The second end of the first input end e1 connection delay capacitor C2 of NOT gate 23,23 second input terminal e2 the first reverser of connection of NAND gate
22 output end, the NAND gate 23 be used for by after delay signal and the signal phase that exports of the first reverser 22 with and it is reversed；The
Two reversers 24 are connect with the output end of NAND gate 23, and the signal for exporting NAND gate 23 is reversed.It is produced by the burst pulse
Raw circuit 02, can the signal (the frequency error factor signal after synchronizing) at the end c1 generate a fixed pulse width when jumping to rising
Narrow pulse signal, the size of burst pulse is depending on the time required to the switching frequency of clock source.
Clock frequency switching circuit according to the present embodiment, and circuit logic diagram as shown in connection with fig. 7, at work,
Switching signal synchronous circuit 01 guarantees that the failing edge for using present clock source plays bat by failing edge trigger 11, passes through decline
Keep frequency error factor signal synchronous with present clock source signal along trigger 11, after the extracted using extracted circuit 12
Export the frequency error factor signal after synchronizing；Frequency error factor signal after synchronizing is transferred to narrow-pulse generation circuit 02, burst pulse
Frequency error factor signal after generation circuit 02 will be synchronized by delay capacitor C2 is delayed, after then passing through the first reverser 22 reversely
Frequency error factor signal phase after synchronous with original and the burst pulse of one fixed pulse width of generation when the signal at the end c1 jumps to rising
Signal, the time required to the switching frequency of burst pulse size apparent time clock frequency switching circuit depending on.Narrow-pulse generation circuit 02 generates
Narrow pulse signal be input to the switching tube Q1 of 03 storage capacitor C1 of clock source oscillator, within the time of narrow pulse signal, Q1
Conducting, the charge on storage capacitor C1 is bled off, clock exports low level at this time.Since frequency error factor signal is by under clock source
Drop is along synchronous, therefore narrow pulse signal is generated since when clock source output is low level, switches electricity in the clock frequency
Lu Zhong, to capacitor C1 discharge when, therefore, to assure that for the clocked logic synchronous with frequency error factor signal be low level, then,
In the switching, when frequency error factor signal arrives, clock source is synchronous with the frequency error factor signal failing edge, passes through narrow pulse signal
Clock, which is low level, to be ensured to storage capacitor C1 electric discharge, within this time, after being input to synchronizing in clock source oscillator 03
Frequency error factor signal can change and configured inside clock source oscillator 03, change 03 output clock frequency of clock source oscillator,
I.e. clock source realizes frequency error factor movement；After narrow pulse signal, Q1 is disconnected, and clock source oscillator 03 starts normal starting of oscillation,
Since narrow pulse signal before discharges C1, clock output is pulled to low level, then starts at this time to storage capacitor C1 since 0
Charging, until capacitor C1 is full of overturning, frequency at this time is exactly the frequency needed after switching.In switching action, the low electricity of clock
The low level time for adding new frequency between usually for the burst pulse time, is turned to high level again and starts, and clock is after switching
Frequency clock.
Clock frequency switching circuit provided in this embodiment is by switching signal synchronous circuit, narrow-pulse generation circuit, switch
Pipe Q1, clock source oscillator and output buffer are constituted, and switching signal synchronous circuit carries out frequency error factor signal and clock source
After failing edge synchronizes, it is transferred to narrow-pulse generation circuit and generates a narrow pulse signal, be then transmitted to the narrow pulse signal
On the switching tube of the storage capacitor C1 of clock source oscillator, the charge on storage capacitor C1 is put within the time of narrow pulse signal
Fall.Since frequency error factor signal is synchronized by clock source failing edge, it is low electricity that narrow pulse signal, which is from clock source output,
Usually start to generate, when frequency error factor signal comes temporarily, clock source is synchronous with the signal failing edge, passes through narrow pulse signal pair
Storage capacitor C1 electric discharge ensures that clock is low level, realizes frequency error factor movement in this time internal clock source.With the prior art
It compares, clock frequency switching circuit provided in this embodiment is not in burr when switching clock frequency, is not needed special
Burr eliminates circuit, does not also need special clock switching frequency enable signal and derivative logic circuit, circuit structure are simple.
The clock frequency switching circuit of above-described embodiment is a kind of carrot-free clock frequency switching circuit, can be applied to band
Have in the clock source integrated circuit of changeable frequency.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (9)
1. a kind of clock frequency switching circuit, which is characterized in that including switching signal synchronous circuit, narrow-pulse generation circuit, when
Clock source oscillator and switching tube；
The switching signal synchronous circuit includes first input end and the second input terminal, the first input end and the second input terminal
It is respectively used to frequency acquisition switching signal and present clock source signal, the switching signal synchronous circuit is for cutting the frequency
It changes signal and carries out the synchronous of failing edge with present clock source signal, the frequency error factor signal after being synchronized simultaneously exports；
The switching tube includes control terminal, first end and second end, and the first end and second end is separately connected clock source oscillation
The both ends of the energy-storage travelling wave tube of device；
The input terminal of the narrow-pulse generation circuit is connect with the output end of switching signal synchronous circuit, for according to the synchronization
Frequency error factor signal afterwards generates a narrow pulse signal, and the narrow pulse signal is input to the control terminal of switching tube, control
Switching tube processed is connected during burst pulse, so that the energy-storage travelling wave tube discharges；
The input terminal of the clock source oscillator is connect with the output end of switching signal synchronous circuit, for after described synchronize
Switch clock frequency under the control of frequency error factor signal.
2. clock frequency switching circuit as described in claim 1, which is characterized in that under the switching signal synchronous circuit includes
Drop is along trigger and extracted circuit；
The failing edge trigger, including first end and second end, the first end and second end are synchronous respectively as switching signal
The first input end of circuit and the second input terminal, the failing edge trigger are used for the frequency error factor signal and present clock
Source signal carries out the synchronization of failing edge, and exports two paths of signals to extracted circuit；
The extracted circuit, for the frequency error factor letter after being synchronized from extraction in the two paths of signals that failing edge trigger exports
Number.
3. clock frequency switching circuit as claimed in claim 2, which is characterized in that the failing edge trigger is d type flip flop.
4. clock frequency switching circuit as described in claim 1, which is characterized in that the narrow-pulse generation circuit includes:
Input buffer, input terminal are connect with the output end of switching signal synchronous circuit, for the frequency error factor after synchronizing
Signal is buffered and is exported；
The output end of delay capacitor, first end ground connection, second end and input buffer connects, for the defeated of input buffer
Signal is delayed out；
First reverser, including input terminal and output end, which connects the second end of delay capacitor, for it will be delayed after
Signal is reversed；
NAND gate, first input end connect the second end of delay capacitor, and the second input terminal connects the output of the first reverser
End, for after be delayed signal and the first reverser output signal phase with and reversely；
Second reverser is connect with the output end of NAND gate, and the signal for exporting NAND gate is reversed.
5. clock frequency switching circuit as described in claim 1, which is characterized in that it further include output buffer, the output
Buffer is connect with the output end of clock source oscillator, carries out Buffer output for the output signal to clock source oscillator.
6. clock frequency switching circuit as claimed in claim 5, which is characterized in that the output buffer is by two-stage phase inverter
It constitutes.
7. clock frequency switching circuit as described in claim 1, which is characterized in that the energy-storage travelling wave tube is capacitor.
8. clock frequency switching circuit as described in claim 1, which is characterized in that the switching tube is metal-oxide-semiconductor；The switch
The control terminal of pipe is the grid of metal-oxide-semiconductor.
9. clock frequency switching circuit as described in claim 1, which is characterized in that the switching tube is switching transistor；Institute
The control terminal for stating switching tube is the base stage of switching transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910631644.3A CN110212894A (en) | 2019-07-12 | 2019-07-12 | A kind of clock frequency switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910631644.3A CN110212894A (en) | 2019-07-12 | 2019-07-12 | A kind of clock frequency switching circuit |
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| CN110212894A true CN110212894A (en) | 2019-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910631644.3A Pending CN110212894A (en) | 2019-07-12 | 2019-07-12 | A kind of clock frequency switching circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113300600A (en) * | 2021-05-27 | 2021-08-24 | 广州大学 | Pre-boosting circuit of boosting conversion circuit |
| CN113676161A (en) * | 2020-05-15 | 2021-11-19 | 深圳市汇顶科技股份有限公司 | Method and device for generating modulated pulse signal |
-
2019
- 2019-07-12 CN CN201910631644.3A patent/CN110212894A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113676161A (en) * | 2020-05-15 | 2021-11-19 | 深圳市汇顶科技股份有限公司 | Method and device for generating modulated pulse signal |
| CN113300600A (en) * | 2021-05-27 | 2021-08-24 | 广州大学 | Pre-boosting circuit of boosting conversion circuit |
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Address after: 518000 Room 201, building A, No. 1, Qian Wan Road, Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen, Guangdong (Shenzhen Qianhai business secretary Co., Ltd.) Applicant after: Shenzhen Pengxin Data Technology Co.,Ltd. Address before: 518000 Room 201, building A, 1 front Bay Road, Shenzhen Qianhai cooperation zone, Shenzhen, Guangdong Applicant before: Shenzhen Panhai Data Technology Co.,Ltd. |