CN103312319B - Be applied to the spurious reduction phase frequency detector circuit in integer-N PLL - Google Patents
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Abstract
A kind of phase frequency detector circuit of the band spurious reduction function be applied in integer-N PLL.This phase frequency detector circuit comprises two frequency-halving circuits, 2 phase-frequency detector PFD based on dynamic trigger, and random signal produces logical circuit and numeral selects logical circuit.First the signal DIV_1 that in the reference clock signal REF_1 inputted by crystal oscillator by two frequency-halving circuits and phase-locked loop, integer divider feedback is come carry out divide-by-two operations to signal REF_2 and DIV_2.Two-way phase-frequency detector PFD1 and PFD2 detects REF_1 respectively, DIV_1 and REF_2, DIV_2 signal show that the clock pulse comprising phase frequency information is accordingly input to numeral and selects in logical circuit.Numeral selects logical circuit to comprise some selectors, the random signal being produced logical circuit output by random signal drives, by the pulse signal UP_1 that PFD1 and PFD2 produces, DN_1 and UP_2, DN_2 randomization after overdriving outputs to charge pump circuit thereafter, to realize spurious signal to disperse to reduce its power spectral density, realize the effect of spurious reduction.
Description
Technical field
The present invention relates to analog phase-locked look field, be specifically related to a kind of phase frequency detector circuit of the spurious reduction be applied in integer-N PLL.
Background technology
Phase-locked loop is the important module of in transceiver, it is used to provide the machine oscillator signal, and along with the fast development of field of wireless communication, transceiver is also more and more higher for the requirement of the various performances of phase-locked loop, especially phase noise, spuious and these 3 indexs of power consumption are more and more concerned.
The phase-locked loop of integral frequency divisioil is generally made up of phase frequency detector, charge pump, loop filter, voltage controlled oscillator and divider.Wherein, phase frequency detector is used for detecting the phase place between the reference signal that inputted by crystal oscillator and the signal fed back by divider and frequency difference information, and converts the potential pulse that width do not wait to and export.The potential pulse that the width that phase frequency detector exports by charge pump circuit does not wait converts corresponding current impulse to, charges or discharge to the loop filter of charge pump rear class.The voltage output end of loop filter directly receives the control voltage input of voltage controlled oscillator to control the frequency of oscillator output.Divider is generally a programmable frequency dividing circuit, and the high frequency output signal frequency split of voltage controlled oscillator becomes low frequency signal to feed back in phase frequency detector by it.
Spurious signal in exporting for phase-locked loop is that the noise introduced during switch under reference frequency due to charge pump causes greatly.The injection noise that this frequency is identical with reference signal can cause little voltage fluctuation in the output of loop filter thus modulation voltage controlled oscillator occurs larger reference spur so that export local oscillation signal both sides band.
Summary of the invention
Can be guessed by the producing cause of reference spur and know, if loop filter can be exported with the voltage fluctuation randomization of reference signal same frequency and equalization, so the output spectrum of voltage controlled oscillator is just more smooth-going contains lower stray energy.When phase lock loop locks, charge pump carrys out switch MOS pipe with reference frequency, thus produces and the noise of reference signal same frequency, if can when phase lock loop locks the switching frequency of randomization charge pump, then can realize the randomness of noise voltage fluctuations, thus reach the spuious object of suppression.
Based on the thought of randomization charge pump switches frequency, because the switch controlling signal of charge pump derives from phase frequency detector, random clock signal can be introduced in phase frequency detector, by suitable logic control circuit, originally that phase frequency detector is exported with pulse repetition frequency randomization that is reference clock same frequency, the Injection Current noise frequency of such charge pump, also with regard to randomization, reaches the randomized target of loop filter output noise voltage fluctuation.
For solving the above-mentioned technical problem existed in prior art, the present invention proposes a kind of spurious reduction phase frequency detector circuit be applied in integer-N PLL, effectively can inhibit the reference spur on phase-locked loop output spectrum.
Design philosophy of the present invention is:
The present invention is a kind of phase frequency detector circuit of the band spurious reduction function be applied in integer-N PLL.This phase frequency detector circuit comprises two frequency-halving circuits, two phase-frequency detectors based on dynamic trigger (PFD), and random signal produces logical circuit and numeral selects logical circuit.First the signal DIV_1 that in the reference clock signal REF_1 inputted by crystal oscillator by two frequency-halving circuits and phase-locked loop, integer divider feedback is come carry out divide-by-two operations to signal REF_2 and DIV_2.Two-way phase-frequency detector PFD1 and PFD2 detects REF_1 respectively, DIV_1 and REF_2, DIV_2 signal show that the clock pulse comprising phase frequency information is accordingly input to numeral and selects in logical circuit.Numeral selects logical circuit to comprise some selectors, the random signal being produced logical circuit output by random signal drives, by the pulse signal UP_1 that PFD1 and PFD2 produces, DN_1 and UP_2, DN_2 randomization after overdriving outputs to charge pump circuit thereafter, to realize spurious signal to disperse to reduce its power spectral density, realize the effect of spurious reduction.
The phase frequency detector circuit that the present invention proposes contains two phase-frequency detector PFD, but their work at different frequencies, and their operating frequency differs 2 times in the present invention.This phase-frequency detector detects the rising edge of input signal based on the dynamic D trigger of band reset function, and comprise the inverter of following thereafter and with door, delay cell, this phase-frequency detector is the basic composition unit of this phase frequency detector circuit.Due to two phase-frequency detector work in this phase frequency detector circuit at different frequencies, this phase frequency detector circuit comprises two and to be held by the output QB of dynamic D trigger and receive input this dynamic D trigger D and hold and the frequency-halving circuit that forms, provides signal to work phase-frequency detector at a lower frequency.Also comprise a random signal in this phase frequency detector circuit and produce logical circuit to produce random signal to drive the numeral selection logical circuit of rear class.Random signal produces logical circuit by 4 dynamic D triggers, an XOR gate, a delay cell and a selector composition.The low frequency signals that selector is obtained after above-mentioned frequency-halving circuit by input reference signal controls, and the connected mode of this uniqueness provides more reliable and stable random signal.Described numeral selects logical circuit to have employed three selectors, first selector is by outside input control, decide adopt fixing reference signal or adopt random signal, the second level is 2 selectors in parallel, controlled to export UP_1 by the output of first selector, DN_1 or UP_2, DN_2 signal.Once first selector outputs random signal, then the second level exports UP_1 at random, DN_1 or UP_2, DN_2 signal, the randomization switching frequency of charge pump.
Concrete technical scheme of the present invention is as follows:
Be applied to the spurious reduction phase frequency detector circuit in integer-N PLL, comprise two frequency-halving circuits, two the phase-frequency detector PFD based on dynamic trigger, random signals produce logical circuit and a numeral selection logical circuit; Numeral is connected with two drive circuits after selecting logical circuit;
Random signal produces the reference clock signal REF_1 signal output part of the input connection crystal oscillator input of logical circuit, and random signal produces logical circuit and exports random signal Ran_C;
The reference clock signal REF_1 inputted by crystal oscillator by the first frequency-halving circuit carries out two divided-frequency, obtains signal REF_2; By the second frequency-halving circuit, integer divider in phase-locked loop is fed back the signal DIV_1 come and carry out two divided-frequency, obtain signal DIV_2;
Two inputs of first phase frequency detector PFD1 connect signal REF_1 and the signal DIV_1 output of the first frequency-halving circuit respectively, and first phase frequency detector PFD1 exports the clock pulse signal UP_1 and the signal DN_1 that comprise phase frequency information accordingly;
Two inputs of second phase frequency detector PFD2 connect signal REF_2 and the signal DIV_2 output of the second frequency-halving circuit respectively, and second phase frequency detector PFD2 exports the clock pulse signal UP_2 and the signal DN_2 that comprise phase frequency information accordingly;
The operating frequency of described first phase frequency detector PFD1 is higher than second phase frequency detector PFD2;
Numeral selects signal UP_1, the signal DN_1 of logical circuit, signal UP_2 and signal DN_2 input to be connected signal UP_1 and the signal DN_1 output of first phase frequency detector PFD1 respectively, and the signal UP_2 of second phase frequency detector PFD2 and signal DN_2 output;
Numeral selects the control signal input of logical circuit to connect random signal Ran_C output and the external input signal INPUT of random signal generation logical circuit respectively; Numeral selects signal output part output signals UP and the DN of logical circuit; It is UPP and UPN that UP signal obtains complementary signal through a drive circuit, but the identical electrical level polar of their frequencies is contrary; It is DNP, DNN that DN signal obtains complementary signal through another drive circuit, but the identical electrical level polar of their frequencies is contrary.
First and second frequency-halving circuit described is identical; Frequency-halving circuit is made up of a d type flip flop based on true single phase clock structure QB end signal being fed back to D end; The Q end of d type flip flop is frequency output terminal, and the clock signal input terminal of d type flip flop is frequency input.
The structure of described two phase-frequency detectors is identical;
For arbitrary phase-frequency detector, its structure comprises two d type flip flops, and the D of two d type flip flops inputs termination power vd D;
When the clock signal input terminal of the first d type flip flop meets signal REF_1 or signal REF_2, the clock signal input terminal of corresponding second d type flip flop meets signal DIV_1 or signal DIV_2;
The Q end of the first d type flip flop connects two-stage inverter, and two inverters connect and compose first group of inverter successively; The Q end of the second d type flip flop connects two-stage inverter, and two inverters connect and compose second group of inverter successively; In first and second group inverter, each inverter is identical;
The output of first and second group inverter is connected to two inputs and door, is be connected two-stage delay circuit with gate output terminal;
Two delay circuits are all be made up of inverter and electric capacity, and wherein, the input of inverter is as the input of delay circuit, and the output of inverter is as the output of delay circuit, and the output of inverter passes through capacity earth;
Inverter parameter in two delay circuits is identical, and the capacitance of the electric capacity in the delay circuit of the second level is 1.5 times of the capacitance of the electric capacity in first order delay circuit.
It is the synchronizing sequential circuit be made up of level Four d type flip flop, a selector and an XOR gate that described random signal produces logical circuit; Level Four d type flip flop connects successively;
In first three grade of d type flip flop, the QB end of previous stage trigger connects the D end of next stage trigger; The QB end of afterbody trigger and the Q end of first order trigger are connected to two inputs of XOR gate, and the output of XOR gate is connected to the D end of first order trigger; The input end of clock of all d type flip flops all connects the reference clock signal REF_1 signal output part of crystal oscillator input;
The Q end of described first order trigger is connected selector two input, the output of the control end connection signal REF_2 of selector respectively with QB end, and the output of selector is the random signal Ran_C output that random signal produces logical circuit; Random signal Ran_C has high and low level signal, and the probability that high and low level produces is identical.
Described random signal produces in logical circuit and also comprises delay cell, between the QB output of the input connection first order trigger of this delay cell and the input of selector.
Numeral selects logical circuit to comprise three selectors, is first and second and three selectors respectively;
In first selector, A input end grounding, B input connects the output that random signal produces logical circuit, and control input end connects external input signal INPUT, and Y output connects the control input end of second and third selector respectively;
In second selector, A input connects the clock pulse UP_1 output of first phase frequency detector PFD1, and B input connects the clock pulse DN_1 output of first phase frequency detector PFD1, and Y output is UP signal output part;
In third selector, A input connects the clock pulse UP_2 output of second phase frequency detector PFD2, and B input connects the clock pulse DN_2 output of second phase frequency detector PFD2, and Y output is DN signal output part;
Selected by the external input signal INPUT in described first selector: in the starting stage of phase-locked loop operation, a mode; After phase lock loop locks, select b mode;
A mode is, fixedly chooses UP_1 and DN_1 selects logical circuit output as numeral;
B mode is, chooses arbitrarily the output of UP_1 and DN_1 or UP_2 and DN_2 as numeral selection logical circuit by random signal.
Described drive circuit comprises numeral and selects the UP signal of logical circuit and UP branch road corresponding to DN signal and DN branch road, and the structure of two branch roads is identical;
For arbitrary branch road, comprise the parallel inverter of two-way and a delay cell;
For corresponding the setting out on a journey of signal UPP or DNP, comprise four inverters connected successively, wherein the input of the first inverter connects UP signal or the DN signal output part that numeral selects logical circuit; Four inverters increase step by step; Afterbody inverter exports UPP or DNP signal;
For the lower road that signal UPN or DNN is corresponding, three inverters comprising MOS switch and connect successively thereafter; The input of described MOS switch connects UP signal or DN signal output part that numeral selects logical circuit; Three inverters increase step by step; Afterbody inverter exports UPN or DNN signal;
For in upper and lower road, according to from rear to front sequence, three grades of inverters are identical between two; The time of delay that delay cell in lower road provides with set out on a journey in first order inverter identical for time of delay of causing.
Described delay cell is MOS switch, and what this MOS switch was made up of PMOS and NMOS often drives MOS switch.
Accompanying drawing explanation
Fig. 1 is phase frequency detector overall structure block diagram of the present invention.
Fig. 2 is the circuit diagram of the two-divider that embodiment adopts.
Fig. 3 is the circuit diagram that in the present invention, random signal produces logical circuit.
Fig. 4 is the circuit diagram of the phase-frequency detector that embodiment adopts.
Fig. 5 is the circuit diagram that in the present invention, numeral selects logical circuit.
Numeral selects logical circuit Single-end output to change into the drive circuit schematic diagram of charge pump double-width grinding by Fig. 6 in the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
Phase frequency detector circuit described in the specific embodiment of the invention is the innovation and improvement carried out on the basis of phase-frequency detector shown in Fig. 4, comprise in the system of random signal generation logical circuit and numeral selection logical circuit by two phase-frequency detectors being incorporated into one, one of them phase-frequency detector is assisted to be operated in lower frequency by two frequency-halving circuits, thus any one that can drive selection two phase-frequency detectors by random signal is as output, upset fixing reference frequency, inhibit reference spur.
The d type flip flop based on true single phase clock structure of QB signal feedback to D input forms by one by the frequency-halving circuit that the technical program adopts.Fig. 2 is exactly the frequency-halving circuit utilizing dynamic D trigger to realize, the QB output feedback link of d type flip flop is to D input, the clock input of two d type flip flops is respectively from the output of divider in the reference frequency input of crystal oscillator and phase-locked loop, and frequency-halving circuit outputs signal and is supplied to the lower phase-frequency detector of operating frequency.
Phase-frequency detector can adopt existing phase-frequency detector, as shown in Figure 4, in phase-frequency detector, the D of d type flip flop 301 and d type flip flop 302 inputs termination power vd D, the clock input of d type flip flop 301 connects reference frequency signal or its two divided-frequency signal, and the clock input of d type flip flop 302 connects signal or its two divided-frequency signal of phase-locked loop divider feedback.D type flip flop 301 and d type flip flop 302 export Q end and are connected the identical inverter of two-stage 303,310 and 309,311 all respectively.The output of inverter 310 and inverter 311 is connected to 2 inputs and door 304, is two-stage delay circuit with gate output terminal, by a larger dead-time problem overcoming charge pump switches time of delay.Wherein in delay circuit, inverter 305 is identical with 306 parameters, and the value of electric capacity 308 is 1.5 times of electric capacity 307.
It is a synchronizing sequential circuit be made up of 4 grades of d type flip flops and an XOR gate that random signal in the present invention produces logical circuit, as shown in Figure 3, front 3 grades of d type flip flops, (i.e. trigger 201, 202, 203) QB exports the D input all connecting next stage trigger, the Q of the QB of trigger 204 end and trigger 201 is held the D end being fed back to first order trigger 201 by an XOR gate 205, the clock input of all d type flip flops all connects crystal oscillator input signal, so just, achieve random signal generating circuit, in order to reach the reliability and stability requirement of random signal, output Q and the QB end of first order trigger 201 is connected to a selector controlled by the signal REF_2 of reference signal REF_1 after two divided-frequency, the connected mode of this innovation can ensure that low and high level output probability is equal, degree of randomization is higher.In order to weaken the problem of clock competition burr in circuit, delay cell 207 is inserted into QB signal rear end, by the time of delay of Reasonable adjustment delay cell 207, effectively can reduce burr.
Fig. 5 and Fig. 6 sets forth numeral and selects logical circuit and drive circuit thereafter.Numeral selects logical circuit to be made up of 3 selectors 401,402,403.UP_1, DN_1 is from the phase-frequency detector of high operate frequency, UP_2, DN_2 is from the phase-frequency detector of low operating frequency, the control inputs signal IINPUT of selector 401 is inputted by outside, and it is used for selection is fixedly choose UP_1, and DN_1 selects the output of logical circuit still to choose UP_1 arbitrarily by random signal as numeral, DN_1 or UP_2, DN_2 select the output of logical circuit as numeral.In the starting stage of phase-locked loop operation, in order to ensure that phase-locked loop can lock faster, can fix and select UP_1, DN_1 as output.After phase lock loop locks, in order to suppress spuious, random signal is just introduced into controlled selector.
For difference or the charge pump being with mirror image branch, only provide UP and DN signal to be inadequate, also need the complementary signal that they are provided, be labeled as UPP at this, UPN and DNP, DNN; But the identical electrical level polar of their frequency is contrary.In order to obtain such signal, we need to add drive circuit after numeral selects logical circuit, as shown in Figure 6.For UP branch road, inverter 501,502,503,504 increase step by step; And inverter 502 and inverter 506, inverter 503 and inverter 507, inverter 504 is identical with inverter 508.505 is the MOS switches often opened be made up of PMOS and NMOS, is used to provide a short delay, and the Late phase that causes of time of delay and inverter 501 with.The structure of DN branch road is identical with UP branch road, UP and DN signal just can obtain 2 charge pump drive singal UPP to complementation after overdrive circuit, UPN and DNP, DNN.
Claims (7)
1. be applied to the spurious reduction phase frequency detector circuit in integer-N PLL, it is characterized in that: comprise two frequency-halving circuits, two the phase-frequency detector PFD based on dynamic trigger, random signals produce logical circuit and a numeral selection logical circuit; Numeral is connected with two drive circuits after selecting logical circuit;
Random signal produces the reference clock signal REF_1 signal output part of the input connection crystal oscillator input of logical circuit, and random signal produces logical circuit and exports random signal Ran_C;
The reference clock signal REF_1 inputted by crystal oscillator by the first frequency-halving circuit carries out two divided-frequency, obtains signal REF_2; By the second frequency-halving circuit, integer divider in phase-locked loop is fed back the signal DIV_1 come and carry out two divided-frequency, obtain signal DIV_2;
Two inputs of first phase frequency detector PFD1 connect reference clock signal REF_1 and the signal DIV_1 output of the first frequency-halving circuit respectively, and first phase frequency detector PFD1 exports the clock pulse signal UP_1 and the signal DN_1 that comprise phase frequency information accordingly;
Two inputs of second phase frequency detector PFD2 connect signal REF_2 and the signal DIV_2 output of the second frequency-halving circuit respectively, and second phase frequency detector PFD2 exports the clock pulse signal UP_2 and the signal DN_2 that comprise phase frequency information accordingly;
The operating frequency of described first phase frequency detector PFD1 is higher than second phase frequency detector PFD2;
Numeral selects signal UP_1, the signal DN_1 of logical circuit, signal UP_2 and signal DN_2 input to be connected signal UP_1 and the signal DN_1 output of first phase frequency detector PFD1 respectively, and the signal UP_2 of second phase frequency detector PFD2 and signal DN_2 output;
Numeral selects the control signal input of logical circuit to connect random signal Ran_C output and the external input signal INPUT of the output of random signal generation logical circuit respectively; Numeral selects signal output part output signals UP and the DN of logical circuit; It is UPP and UPN that UP signal obtains complementary signal through a drive circuit, but the identical electrical level polar of their frequencies is contrary; It is DNP, DNN that DN signal obtains complementary signal through another drive circuit, but the identical electrical level polar of their frequencies is contrary.
2. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 1, is characterized in that first and second frequency-halving circuit described is identical; Frequency-halving circuit is made up of a d type flip flop based on true single phase clock structure QB end signal being fed back to D end; The Q end of d type flip flop is frequency output terminal, and the clock signal input terminal of d type flip flop is frequency input;
The structure of described two phase-frequency detectors is identical;
For arbitrary phase-frequency detector, its structure comprises two d type flip flops, and the D of two d type flip flops inputs termination power vd D;
When the clock signal input terminal of the first d type flip flop meets signal REF_1, the clock signal input terminal of the second d type flip flop meets signal DIV_1; Or when the clock signal input terminal of the first d type flip flop meets signal REF_2, the clock signal input terminal of the second d type flip flop meets signal DIV_2;
The Q end of the first d type flip flop connects two-stage inverter, and two inverters connect and compose first group of inverter successively; The Q end of the second d type flip flop connects two-stage inverter, and two inverters connect and compose second group of inverter successively; In first and second group inverter, each inverter is identical;
The output of first and second group inverter is connected to two inputs and door, is be connected two-stage delay circuit with gate output terminal;
Two delay circuits are all be made up of inverter and electric capacity, and wherein, the input of inverter is as the input of delay circuit, and the output of inverter is as the output of delay circuit, and the output of inverter passes through capacity earth;
Inverter parameter in two delay circuits is identical, and the capacitance of the electric capacity in the delay circuit of the second level is 1.5 times of the capacitance of the electric capacity in first order delay circuit.
3. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 1, it is characterized in that described random signal produces logical circuit is the synchronizing sequential circuit be made up of level Four d type flip flop, a selector and an XOR gate; Level Four d type flip flop connects successively;
In first three grade of d type flip flop, the QB end of previous stage trigger connects the D end of next stage trigger; The QB end of afterbody trigger and the Q end of first order trigger are connected to two inputs of XOR gate, and the output of XOR gate is connected to the D end of first order trigger; The input end of clock of all d type flip flops all connects the reference clock signal REF_1 signal output part of crystal oscillator input;
The Q end of described first order trigger is connected selector two input, the output of the control end connection signal REF_2 of selector respectively with QB end, and the output of selector is the random signal Ran_C output that random signal produces logical circuit output; Random signal Ran_C has high and low level signal, and the probability that high and low level produces is identical.
4. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 3, it is characterized in that described random signal produces in logical circuit and also comprise delay cell, between the QB output of the input connection first order trigger of this delay cell and the input of selector.
5. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 1, it is characterized in that numeral selects logical circuit to comprise three selectors, is first and second and three selectors respectively;
In first selector, A input end grounding, B input connects the output that random signal produces logical circuit, and control input end connects external input signal INPUT, and Y output connects the control input end of second and third selector respectively;
In second selector, A input connects the clock pulse UP_1 output of first phase frequency detector PFD1, and B input connects the clock pulse DN_1 output of first phase frequency detector PFD1, and Y output is UP signal output part;
In third selector, A input connects the clock pulse UP_2 output of second phase frequency detector PFD2, and B input connects the clock pulse DN_2 output of second phase frequency detector PFD2, and Y output is DN signal output part;
Selected by the external input signal INPUT in described first selector: in the starting stage of phase-locked loop operation, select a mode; After phase lock loop locks, select b mode;
A mode is, fixedly chooses UP_1 and DN_1 selects logical circuit output as numeral;
B mode is, chooses arbitrarily the output of UP_1 and DN_1 or UP_2 and DN_2 as numeral selection logical circuit by random signal.
6. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 5, it is characterized in that described drive circuit comprises numeral and selects the UP signal of logical circuit and UP branch road corresponding to DN signal and DN branch road, the structure of two branch roads is identical;
For arbitrary branch road, comprise the parallel inverter of two-way and a delay cell;
For corresponding the setting out on a journey of signal UPP or DNP, comprise four inverters connected successively, wherein the input of the first inverter connects UP signal or the DN signal output part that numeral selects logical circuit; Four inverters increase step by step; Afterbody inverter exports UPP or DNP signal;
For the lower road that signal UPN or DNN is corresponding, three inverters comprising MOS switch and connect successively thereafter; The input of described MOS switch connects UP signal or DN signal output part that numeral selects logical circuit; Three inverters increase step by step; Afterbody inverter exports UPN or DNN signal;
For in upper and lower road, according to from rear to front sequence, three grades of inverters are identical between two; The time of delay that delay cell in lower road provides with set out on a journey in first order inverter identical for time of delay of causing.
7. the spurious reduction phase frequency detector circuit be applied in integer-N PLL according to claim 6, it is characterized in that described delay cell is MOS switch, what this MOS switch was made up of PMOS and NMOS often drives MOS switch.
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| US10965296B2 (en) * | 2016-08-09 | 2021-03-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Frequency synthesizer |
| CN108988850B (en) * | 2018-08-31 | 2022-03-11 | 重庆西南集成电路设计有限责任公司 | Dual-mode linearized charge pump circuit and mode selection circuit for phase-locked loop |
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| WO2021142830A1 (en) * | 2020-01-19 | 2021-07-22 | 京东方科技集团股份有限公司 | Random number generation circuit, random number generation method, and electronic device |
| CN112953527A (en) * | 2021-03-12 | 2021-06-11 | 中国科学院微电子研究所 | Phase-locked loop structure and electronic equipment capable of being locked quickly |
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