CN110460328A - Arbitrary integer frequency divider and phase-locked loop systems - Google Patents
Arbitrary integer frequency divider and phase-locked loop systems Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The application provides a kind of arbitrary integer frequency divider and phase-locked loop systems.Arbitrary integer frequency divider includes frequency division module and logical operation module.First input end of the first input end of frequency division module as arbitrary integer frequency divider, for receiving the first signal；Second input terminal of second input terminal of frequency division module as arbitrary integer frequency divider, for receiving control signal；The first input end of the output end connection logical operation module of frequency division module；Output end of the output end of logical operation module as arbitrary integer frequency divider；The third input terminal of the output end connection frequency division module of logical operation module and the second input terminal of logical operation module.Arbitrary integer fraction frequency device provided by the present application is simple, it is easy to accomplish.
Description
Technical field
This application involves digital circuit technique field more particularly to a kind of arbitrary integer frequency dividers and phase-locked loop systems.
Background technique
Phase-locked loop systems usually form feedforward path by phase frequency detector, filter and voltage controlled oscillator three parts, by dividing
The feedback network of frequency device component frequency phase.Frequency divider inputs phase frequency detector, frequency discrimination after dividing the frequency of voltage controlled oscillator
The phase difference of this frequency clock and reference clock is converted into voltage signal output by phase discriminator, is formed after low-pass filtered device filtering
The control voltage of voltage controlled oscillator, is modulated the frequency of oscillator output signal.
Frequency divider in general phase-locked loop systems is by the way that n d type flip flop cascade is realized 2nFrequency dividing, it cannot
Realize the frequency dividing of arbitrary integer.But with the development of integrated circuit, system is higher and higher to the requirement on flexibility of phaselocked loop,
For different application demands, system provides different reference clocks to phaselocked loop, and frequency divider is needed to provide wider frequency dividing ratio,
Therefore, 2nFrequency dividing circuit is difficult to meet the requirements, it is desirable to provide is able to carry out the frequency divider of arbitrary integer frequency dividing.
Arbitrary integer divider circuit in traditional technology needs to carry out odd even selection by switching switch, and there are realities
Existing complicated problem.
Summary of the invention
Based on this, it is necessary to provide a kind of arbitrary integer frequency divider and phase-locked loop systems.
A kind of arbitrary integer frequency divider, comprising: frequency division module and logical operation module；
First input end of the first input end of the frequency division module as the arbitrary integer frequency divider, for receiving the
One signal；Second input terminal of second input terminal of the frequency division module as the arbitrary integer frequency divider, for receiving control
Signal processed；The output end of the frequency division module connects the first input end of the logical operation module；The logical operation module
Output end of the output end as the arbitrary integer frequency divider；The output end of the logical operation module connects the frequency dividing mould
The third input terminal of block and the second input terminal of the logical operation module；
The frequency division module carries out scaling down processing to first signal according to the control signal and generates second signal, and
The second signal is sent to the logical operation module；The logical operation module carries out logic fortune to the second signal
It generates and third signal and exports after calculation, and the third signal is inputted the frequency division module and described by the logical operation module
Logical operation module.
The frequency division module includes multiple sub- frequency units in one of the embodiments,；
The sub- frequency unit control signal input connects non-inverting signal input thereof；The signal of the sub- frequency unit is defeated
Outlet connects the signal input part of sub- frequency unit described in next stage；Under the reverse signal output end connection of the sub- frequency unit
The non-inverting signal input thereof of sub- frequency unit described in level-one；
The signal input part and reverse signal of sub- frequency unit described in the first order in the multiple sub- frequency unit input
The first input end as the frequency division module is held, for receiving first signal；The data of each sub- frequency unit are defeated
Enter second input terminal of the end as the frequency division module, for receiving the control signal；Each sub- frequency unit it is preset
Third input terminal of the number control terminal as the frequency division module, is separately connected the output end of the logical operation module, for connecing
Receive the third signal；The signal output end and reverse signal output end of each sub- frequency unit are as the frequency division module
Output end is all connected with the first input end of the logical operation module, for exporting the second signal.
In one of the embodiments, the sub- frequency unit include the first d type flip flop, the first NAND gate, second with it is non-
The first input end of door and phase inverter, the input terminal of the phase inverter and first NAND gate is as the sub- frequency unit
Data input pin, the output end of the phase inverter connect the second input terminal of second NAND gate；First NAND gate
The preset number control terminal of second input terminal and the first input end of second NAND gate as the sub- frequency unit；Described
The output end of one NAND gate connects the reset signal input terminal of first d type flip flop, and the output end of second NAND gate connects
Connect the setting signal input terminal of first d type flip flop.
The control signal is configuration words signal in one of the embodiments,.
The data bits of the configuration words signal is more than or equal in one of the embodiments,.
In one of the embodiments, when the third signal is high level, the sub- frequency unit work is preset
The value of number state, the signal output end output of the sub- frequency unit is equal to the value of data input pin input；When the third is believed
Number be low level when, the sub- frequency unit signal output end output value be equal to control signal input input value.
The logical operation module includes arithmetic element, resetting unit and driving shaping list in one of the embodiments,
Member；
First input end of the first input end of the arithmetic element as the logical operation module, the arithmetic element
Input terminal connect the output end of the frequency division module, for receiving the second signal；The output end of the arithmetic element connects
Connect the input terminal of the resetting unit；The output end of the resetting unit connects the input terminal of the driving shaping unit；It is described
Drive output end of the output end of shaping unit as the logical operation module；Second input terminal conduct of the arithmetic element
The output end of second input terminal of the logical operation module, the driving shaping unit connects the second defeated of the arithmetic element
Enter end.
The resetting unit includes the second d type flip flop in one of the embodiments, and second d type flip flop is decline
Along effective d type flip flop, the output end of the arithmetic element connects the input terminal of second d type flip flop；The 2nd D triggering
The output end of device connects the input terminal of the driving shaping unit.
The arithmetic element is programmable logic arithmetic element in one of the embodiments,.
A kind of phase-locked loop systems, including as above described in any item arbitrary integer frequency dividers.
The arbitrary integer frequency divider and phase-locked loop systems provided by the embodiments of the present application, the arbitrary integer frequency divider packet
Include the frequency division module and the logical operation module.The frequency division module carries out scaling down processing to first signal, described
The third signal is generated after logical operation module further progress logical operation.The arbitrary integer provided in this embodiment point
Frequency device can be realized the arbitrary integer frequency dividing to first signal, and without carrying out odd even selection, no setting is required, and switching is switched, knot
Structure is simple, is easy to implement, and greatly improves applicability.In addition, the third signal is input to by the logical operation module
The frequency division module and the logical operation module improve the frequency division module and logical operation module frequency dividing and operation
Accuracy.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for the arbitrary integer frequency divider that the application one embodiment provides；
Fig. 2 is the structural schematic diagram for the frequency division module that the application one embodiment provides；
Fig. 3 is the structural schematic diagram for the sub- frequency unit that the application one embodiment provides；
Fig. 4 is the structural schematic diagram for the logical operation module that the application one embodiment provides；
The structural schematic diagram for the logical operation module that Fig. 5 is the data bits that the application one embodiment provides when being 9；
Each signal contrast schematic diagram that Fig. 6 is the data bits that the application one embodiment provides when being 9.
Description of symbols
Arbitrary integer frequency divider 10
Frequency division module 100
Sub- frequency unit 110
First d type flip flop 111
First NAND gate 112
Second NAND gate 113
Phase inverter 114
Logical operation module 200
Arithmetic element 210
Second d type flip flop 221
Resetting unit 220
Drive shaping unit 230
Specific embodiment
It is any to the application below in conjunction with attached drawing for the objects, technical solutions and advantages of the application are more clearly understood
The specific embodiment of integer frequency divider is illustrated.It should be appreciated that specific embodiment described herein is only used to explain
The application is not used to limit the application.
Arbitrary integer frequency divider 10 provided by the embodiments of the present application may be used as the frequency divider of phaselocked loop or clock occurs
Device.
Referring to Figure 1, the application one embodiment provides a kind of arbitrary integer frequency divider 10.The arbitrary integer frequency divider
10 include frequency division module 100 and logical operation module 200.The frequency division module 100 include first input end, the second input terminal and
Output end.The logical operation module 200 includes first input end, the second input terminal, third input terminal and output end.Described point
The output end of frequency module 100 connects the input terminal of the logical operation module 200.The output end of the logical operation module 200
Connect the third input terminal of the frequency division module 100 and the second input terminal of the logical operation module 200.
First input end of the first input end of the frequency division module 100 as the arbitrary integer frequency divider 10, is used for
Receive the first signal CLK_IN.Second input terminal of the frequency division module 100 as the arbitrary integer frequency divider 10 second
Input terminal, for receiving control signal DIV<n:0>.The output end of the logical operation module 200 is as the arbitrary integer point
The output end of frequency device 10, for exporting third signal CLK_OUT.
The frequency division module 100 controls signal DIV<n:0>according to the control and divides the first signal CLK_IN
Frequency is handled, and generates second signal CLK_DIV.The second signal CLK_DIV is sent to the logic by the frequency division module 100
Computing module 200.The logical operation module 200 carries out logical operation according to logic of propositions circuit or algorithm, by described second
Signal CLK_DIV is according to generating the third signal CLK_OUT after presetting sub- division factor frequency dividing and export.Meanwhile it described patrolling
It collects computing module 200 and the third signal CLK_OUT is input to the frequency division module 100 and the logical operation module 200.
In the present embodiment, the arbitrary integer frequency divider 10 includes the frequency division module 100 and the logical operation module
200.The frequency division module 100 carries out scaling down processing to the first signal CLK_IN, and the logical operation module 200 is further
The third signal CLK_OUT is generated after carrying out logical operation.The arbitrary integer frequency divider 10 provided in this embodiment can
It realizes and the arbitrary integer of first signal is divided, without carrying out odd even selection, no setting is required, and switching is switched, and structure is simple,
It is easy to implement, greatly improves applicability.In addition, the logical operation module 200 inputs the third signal CLK_OUT
To the frequency division module 100 and the logical operation module 200, the frequency division module 10 and the logical operation module are improved
The accuracy of 200 frequency dividings and operation.
Fig. 2 is referred to, in one embodiment, the frequency division module 100 includes multiple sub- frequency units 110.The son
Frequency unit 110 can be the d type flip flop (SDFF) with preset number function.The sub- frequency unit 110 is inputted including data
Hold N, preset number control terminal Ld, signal input part CK, non-inverting signal input thereof CK_, control signal input D, signal output end
Q, reverse signal output end QB.
Wherein, the control signal input D of each sub- frequency unit 110 connects the non-inverting signal input thereof of itself
QB, meanwhile, the signal of the sub- frequency unit 110 of the signal output end Q connection next stage of each sub- frequency unit 110
Input terminal CK.Sub- frequency unit 110 described in the reverse signal output end QB connection next stage of the sub- frequency unit 110 it is reversed
Signal input part CK_.
In multiple sub- frequency units 110, the signal input part CK of sub- frequency unit 110 described in the first order and reversed letter
Number first input end of the input terminal CK_ as the frequency division module 100, for receiving the first signal CLK_IN.Wherein,
The signal input part CK of sub- frequency unit 110 described in level-one receives the clk in the first signal CLK_IN, son described in the first order
The non-inverting signal input thereof CK_ of frequency unit 110 receives the clkb in the first signal CLK_IN.Each sub- frequency unit
Second input terminal of the 110 data input pin N as the frequency division module 100, for receiving the control signal DIV<n:0>.
Third input terminal of the preset number control terminal Ld of each sub- frequency unit 110 as the frequency division module 100.Each son point
The preset number control terminal Ld of frequency unit 110 is connect with the output end of the logical operation module 200, for receiving the third letter
Number CLK_OUT.The signal output end Q and reverse signal output end QB of the sub- frequency unit 110 are as the frequency division module 100
Output end.The signal output end Q and reverse signal output end QB of the sub- frequency unit 110 with the logical operation module
200 first input end, for exporting the second signal CLK_DIV.
In one embodiment, when the third signal CLK_OUT is high level, the sub- frequency unit 110 works
It is equal to the value of data input pin input in the value of preset number state, the signal output end output of the sub- frequency unit 110.Work as institute
When to state third signal CLK_OUT be low level, the value of the signal output end of the sub- frequency unit 110 is equal to control signal input
Hold the value of input.
The frequency division module 100 of above several embodiment introductions, has the advantages of simple structure and easy realization.Meanwhile by each son
The preset number control terminal Ld of frequency unit 110 connects the output end of the logical operation module 200, receives the third signal
CLK_OUT realizes the preset number control of the sub- frequency unit 110, and structure is more convenient, and facilitates memory.
Fig. 3 is referred to, in one embodiment, the sub- frequency unit 110 includes a d type flip flop, two NAND gates
With a phase inverter.As shown in figure 3, the sub- frequency unit 110 includes the first d type flip flop 111, the first NAND gate 112, second
NAND gate 113 and phase inverter 114.First d type flip flop 111 has Protection Counter Functions.The input terminal of the phase inverter 114 and institute
Data input pin N of the first input end as the sub- frequency unit 110 of the first NAND gate 112 is stated, the phase inverter 114
Output end connects the second input terminal of second NAND gate 113.Second input terminal of first NAND gate 112 and described
Preset number control terminal Ld of the first input end of two NAND gates 113 as the sub- frequency unit 110.First NAND gate
112 output end connects the reset signal input terminal of first d type flip flop 111.The output end of second NAND gate 113 connects
Connect the setting signal input terminal of first d type flip flop 111.
In the present embodiment, the sub- frequency unit 110 include the first d type flip flop 111, the first NAND gate 112, second with it is non-
Door 113 and phase inverter 114, realizing has the trigger of preset number function, and circuit overall complexity is low, and circuit scale is small, is convenient for
It realizes, and small power consumption.
In one embodiment, the control signal is configuration words signal.The control signal is described any for determining
The division range of integer frequency divider 10.The data bits of the configuration words signal can be arranged according to actual needs.The configuration
The data bits of word signal is more than or equal to 2.Assuming that the data bits of the configuration words signal is n, division range is 2- (2n-1)。
For example, then, the control signal is DIV<8:0>when the data bits of the configuration words signal is 9, the arbitrary integer frequency dividing
The division range 2- (2 of device 109- 1)=2-511 frequency dividing.
Fig. 4 is referred to, the logical operation module 200 is further described with reference to embodiments.Such as Fig. 4 institute
Show, the logical operation module 200 includes arithmetic element 210, resetting unit 220 and driving shaping unit 230.
The arithmetic element 210 includes first input end, the second input terminal and output end.The resetting unit 220 includes
Input terminal and output end.The driving shaping unit 230 includes input terminal and output end.The first of the arithmetic element 210 is defeated
Enter first input end of the end as the logical operation module 200, for receiving the second signal CLK_DIV.The operation
Second input terminal of second input terminal of unit 210 as the logical operation module 200, for receiving the third signal
CLK_OUT.Output end of the output end of the driving shaping unit 230 as the logical operation module 200.
The output end of the first input end of the arithmetic element 210 and the frequency division module 100, specifically, the operation
The first input end of unit 210 is separately connected the signal output end and reverse signal output end of each sub- frequency unit 110.Institute
The second input terminal for stating arithmetic element 210 connects the output end of the driving shaping unit 230.The arithmetic element 210 it is defeated
Outlet connects the input terminal of the resetting unit 220.The output end of the resetting unit 220 connects the driving shaping unit
230 input terminal.
The arithmetic element 210 carries out logical operation to the second signal CLK_DIV that the frequency division module 100 exports, defeated
M signal DFFLD_IN out.The resetting unit 220 and the driving shaping unit 230 are respectively to the M signal
DFFLD_IN is zeroed out, drives and shaping, exports the third signal CLK_OUT.The third signal CLK_OUT of output is returned
Input the arithmetic element 210.
The resetting unit 220 includes the second trigger 221, and second d type flip flop 221 is the effective D touching of failing edge
Send out device.The output end of the arithmetic element 210 connects the input terminal D of second d type flip flop 221.Second d type flip flop
221 output end connects the input terminal Q of the driving shaping unit 230.
In one embodiment, the driving shaping unit 230 may include phase inverter.The input terminal of the phase inverter with
The output end of the resetting unit 220 connects, output of the output end of the phase inverter as the logical operation module 200
End.
In one embodiment, the arithmetic element 210 is programmable logic arithmetic element.Programmable logic arithmetic element
At low cost, it is convenient to realize.Certainly, the logical operation module 200 can also entirely be designed as programmable logic computing module.In
In some other embodiments, the arithmetic element 210 or other structures with division function.
Fig. 5 is referred to, is come below by way of a specific example to the arithmetic element 210 and the arbitrary integer frequency divider
10 course of work is described in detail.In the present embodiment, it is assumed that the control signal is configuration words signal, the configuration words signal
Data bits is 9.The arbitrary integer frequency divider 10 can realize 2- (29- 1), i.e., 2 to 511 frequency dividing.The arithmetic element 210 is wrapped
Include 5 nor gates, 4 NAND gates, 1 d type flip flop and 3 points of phase inverters.The sub- frequency unit 110 that number is 0 to 8 is distinguished
Output signal q0-q8 is respectively connected to the input terminal of nor gate and NAND gate.By the operation of the arithmetic element 210, generate
The M signal DFFLD_IN.The signal input part of the M signal DFFLD_IN input effective d type flip flop of failing edge
D.The effective d type flip flop of failing edge filters out the spike that the M signal DFFLD_IN is generated in rising edge clock, In
When failing edge arrives, signal is exported to the driving shaping unit 230, the final third signal CLK_OUT is obtained.
Refer to Fig. 6, it is assumed that the data bits of the configuration words signal be 9, then the control signal DIV<n:0>=
000011101, divider ratio is 29 at this time, and each signal contrast schematic diagram is as shown in Figure 6.Q0~q8 is each sub- frequency dividing list in figure
The second signal CLK_DIV of member output, DFFLD_IN are the M signal, it is assumed that the first signal CLK_IN is
1GHz, then the third signal CLK_OUT is 1GHz/29=34.483MHz.
In addition, the application also provides a kind of phase-locked loop systems, including arbitrary integer frequency divider 10 as described above.At one
In specific embodiment, the phase-locked loop systems include phase frequency detector, filter, voltage controlled oscillator and the arbitrary integer point
Frequency device 10.The phase frequency detector, the filter and the voltage controlled oscillator form feedforward path, the arbitrary integer frequency dividing
The feedback network of 10 component frequency phase of device.After the arbitrary integer frequency divider 10 divides the frequency of the Voltage-Controlled oscillation circuit
Input the phase frequency detector, it is defeated that the phase difference of this clock and reference clock is converted to voltage signal by the phase frequency detector
Out, the control voltage that voltage controlled oscillator is formed after the filter filtering, to the frequency of the signal of voltage controlled oscillator output
Rate is modulated.Since the frequency dividing phase lock circuitry includes the arbitrary integer frequency divider 10, which has
All beneficial effects possessed by the arbitrary integer frequency divider 10.In addition, in the present embodiment, the arbitrary integer frequency divider 10
The third signal CLK_OUT high-level pulse width be it is fixed, pulse width be equal to first signal period.
In the phase-locked loop systems, the high-level pulse width of the output clock of feedback divider and input pre-divider is much smaller than clock
Period reduces locking phase in this way, the working time of phase frequency detector and level translator will shorten in each clock cycle
The function of loop system.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to the application the scope of the patents therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the concept of this application, various modifications and improvements can be made, these belong to the guarantor of the application
Protect range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of arbitrary integer frequency divider characterized by comprising frequency division module (100) and logical operation module (200)；
First input end of the first input end of the frequency division module (100) as the arbitrary integer frequency divider, for receiving
First signal；Second input terminal of second input terminal of the frequency division module (100) as the arbitrary integer frequency divider, is used for
Receive control signal；The output end of the frequency division module (100) connects the first input end of the logical operation module (200)；
Output end of the output end of the logical operation module (200) as the arbitrary integer frequency divider；The logical operation module
(200) output end connect the frequency division module (100) third input terminal and the logical operation module (200) it is second defeated
Enter end；
The frequency division module (100) carries out scaling down processing to first signal according to the control signal and generates second signal,
And the second signal is sent to the logical operation module (200)；The logical operation module (200) is to second letter
It number carries out generating after logical operation third signal and exporting, and the logical operation module (200) inputs the third signal
The frequency division module (100) and the logical operation module (200).
2. arbitrary integer frequency divider according to claim 1, which is characterized in that the frequency division module (100) includes multiple
Sub- frequency unit (110)；
Sub- frequency unit (110) control signal input connects non-inverting signal input thereof；The sub- frequency unit (110)
Signal output end connects the signal input part of sub- frequency unit (110) described in next stage；The sub- frequency unit (110) it is reversed
Signal output end connects the non-inverting signal input thereof of sub- frequency unit (110) described in next stage；
The signal input part of sub- frequency unit (110) described in the first order in the multiple sub- frequency unit (110) and reversed letter
Number first input end of the input terminal as the frequency division module (100), for receiving first signal；Each sub- frequency dividing list
Second input terminal of the data input pin of first (110) as the frequency division module (100), for receiving the control signal；Respectively
Third input terminal of the preset number control terminal of the sub- frequency unit (110) as the frequency division module (100), is separately connected institute
The output end for stating logical operation module (200), for receiving the third signal；The signal of each sub- frequency unit (110)
The output end of output end and reverse signal output end as the frequency division module (100), is all connected with the logical operation module
(200) first input end, for exporting the second signal.
3. arbitrary integer frequency divider according to claim 2, which is characterized in that the sub- frequency unit (110) includes the
One d type flip flop (111), the first NAND gate (112), the second NAND gate (113) and phase inverter (114), the phase inverter (114)
The data input pin of input terminal and the first input end of first NAND gate (112) as the sub- frequency unit (110), institute
The output end for stating phase inverter (114) connects the second input terminal of second NAND gate (113)；First NAND gate (112)
The second input terminal and second NAND gate (113) preset number of the first input end as the sub- frequency unit (110)
Control terminal；The output end of first NAND gate (112) connects the reset signal input terminal of first d type flip flop (111), institute
The output end for stating the second NAND gate (113) connects the setting signal input terminal of first d type flip flop (111).
4. arbitrary integer frequency divider according to claim 2, which is characterized in that the control signal is configuration words signal.
5. arbitrary integer frequency divider according to claim 4, which is characterized in that the data bits of the configuration words signal is big
In equal to 2.
6. arbitrary integer frequency divider according to any one of claims 2 to 5, which is characterized in that when the third signal is
When high level, sub- frequency unit (110) work is in preset number state, the signal output end of the sub- frequency unit (110)
The value of output is equal to the value of data input pin input；When the third signal is low level, the sub- frequency unit (110)
The value of signal output end output is equal to the value of control signal input input.
7. arbitrary integer frequency divider according to claim 1, which is characterized in that the logical operation module (200) includes
Arithmetic element (210), resetting unit (220) and driving shaping unit (230)；
First input end of the first input end of the arithmetic element (210) as the logical operation module (200), the fortune
The input terminal for calculating unit (210) connects the output end of the frequency division module (100), for receiving the second signal；The fortune
The output end for calculating unit (210) connects the input terminal of the resetting unit (220)；The output end of the resetting unit (220) connects
Connect the input terminal of driving shaping unit (230)；The output end of driving shaping unit (230) is as the logical operation
The output end of module (200)；Second input terminal of the arithmetic element (210) as the logical operation module (200)
The output end of two input terminals, driving shaping unit (230) connects the second input terminal of the arithmetic element (210).
8. arbitrary integer frequency divider according to claim 7, which is characterized in that the resetting unit (220) includes the 2nd D
Trigger (221), second d type flip flop (221) are the effective d type flip flop of failing edge, the output of the arithmetic element (210)
End connects the input terminal of second d type flip flop (221)；The output end connection driving of second d type flip flop (221) is whole
The input terminal of shape unit (230).
9. arbitrary integer frequency divider according to claim 7, which is characterized in that the arithmetic element (210) is programmable
Logical unit.
10. a kind of phase-locked loop systems, which is characterized in that divided including arbitrary integer as described in any one of claim 1 to 9
Device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112235012A (en) * | 2020-09-28 | 2021-01-15 | 苏州锐迪联电子科技有限公司 | Intercom frequency division chip |
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| CN210578497U (en) * | 2019-09-09 | 2020-05-19 | 广东华芯微特集成电路有限公司 | Arbitrary integer frequency divider and phase-locked loop system |
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| US4357527A (en) * | 1978-01-31 | 1982-11-02 | Tokyo Shibaura Denki Kabushiki Kaisha | Programmable divider |
| US4468797A (en) * | 1981-02-13 | 1984-08-28 | Oki Electric Industry Co., Ltd. | Swallow counters |
| US5640116A (en) * | 1993-03-18 | 1997-06-17 | Fujitsu Limited | PLL circuit of pulse swallow-type prescaler system |
| US6041093A (en) * | 1997-08-22 | 2000-03-21 | Lg Semicon Co., Ltd. | Variable frequency dividing circuit |
| US6411669B1 (en) * | 2000-05-25 | 2002-06-25 | C&S Technology Co., Ltd. | Dual-modulus prescaler for RF synthesizer |
| US20080297209A1 (en) * | 2007-05-31 | 2008-12-04 | Jeremy Scuteri | Circuits and Methods for Programmable Integer Clock Division with 50% Duty Cycle |
| CN103684425A (en) * | 2012-09-12 | 2014-03-26 | 比亚迪股份有限公司 | Dual-mode frequency divider circuit |
| CN103312319A (en) * | 2013-05-23 | 2013-09-18 | 江苏天源电子有限公司 | Spurious suppression phase frequency detector circuit applied to integer fractional frequency phase-locked loop |
| US20180109266A1 (en) * | 2016-10-19 | 2018-04-19 | Stmicroelectronics International N.V. | Programmable Clock Divider |
| KR20190062136A (en) * | 2017-11-28 | 2019-06-05 | 삼성전자주식회사 | Frequency divider and transceiver including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112235012A (en) * | 2020-09-28 | 2021-01-15 | 苏州锐迪联电子科技有限公司 | Intercom frequency division chip |
| CN112235012B (en) * | 2020-09-28 | 2022-05-31 | 苏州锐迪联电子科技有限公司 | Intercom frequency division chip |
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