CN107565956A - Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit - Google Patents
Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit Download PDFInfo
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Abstract
Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit, it is related to microelectronic chip design field.It is to solve the problems, such as the loop switching circuit complexity of clock data recovery circuit.The present invention is applied to the VCO frequency band switching circuits in double loop clock data recovery circuit, two clock counters are respectively used to reference clock and VCO output clock counts, the loop selection signal that the count value that results contrast circuit is used to be obtained according to two clock counters adjusts the frequency band control word of band count device output and d type flip flop exports, one signal input part of the input OR gate of reset signal output end connection two of results contrast circuit, the reset signal input of band count device, another input of two input OR gates and the reset signal input of d type flip flop gather the reset signal of outside input simultaneously.The present invention is adapted to carry out the frequency band switching and loop switching of the VCO in double loop clock data recovery circuit.
Description
Technical field
The invention belongs to microelectronic chip design field.
Background technology
Clock data recovery circuit is widely used in the fields such as data communication.Clock data recovery circuit master
It is divided into the clock data recovery circuit based on PLL structures and the clock data recovery circuit based on PI structures, wherein based on PLL
The clock data recovery circuit of structure can be divided into single loop and double loop again.The clock data recovery circuit of double loop includes lock
Frequency loop and phase-locked loop, wherein frequency-locked loop include phase frequency detector, charge pump, low pass filter, VCO (voltage controlled oscillator)
And its frequency band switching circuit and alternative circuit, phase-locked loop include VCO and its frequency band switching circuit, BBPD, charge pump, low pass
Wave filter and alternative circuit, in addition double loop also need to the switching that lock detecting circuit realizes loop, its circuit structure is very
It is complicated.
The content of the invention
The present invention is to solve the problems, such as that the loop switching circuit of clock data recovery circuit is extremely complex, and now providing should
For the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit.
Applied to the VCO frequency band switching circuits in double loop clock data recovery circuit, including：Two clock counters,
Results contrast circuit, band count device, two input OR gates and d type flip flop；
Two clock counters are respectively used to reference clock and VCO output clock counts,
The count value that results contrast circuit is used to be obtained according to two clock counters adjusts the frequency that band count device exports
The loop selection signal exported with control word and d type flip flop,
When the count value of reference clock is more than the count value of VCO output clocks and the arrival of results contrast circuit output clock
When, the frequency band control word increase of results contrast circuit control band count device output,
When the count value of reference clock is less than the count value of VCO output clocks and the arrival of results contrast circuit output clock
When, the frequency band control word of results contrast circuit control band count device output reduces,
When the count value of reference clock is equal to the count value of VCO output clocks and the arrival of results contrast circuit output clock
When, results contrast circuit control d type flip flop output phase-locked loop selection signal,
One signal input part of the input OR gate of reset signal output end connection two of results contrast circuit, band count device
Reset signal input, another input of two input OR gates and the reset signal input of d type flip flop gather simultaneously it is outer
The reset signal of portion's input.
Applied to the loop switching method of the VCO frequency band switching circuits in double loop clock data recovery circuit, including lock
Frequency lock phase switching method and lock phase frequency locking switching method,
Frequency locking lock phase switching method is carried out under frequency-locked loop working condition, the described method comprises the following steps：
Step 1：Clock count is exported to reference clock and VCO respectively using two clock counters 1,
Step 2：The count value obtained using results contrast circuit 2 to two clock counters 1 is compared,
When the count value of reference clock is more than the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, results contrast circuit 2 controls the frequency band control word increase of the output of band count device 3, is then back to step 1,
When the count value of reference clock is less than the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, results contrast circuit 2 controls the frequency band control word of the output of band count device 3 to reduce, and is then back to step 1,
When the count value of reference clock is equal to the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, frequency-locked loop is switched to phase-locked loop by the output control signal of d type flip flop 5, is completed frequency locking lock and is mutually switched；
Lock phase frequency locking switching method is carried out under phase-locked loop working condition, the described method comprises the following steps：
Step 1：Clock count is exported to reference clock and VCO respectively using two clock counters 1,
Step 2：The count value obtained using results contrast circuit 2 to two clock counters 1 is compared,
When the count value of reference clock is equal to the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, frequency band control word and the output control signal of d type flip flop 5 that band count device 3 exports keep constant, are then back to step 1,
When the count value of reference clock is less than or greater than the count value of VCO output clocks and results contrast circuit 2 exports
When clock arrives, phase-locked loop is switched to frequency-locked loop by the output control signal of d type flip flop 5, completes the frequency locking switching of lock phase.
In order to reduce the complexity of the loop switching circuit of existing clock data recovery circuit, the application by VCO frequency
The function of loop switching is realized with switching circuit, so just eliminates lock detecting circuit, and frequency band of the present invention in VCO is locked
Just realize that loop switches after fixed, and it is unrelated with VCO control voltage, therefore phase frequency detector and charge pump can also be saved, only
VCO control voltage is adjusted in phase-locked loop.The frequency-locked loop of the present invention is only comprising VCO and its frequency band switching circuit and two choosings
One circuit, loop switching signal can be generated while VCO frequency band control word is generated, have the work(of lock detecting circuit concurrently
Can, lock detecting circuit can be saved, effectively reduces complexity in circuits.Meanwhile frequency band switching circuit passes through counter
To 2 clock counts, the frequency of 2 clocks is compared by count value, and then frequency band is adjusted.The present invention is by long number
Compare the complexity for simplifying and for 1 digit, further reducing circuit.
Brief description of the drawings
Fig. 1 is the structural representation of the VCO frequency band switching circuits described in embodiment one；
Fig. 2 is the structural representation of the results contrast circuit described in embodiment two；
Fig. 3 is the schematic diagram that VCO frequency bands switching circuit of the present invention is applied to double loop clock data recovery circuit；
Fig. 4 is the simulation result curve map of frequency band switching circuit.
Embodiment
Embodiment one：Reference picture 1 illustrates present embodiment, is applied to double loop described in present embodiment
VCO frequency band switching circuits in clock data recovery circuit, including：Two clock counters 1, results contrast circuit 2, frequency band meter
Number device 3, two inputs OR gate 4 and d type flip flop 5；
Two clock counters 1 are respectively used to count reference clock clk_ref and VCO output clock clk, the meter of output
Numerical value is denoted as A [0 respectively:N-1] and B [0:N-1], wherein n is the digit of clock counter 1,
The count value that results contrast circuit 2 is used to be obtained according to two clock counters 1 adjusts the output of band count device 3
The loop selection signal that frequency band control word and d type flip flop 5 export, specifically：
The up signal input parts of the up signal output parts connection band count device 3 of results contrast circuit 2, results contrast circuit
The down signal input parts of 2 down signal output parts connection band count device 3, the equal signal outputs of results contrast circuit 2
The D inputs of end connection d type flip flop 5, the clk_band clock signal output terminals of results contrast circuit 2 connect band count simultaneously
The clock signal input terminal of device 3 and the input end of clock of d type flip flop 5, the rst_comp reset signals output of results contrast circuit 2
One signal input part of the input OR gate 4 of end connection two, up signal output parts, down signal output parts and equal signal outputs
End is referred to as the comparative result signal output part of results contrast circuit 2,
When reference clock clk_ref count value is more than VCO output clocks clk count value and the arrival of clk_band clocks
When, up signal output parts output " 1 ", the frequency band control word s [0 that band count device 3 exports:M-1] increase, wherein m is frequency band meter
The digit of number device,
When reference clock clk_ref count value is less than VCO output clocks clk count value and the arrival of clk_band clocks
When, down signal output parts output " 1 ", the frequency band control word s [0 that band count device 3 exports:M-1] reduce,
When reference clock clk_ref count value is equal to VCO output clocks clk count value and the arrival of clk_band clocks
When, it is " 1 " that d type flip flop 5, which exports lock signals, and lockn signals are " 0 ", i.e.,：D type flip flop 5 exports phase-locked loop selection signal,
Frequency-locked loop is switched into phase-locked loop,
Above-mentioned clk_band clocks are that results contrast circuit 2 exports clock,
Another input and d type flip flop 5 of the rst reset signals input of band count device 3, two input OR gates 4
Rst reset signals input gathers rst reset signals simultaneously, and when band count device 3 collects rst reset signals, it is exported
Frequency band control word reset, the rst_ that the two rst reset signals that gathers of input OR gates 4 and results contrast circuit 2 export
Comp reset signals carry out OR operation, and the rst_counter reset signals of output are used to answer two clock counters 1
Position, when d type flip flop 5 collects rst reset signals, it is " 0 " that d type flip flop 5, which resets and exports lock signals, and lockn signals are
" 1 ", phase-locked loop switch to frequency-locked loop, the reset signal that rst reset signals are an externally input, the reset signal of outside input
Directly control the reset of whole circuit.
In practical operation, as shown in figure 3, the frequency band control word output end of band count device 3 and VCO frequency band control word are defeated
Enter end connection, realize multiband VCO frequency band adjustments, the lock signal output parts and lockn signal output parts point of d type flip flop 5
It is not connected with the positive control terminal of alternative circuit and Reverse Turning Control end, realizes the switching between phase-locked loop and frequency-locked loop.
Embodiment two：Reference picture 2 illustrates present embodiment, and present embodiment is to embodiment one
The described VCO frequency band switching circuits being applied in double loop clock data recovery circuit are described further, present embodiment
In, results contrast circuit 2 includes：2 n-1 input OR gates, 21,2 sub- d type flip flops 22, comparator 23, sampled signal and reset
Signal generating circuit 24 and phase inverter time delay chain 25；
2 n-1 input OR gates 21 are respectively used to gather the n-1 positions count value A [0 of two clock counters 1:N-2] and B
[0:N-2], the output end of 2 n-1 input OR gates 21 connects the D inputs of 2 sub- d type flip flops 22 respectively, and comparator 23 is used for
The output signal of 2 sub- d type flip flops 22 is gathered,
Sampled signal and reset signal generative circuit 24 are used for the output signal (a and b) for gathering 2 n-1 input OR gates 21
With two highest order count values of clock counter 1 (A [n-1] and B [n-1]), sampled signal and reset signal generative circuit 24
Sample sampled signals output end connects the input end of clock of 2 sub- d type flip flops 22, sampled signal and reset signal generation simultaneously
The signal input part of the rst_comp reset signals output end connection phase inverter time delay chain 25 of circuit 24 is simultaneously more electric as a result
The rst_comp reset signal output ends on road 2, the up signals of three output ends of comparator 23 while as a result comparison circuit 2
Output end, down signal output parts and equal signal output parts, the clk_band clock signal output terminals of phase inverter time delay chain 25
The clk_band clock signal output terminals of comparison circuit 2 as a result.
Results contrast circuit 2 is when the highest order of two clock counters 1 is all to become " 1 ", to two clock counters 1
As a result it is compared, now at least one clock counter 1 is in addition to highest order, and remaining position is all " 0 ", if another clock count
Remaining position of device 1 is also all " 0 ", then the result of two clock counters 1 is equal, otherwise remaining position be all " 0 " result it is small.Will
The low level result of two clock counters 1 is after OR gate, it can be determined that whether low level is all " 0 ", if the input of OR gate is all
" 0 ", then output is " 0 ", is otherwise " 1 ".So just the comparison of long number is changed for the comparison of 1 digit, reduces circuit
Complexity.
The output signal a and b that 2 sub- d type flip flops 22 of results contrast circuit 2 input OR gate 21 to n-1 are sampled
When, it is ensured that a and b at least one is " 0 ", and this just needs sampled signal and reset signal generative circuit 24 to produce suitably
Sample sampled signals, i.e., when the highest order of two clock counters 1 is all " 1 ", and when the output of OR gate is not all " 1 ",
Sample sampled signals are generated, sample output of 2 sub- d type flip flops 22 to OR gate.
Rst_comprst_comp reset signals are generated clk_band by phase inverter time delay chain 25 by enough delays
Clock signal, the rising edge of clk_band clock signals is set just to be produced after up, down signal reach band count device 3.
Embodiment three：Reference picture 2 illustrates present embodiment, and present embodiment is to embodiment two
The described VCO frequency band switching circuits being applied in double loop clock data recovery circuit are described further, present embodiment
In, sampled signal and reset signal generative circuit 24 include an AND gate 241, two AND gates 242 and NAND gate 243,
Two inputs of NAND gate 243 connect the signal output part of 2 n-1 input OR gates 21 respectively, NAND gate 243
Output end connects an input of two AND gates 242,
One AND gate 241 is used to gather two highest order count values of clock counter 1, and the output end of an AND gate 241 is same
When connect another input of two AND gates 242 and the signal input part of phase inverter time delay chain 25, and as sampled signal and
The rst_comp reset signal output ends of reset signal generative circuit 24,
The signal output part of two AND gates 242 samples as the sample of sampled signal and reset signal generative circuit 24 to be believed
Number output end.
Embodiment four：The VCO being applied in double loop clock data recovery circuit frequencies described in present embodiment
Loop switching method with switching circuit, including frequency locking lock phase switching method and lock phase frequency locking switching method；
Frequency locking lock phase switching method is carried out under frequency-locked loop working condition, the described method comprises the following steps：
Step 1：Clock clk is exported using two clock counters 1 to reference clock clk_ref and VCO respectively to count,
Step 2：The count value obtained using results contrast circuit 2 to two clock counters 1 is compared,
When reference clock clk_ref count value is more than VCO output clocks clk count value and the arrival of clk_band clocks
When, up signal output parts output " 1 ", the frequency band control word s [0 that band count device 3 exports:M-1] increase, it is then back to step
One, wherein m are the digit of band count device,
When reference clock clk_ref count value is less than VCO output clocks clk count value and the arrival of clk_band clocks
When, down signal output parts output " 1 ", the frequency band control word s [0 that band count device 3 exports:M-1] reduce, it is then back to step
One,
When reference clock clk_ref count value is equal to VCO output clocks clk count value and the arrival of clk_band clocks
When, it is " 1 " that d type flip flop 5, which exports lock signals, and lockn signals are " 0 ", and frequency-locked loop is switched into phase-locked loop, completes frequency locking
Lock mutually switches；
Lock phase frequency locking switching method is carried out under phase-locked loop working condition, the described method comprises the following steps：
Step 1：Clock count is exported to reference clock and VCO respectively using two clock counters 1,
Step 2：The count value obtained using results contrast circuit 2 to two clock counters 1 is compared,
When the count value of reference clock is equal to the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, frequency band control word and the output control signal of d type flip flop 5 that band count device 3 exports keep constant, are then back to step 1,
When the count value of reference clock is more than the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, results contrast circuit 2 controls the frequency band control word increase of the output of band count device 3, and the output control signal of d type flip flop 5 will lock
Phase loop switches to frequency-locked loop, completes the frequency locking switching of lock phase,
When the count value of reference clock is less than the count value of VCO output clocks and the output clock arrival of results contrast circuit 2
When, results contrast circuit 2 controls the frequency band control word of the output of band count device 3 to reduce, and the output control signal of d type flip flop 5 will lock
Phase loop switches to frequency-locked loop, completes the frequency locking switching of lock phase.
Embodiment five：Present embodiment is to being applied to double loop clock data described in embodiment four
The loop switching method of VCO frequency band switching circuits in restoring circuit is described further, in present embodiment,
Also include repositioning method, methods described is：
Rst reset signals input, another input and d type flip flop 5 of two input OR gates 4 to band count device 3
Rst reset signals input simultaneously send rst reset signals,
The frequency band control word that band count device 3 exports to it resets,
Two input OR gates 4 reset to two clock counters 1,
It is " 0 " that d type flip flop 5, which resets and exports lock signals, and lockn signals are " 1 ", and it is frequency-locked loop work to make original state
Make state, complete to reset.
Embodiment example：
The frequency of the reference clock of the present embodiment is 3.125GHz, VCO totally 8 frequency bands, frequency band be " 011 ", control electricity
3.125GHz clock is exported when pressure is about 580mV, clock counter is 7, and band count device is 3, and supply voltage is
1.2V.The present embodiment is as shown in figure 3, because eliminate the phase frequency detector and charge pump in frequency-locked loop, by electric resistance partial pressure electricity
Road provides the VCO control voltages in frequency locking stage.Simulation result is as shown in Figure 4.
Original state：State after two clock counters 1, band count device 3 and d type flip flop 5 reset is original state,
Now, the VCO frequency band control words s [0 that band count device 3 exports:2] it is " 000 ", the lock signals of d type flip flop 5 are " 0 ",
Lockn signals are " 1 ", and frequency-locked loop works, and phase-locked loop does not work.Two clock counters 1 in frequency band switching circuit
As a result 0 is all reset to, up the and down signals of results contrast circuit 2 are also reset to 0.
When frequency-locked loop works：Lock signals are " 0 ", and lockn signals are " 1 ", whenever the highest order A of clock counter
[6] when and B [6] (count1 [6] and count2 [6] in Fig. 4) is changed into 1, up and down signals just become according to comparative result
To change, VCO frequency band control word also produces corresponding change, as shown in figure 4, because up signals are " 1 " always, VCO frequency band control
Word processed just constantly increases, and untill being changed into " 011 ", now VCO output frequency close to the frequency of reference clock, cut by frequency band
It is " 1 " to change circuit output lock signals, and lockn signals are " 0 ", and frequency-locked loop work is completed, and phase-locked loop is started working.
When phase-locked loop works：Lock signals are " 1 ", and lockn signals are " 0 ", and now VCO frequency band control word is kept
" 011 " is constant.
Two clock counters 1 are respectively intended to count reference clock clk_ref and VCO output clock clk；As a result
Comparison circuit is compared to the result of clock counter, and exports up, down and equal signal, wherein up and down signals
For controlling the plus-minus of band count device, equal signals export lock and lockn signals after d type flip flop preserves, as
The signal of frequency band locking, while for controlling the switching of CDR loops；Band count device when clock arrives, according to the up of input,
Down signals carry out plus-minus operation, export VCO frequency band control word, and OR gate is used to obtain the reset signal of clock counter, and D is touched
Hair device then ensure that the original state of the lock after resetting is " 0 ", and frequency-locked loop works.
The digit of clock counter has influence on the precision of frequency detecting：
2N|Tref-Tb|≤Tref
Wherein, N be clock counter digit, TrefAnd TbThe respectively cycle of reference clock and VCO clocks.According to VCO
Simulation result, N takes 6, and because counter needs highest order to represent carry, the digit of counter is set to 7.
Results contrast circuit is as shown in Fig. 2 results contrast circuit receives prime clock counter by 26 input OR gates
6 A [0 afterwards:5] and B [0:5], 0 is all as inputted, then exports 0, otherwise export 1；When sampled signal arrives, d type flip flop will
As a result simultaneously latch result is received.Result after latch obtains up, down and equal signal by comparator.
Because when the highest order A [6] and B [6] of clock counter are " 1 ", just the value of two clock counters is carried out
Compare, so now latter 6 of wherein at least 1 counter are all " 0 ".If A [0:5] it is all " 0 ", and B [0:5] it is not all
" 0 ", then A<B；If A [0:5] it is not all " 0 ", and B [0:5] " 0 " is all, then A>B；If A [0:5] it is all " 0 ", and B [0:5]
" 0 " is all, then A=B.
Sampled signal and reset signal generative circuit are as shown in Figure 2.The highest order of two clock counters is passed through with obtaining behind the door
To rst_comp signals, because the delay that the signal passes through is shorter than the delay of 6 input OR gates, by the use of the signal adopting as d type flip flop
Sample clock will be unable to obtain correct result, so be all " 1 " in A [6] and B [6], and the output a and b of two 6 input OR gates are not
Sampled signal sample is just exported when being all " 0 ", d type flip flop is received data, can so ensure the data received at least
It is " 0 " to have 1；In addition, rst_comp signals also serve as the reset signal of clock counter.Rst_comp signals pass through phase inverter
Clock signals of the clk_band as band count device is exported after time delay chain, after making up, down signal arrival band count device
Clock clk_band is just provided.
Claims (5)
1. applied to the VCO frequency band switching circuits in double loop clock data recovery circuit, it is characterised in that including：At two
Clock counter (1), results contrast circuit (2), band count device (3), two input OR gates (4) and d type flip flop (5)；
Two clock counters (1) are respectively used to reference clock and VCO output clock counts,
The count value that results contrast circuit (2) is used to be obtained according to two clock counters (1) adjusts band count device (3) output
Frequency band control word and d type flip flop (5) output loop selection signal,
When the count value of reference clock is more than the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
The frequency band control word increase of results contrast circuit (2) control band count device (3) output,
When the count value of reference clock is less than the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
The frequency band control word of results contrast circuit (2) control band count device (3) output reduces,
When the count value of reference clock is equal to the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
Results contrast circuit (2) control d type flip flop (5) output phase-locked loop selection signal,
One signal input part of the input OR gate (4) of reset signal output end connection two of results contrast circuit (2), band count
The reset signal input of the reset signal input of device (3), another input of two input OR gates (4) and d type flip flop (5)
The reset signal of outside input is gathered simultaneously.
2. the VCO frequency band switching circuits according to claim 1 being applied in double loop clock data recovery circuit, it is special
Sign is,
Results contrast circuit (2) includes：2 n-1 input OR gates (21), 2 sub- d type flip flops (22), comparator (23), sampling letter
Number and reset signal generative circuit (24) and phase inverter time delay chain (25)；
2 n-1 input OR gates (21) are respectively used to gather the n-1 positions count value of two clock counters (1), 2 n-1 inputs or
The output end of door (21) connects the D inputs of 2 sub- d type flip flops (22) respectively, and comparator (23) is used to gather 2 sub- D triggerings
The output signal of device (22),
Sampled signal and reset signal generative circuit (24) are for the output signal of 2 n-1 input OR gates (21) of collection and two
The sampled signal output end of clock counter (1) highest order count value, sampled signal and reset signal generative circuit (24) is simultaneously
Connect the input end of clock of 2 sub- d type flip flops (22), the reset signal output of sampled signal and reset signal generative circuit (24)
The signal input part of end connection phase inverter time delay chain (25) and as a result the reset signal output end of comparison circuit (2), compare
The comparative result signal output part of three output ends of device (23) while as a result comparison circuit (2), phase inverter time delay chain
(25) clock signal output terminal of clock signal output terminal comparison circuit (2) as a result.
3. the VCO frequency band switching circuits according to claim 2 being applied in double loop clock data recovery circuit, it is special
Sign is,
Sampled signal and reset signal generative circuit (24) include an AND gate (241), two AND gates (242) and NAND gate
(243),
Two inputs of NAND gate (243) connect the signal output part of 2 n-1 input OR gates (21), NAND gate (243) respectively
Output end connect two AND gates (242) an input,
One AND gate (241) is used to gather two clock counter (1) highest order count values, the output end of an AND gate (241)
Another input of two AND gates (242) and the signal input part of phase inverter time delay chain (25) are connected simultaneously, and as sampling
The reset signal output end of signal and reset signal generative circuit (24),
The signal output part of two AND gates (242) exports as sampled signal and the sampled signal of reset signal generative circuit (24)
End.
4. the loop of the VCO frequency band switching circuits being applied in double loop clock data recovery circuit described in claim 1 is cut
Change method, including frequency locking lock phase switching method and lock phase frequency locking switching method, it is characterised in that
Frequency locking lock phase switching method is carried out under frequency-locked loop working condition, the described method comprises the following steps：
Step 1：Clock count is exported to reference clock and VCO respectively using two clock counters (1),
Step 2：The count value obtained using results contrast circuit (2) to two clock counters (1) is compared,
When the count value of reference clock is more than the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
The frequency band control word increase of results contrast circuit (2) control band count device (3) output, is then back to step 1,
When the count value of reference clock is less than the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
The frequency band control word of results contrast circuit (2) control band count device (3) output reduces, and is then back to step 1,
When the count value of reference clock is equal to the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
Frequency-locked loop is switched to phase-locked loop by d type flip flop (5) output control signal, is completed frequency locking lock and is mutually switched；
Lock phase frequency locking switching method is carried out under phase-locked loop working condition, the described method comprises the following steps：
Step 1：Clock count is exported to reference clock and VCO respectively using two clock counters (1),
Step 2：The count value obtained using results contrast circuit (2) to two clock counters (1) is compared,
When the count value of reference clock is equal to the count value of VCO output clocks and results contrast circuit (2) output clock arrives,
The frequency band control word and d type flip flop (5) output control signal of band count device (3) output keep constant, are then back to step 1,
When the count value of reference clock is less than or greater than the count value of VCO output clocks and results contrast circuit (2) output clock
During arrival, phase-locked loop is switched to frequency-locked loop by d type flip flop (5) output control signal, completes the frequency locking switching of lock phase.
5. the ring of the VCO frequency band switching circuits according to claim 4 being applied in double loop clock data recovery circuit
Road switching method, it is characterised in that it also includes repositioning method, and methods described is：
Reset signal input to band count device (3), another input of two input OR gates (4) and d type flip flop (5)
Reset signal input sends reset signal simultaneously,
The frequency band control word that band count device (3) exports to it resets, and two input OR gates (4) enter to two clock counters (1)
Row resets, and d type flip flop (5) resets and output control signal makes original state be frequency-locked loop working condition, completes to reset.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110244588A (en) * | 2018-03-09 | 2019-09-17 | 华大半导体有限公司 | Multifunctional timer |
| CN110635800A (en) * | 2019-09-20 | 2019-12-31 | 上海华力微电子有限公司 | Frequency comparison-based locking indicating circuit and method applied to phase-locked loop |
| CN112187257A (en) * | 2020-10-16 | 2021-01-05 | 广西师范大学 | High-speed low-jitter data synchronous phase discriminator |
| CN112532214A (en) * | 2020-11-12 | 2021-03-19 | 成都芯源系统有限公司 | Detection method and circuit for judging whether clock signal is accurate or not |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290443A (en) * | 1997-12-05 | 2001-04-04 | 特尔科迪亚技术股份有限公司 | Method and apparatus for variable bit rate clock recovery |
| US6747518B1 (en) * | 2002-12-30 | 2004-06-08 | Broadcom Corporation | CDR lock detector with hysteresis |
| US20050174185A1 (en) * | 2004-02-10 | 2005-08-11 | Steinbach Guntor W. | Centering a multi-band voltage controlled oscillator |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
-
2017
- 2017-09-22 CN CN201710866316.2A patent/CN107565956B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290443A (en) * | 1997-12-05 | 2001-04-04 | 特尔科迪亚技术股份有限公司 | Method and apparatus for variable bit rate clock recovery |
| US6747518B1 (en) * | 2002-12-30 | 2004-06-08 | Broadcom Corporation | CDR lock detector with hysteresis |
| US20050174185A1 (en) * | 2004-02-10 | 2005-08-11 | Steinbach Guntor W. | Centering a multi-band voltage controlled oscillator |
| CN104485947A (en) * | 2014-12-30 | 2015-04-01 | 中南民族大学 | Digital phase discriminator used for GPS tame crystal oscillator |
Non-Patent Citations (1)
| Title |
|---|
| YONGSHENG WANG等: "A 12.5Gbps dual loop quarter rate CDR using lock detecting technique in 55nm CMOS process", 《2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110244588A (en) * | 2018-03-09 | 2019-09-17 | 华大半导体有限公司 | Multifunctional timer |
| CN110244588B (en) * | 2018-03-09 | 2022-04-05 | 华大半导体有限公司 | Multifunctional timer |
| CN110635800A (en) * | 2019-09-20 | 2019-12-31 | 上海华力微电子有限公司 | Frequency comparison-based locking indicating circuit and method applied to phase-locked loop |
| CN110635800B (en) * | 2019-09-20 | 2023-05-23 | 上海华力微电子有限公司 | Locking indication circuit and method applied to phase-locked loop and based on frequency comparison |
| CN112187257A (en) * | 2020-10-16 | 2021-01-05 | 广西师范大学 | High-speed low-jitter data synchronous phase discriminator |
| CN112532214A (en) * | 2020-11-12 | 2021-03-19 | 成都芯源系统有限公司 | Detection method and circuit for judging whether clock signal is accurate or not |
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| CN107565956B (en) | 2020-06-30 |
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