CN107294531A - Phase-locked loop and frequency divider - Google Patents
Phase-locked loop and frequency divider Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
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Abstract
The invention provides a kind of phase-locked loop and frequency divider.Above-mentioned phase-locked loop includes difference sigma modulator, decoder and frequency divider.Above-mentioned decoder couples above-mentioned difference sigma modulator, and produce intermediate division than integer-bit and intermediate division than decimal place.Above-mentioned frequency divider couples above-mentioned decoder, with receive above-mentioned intermediate division than integer-bit and above-mentioned intermediate division ratio decimal place.Above-mentioned frequency divider switches to integral frequency divisioil pattern or fractional frequency division pattern according to control signal.
Description
Technical field
The invention mainly relates to a phase-locked loop technology, accumulated more particularly to by decimal frequency divider is switched to reducing difference
Divide the phase-locked loop technology of the introduced quantizing noise of modulator (Delta-Sigma Modulator, DSM).
Background technology
Phase-locked loop (phase locked loop, PLL) circuit is a kind of feedback control system, and it is generally used
In integrated circuit and electronic installation.Phase-locked loop major function is the frequency of oscillation for changing voltage controlled oscillator, makes feedback letter
Number go to follow the trail of the phase of reference signal, to enable feedback signal and reference signal to reach the synchronization of frequency and phase.
Fig. 1 is the block diagram for showing traditional phase-locked loop 100.As shown in figure 1, can be wrapped in traditional phase-locked loop 100
Phase frequency detector (Phase Frequency Detector, PFD) 110, charge pump (Charge Pump, CP) 120, ring are included
It is path filter (Loop Filter, LF) 130, voltage controlled oscillator (Voltage Control Oscillator, VCO) 140, poor
Different sigma modulator (Delta-Sigma Modulator, DSM) 150 and frequency divider (Frequency Divider) 160.
As shown in figure 1, traditional phase-locked loop can add difference sigma modulator.The effect of difference sigma modulator be with
Higher speed is sampled, and the numeral output changed in a certain interval is exported according to the type of the difference sigma modulator
Value, the frequency dividing ratio input signal using the digital output value of the change as integer frequency divider carries out integral frequency divisioil again and again,
Clock signal FBCLK is set to level off to the input clock signal FIN of phase-locked loop by accumulation.Difference sigma modulator will also quantify
Noise pushes high frequency to, it is easily low pass filtering device and is filtered, but because integer frequency divider has certain low pass special in itself
Property, the quantizing noise of high frequency is no longer handled furthermore with low pass filter so general, so use difference sigma modulator
Phase-locked loop still has substantial amounts of quantizing noise, influences the efficiency of phase-locked loop.
The content of the invention
In view of above-mentioned problem of the prior art, the invention provides accumulated by decimal frequency divider is switched to reducing difference
Divide the method for the phase-locked loop and reduction quantizing noise of the introduced quantizing noise of modulator.
A kind of phase-locked loop is provided according to one embodiment of the invention.Above-mentioned phase-locked loop includes difference quadrature modulates
Device, decoder and frequency divider.Above-mentioned decoder couples above-mentioned difference sigma modulator, and produce intermediate division than integer
Position and intermediate division than decimal place.Above-mentioned frequency divider couples above-mentioned decoder, with receive above-mentioned intermediate division than integer
Position and the decimal place of above-mentioned intermediate division ratio.Above-mentioned frequency divider switches to integral frequency divisioil pattern or fractional frequency division according to control signal
Pattern.
According to some embodiments of the invention, above-mentioned decoder includes the first decoder and the second decoder.First decoder
Above-mentioned difference sigma modulator is coupled, and produces the input signal of above-mentioned difference sigma modulator.The coupling of second decoder is above-mentioned
Difference sigma modulator, the output signal for receiving above-mentioned difference sigma modulator, and produce above-mentioned intermediate division than integer
Position and the decimal place of above-mentioned intermediate division ratio.According to some embodiments of the invention, the first decoding utensil mlultiplying circuit, and above-mentioned
Second decoder has division circuit.
According to some embodiments of the invention, above-mentioned frequency divider includes integer frequency divider and divider clock generation circuit.
Integer frequency divider receive above-mentioned intermediate division than integer-bit.Divider clock generation circuit receive above-mentioned intermediate division than it is small
Numerical digit, and above-mentioned control signal.
One embodiment of the invention provides a kind of frequency divider.When above-mentioned frequency divider includes integer frequency divider and frequency divider
Clock generation circuit.Integer frequency divider receive intermediate division than integer-bit.Divider clock generation circuit is coupled to above-mentioned integer
Frequency divider, and receive intermediate division than decimal place and control signal.
One embodiment of the invention provides a kind of method for reducing quantizing noise.The method of above-mentioned reduction quantizing noise is fitted
For phase-locked loop.The step of method of above-mentioned reduction quantizing noise, includes, and difference quadrature modulates are produced by the first decoder
The input signal of device；The output signal of above-mentioned difference sigma modulator is received by the second decoder, to produce intermediate division ratio
Integer-bit and intermediate division ratio decimal place；Transmit above-mentioned intermediate division than integer-bit and above-mentioned intermediate division ratio decimal
Position is to frequency divider；And according to control signal, determine that above-mentioned frequency divider switches to integral frequency divisioil pattern or fractional frequency division pattern.
One embodiment of the invention provides a kind of method for reducing quantizing noise.The method of above-mentioned reduction quantizing noise is fitted
For frequency divider.The step of method of above-mentioned reduction quantizing noise, includes, from decoder receive intermediate division than integer-bit and
Intermediate division than decimal place；And according to control signal, determine that above-mentioned frequency divider switches to integral frequency divisioil pattern or decimal point
Frequency pattern.
On other additional features and advantage of the invention, those skilled in the art are not departing from the spirit and model of the present invention
In enclosing, when can do a little change according to the apparatus and method disclosed in the application implementation and obtained with retouching.
Brief description of the drawings
Fig. 1 is the block diagram for the phase-locked loop 100 for showing known technology.
Fig. 2 is the block diagram for showing the phase-locked loop 200 according to one embodiment of the invention.
Fig. 3 is to show phase-locked loop (Phase-locked loops, PLL) described according to another embodiment of the present invention
The block diagram of circuit 300
Fig. 4 is the block diagram for showing the frequency divider 280 according to one embodiment of the invention.
Fig. 5 is the circuit diagram for showing the divider clock generation circuit 282 according to one embodiment of the invention.
Fig. 6 is to show the signal waveforms according to one embodiment of the invention.
Fig. 7 is to show that the reduction according to one embodiment of the invention quantifies the flow chart 600 of Noise Method.
Fig. 8 is to show that the reduction according to one embodiment of the invention quantifies the flow chart 700 of Noise Method.
Embodiment
What this section was described is preferred embodiment of the present invention, it is therefore intended that illustrates the spirit of the present invention and is not used to
Protection scope of the present invention is limited, protection scope of the present invention is worked as to be defined depending on appended claims confining spectrum.
Fig. 2 is to show phase-locked loop (Phase-locked loops, the PLL) electricity according to one embodiment of the invention
The block diagram on road 200.As shown in Fig. 2 may include phase frequency detector (Phase Frequency in phase-locked loop 200
Detector, PFD) 210, it is charge pump (Charge Pump, CP) 220, loop filter (Loop Filter, LF) 230, voltage-controlled
Oscillator (Voltage Control Oscillator, VCO) 240, first decoder 250, difference sigma modulator (Delta-
Sigma Modulator, DSM) the 260, second decoder 270 and frequency divider (Frequency Divider) 280.Need note
Meaning, block diagram in fig. 2, only for convenient explanation embodiments of the invention, the present invention is not limited thereto.
The operation of the phase frequency detector 210 of phase-locked loop 200, charge pump 220 and loop filter 230 is similar traditional
The framework of phase-locked loop, is just repeated no more in the present invention.
According to one embodiment of the invention, the first decoder 250 receives a theoretical frequency dividing ratio DIV, below for convenience of statement,
It is integer-bit DIV_M and decimal place DIV_N by theoretical frequency dividing ratio DIV points.For example, if theoretical frequency dividing ratio is 5.4, its is whole
Numerical digit DIV_M is 5, and decimal place DIV_N is 4, and integer-bit DIV_M and decimal place DIV_N are poor through the processing generation of the first decoder 250
The input signal DSMIN of different sigma modulator 260, signal DSMIN produce signal after being handled through difference sigma modulator 260
DSMOUT, the effect of difference sigma modulator 260 is that signal DSMIN is sampled with higher speed, the number of exporting change
Word output valve, such as when difference sigma modulator 260 is 3 rank, 4 grades of difference sigma modulators, then output signal DSMOUT takes
Integer in [DSMIN-4, DSMIN+3] interval, and send integer output signal DSMOUT to second decoders 270,
In the other embodiment of the present invention, difference sigma modulator 260 can be arbitrary order arbitrary number of level.
First decoder 250 includes the mlultiplying circuit for being multiplied by 2, now when DIV_N is less than or equal to 4, DSMIN integer-bits most
Latter position perseverance is Binary Zero；When DIV_N last perseverance for being more than or equal to 5, DSMIN integer-bits is binary one.For example,
If theoretical frequency dividing ratio DIV is equal to 5.4, its decimal place DIV_N is equal to 4, and theoretical frequency dividing ratio DIV is binary
0101.011 ..., the mlultiplying circuit for being multiplied by 2 through the first decoder 250 is handled, and output signal DSMIN is equal to binary value
1010.11 ..., if theoretical frequency dividing ratio DIV is equal to 5.5, DIV_N and is equal to 5, theoretical frequency dividing ratio DIV is that binary zero 101.1 is passed through
First decoder 250 is multiplied by 2 mlultiplying circuit processing, and output signal DSMIN is equal to binary value 1011.If difference quadrature modulates
Device 260 takes 3 rank, 4 grades of difference sigma modulators, then output signal DSMOUT takes the integer in [DSMIN-4, DSMIN+3] interval,
And send integer output signal DSMOUT to second decoders 270.
Second decoder 270 include divided by 2 division circuit, there is correspondence to close for the division circuit and above-mentioned mlultiplying circuit
System, for example when mlultiplying circuit be one be multiplied by 2 mlultiplying circuit when, division circuit be one divided by 2 division circuit, the present invention
In other embodiment, the first decoder 250 and the second decoder 270 can also include other mlultiplying circuits that there is corresponding relation
And division circuit.
Integer output signal DSMOUT produced after the processing of the second decoder 270 intermediate division than integer-bit N and
Intermediate division than decimal place S, the second decoder 270 by intermediate division than integer-bit N and intermediate division than decimal place S
Send frequency divider 280 to.Intermediate division than integer-bit N be signal DSMOUT through the second decoder 270 division circuit processing
The integer part of gone out result；Intermediate division than decimal place S be at division circuits of the signal DSMOUT through the second decoder 270
Reason goes out the fractional part of result, for example, if signal DSMIN is equal to binary value 1010.11 ..., through 3 rank, 4 grades of differences
Sigma modulator 260 is handled, and output signal DSMOUT takes the integer in [DSMIN-4, DSMIN+3] interval, for example, work as signal
DSMOUT is equal to binary value 1010, and the division circuit processing through the second decoder 270, binary value 1010 moves to right 1, centre
The integer-bit N of frequency dividing ratio is binary value 0101, intermediate division than decimal place S be 1 binary value 0, when DSMOUT is equal to
Binary value 1011, the division circuit processing through the second decoder 270, binary value 1011 moves to right 1, then intermediate division than
Integer-bit N is binary value 0101, intermediate division than decimal place S be 1 binary value 1.
In other embodiments of the invention, the first decoder 250 and the second decoder 270 can also include other presence
The mlultiplying circuit and division circuit of corresponding relation, such as when the mlultiplying circuit and second that the first decoder 250 includes being multiplied by 4 is decoded
Device 270 include divided by 4 division circuit, then the multiplication and division of corresponding binary data need to move to left 2 and move to right 2,
Corresponding intermediate division than decimal place S be 2 binary values.Intermediate division than decimal place S digit translated depending on first
The division circuit that the mlultiplying circuit and the second decoder 270 that code device 250 is included are included.
In another embodiment of the invention, for convenience of operate, intermediate division than decimal place S can be subtracted with a certain value
Division circuit processing of the signal DSMOUT through the second decoder 270 goes out the fractional part of result, such as when middle frequency dividing ratio
Decimal place S be 1 bit, this it is a certain value be 2, then intermediate division than decimal place S be separately entered as 01, or 10, such as go out
Other existing such as 00 or 11 values, then be determined as run-time error.
Fig. 3 is to show phase-locked loop (Phase-locked loops, PLL) described according to another embodiment of the present invention
The block diagram of circuit 300, as shown in figure 3, may include phase frequency detector (Phase Frequency in phase-locked loop 300
Detector, PFD) 310, it is charge pump (Charge Pump, CP) 320, loop filter (Loop Filter, LF) 330, voltage-controlled
Oscillator (Voltage Control Oscillator, VCO) 340, difference sigma modulator (Delta-Sigma
Modulator, DSM) 350, decoder 360 and frequency divider (Frequency Divider) 370.
From unlike embodiment illustrated in fig. 2, the embodiment is by the first decoder 250 and the second decoder 270 in Fig. 2
Decoder 350 is integrated into, makes decoder 350 while having the function of the first decoder 250 and the second decoder 270 concurrently, letter is received
Number DIV_M and signal DIV_N, processing produces signal DSMIN and simultaneously exported to difference sigma modulator 360；Signal DSMOUT is received,
Processing produce intermediate division than integer-bit N and intermediate division ratio decimal place S and export to frequency divider 370.
Fig. 4 is the block diagram of the frequency divider 280 according to one embodiment of the invention.As shown in figure 4, frequency divider 280
Including integer frequency divider 281 and divider clock generation circuit 282.
Integer frequency divider 281 is integer frequency divider.According to one embodiment of the invention, integer frequency divider 281 receives second
The integer-bit N for the frequency dividing ratio that decoder 270 is exported, and the clock signal clk 1 that divider clock generation circuit 282 is exported, and
Enable signal EN is exported to divider clock generation circuit 282, and clock signal FBCLK is to phase-frequency detector 210.
According to one embodiment of the invention, divider clock generation circuit 282 receives signal SMODE, and according to signal
SMODE control frequency dividers 280 switch between integral frequency divisioil pattern or fractional frequency division pattern.When control signal SMODE be equal to 0,
The partial function of divider clock generation circuit 282 is closed down, frequency divider 280 switches to integral frequency divisioil pattern.As control signal SMODE
Equal to 1, start the repertoire of divider clock generation circuit 282, frequency divider 280 can then switch to fractional frequency division pattern.According to
One embodiment of the invention, control signal SMODE is provided by external circuit, and control signal SMODE is set on demand by user
It is fixed.
When frequency divider 280 switches to integral frequency divisioil pattern, divider clock generation circuit 282 is in part enable shape
State, the clock signal clk 1 that divider clock generation circuit 282 is exported is the voltage controlled oscillator 240 gathered by MUX
Output signal, i.e. clock signal CLK1 be equal to voltage controlled oscillator 240 export certain clock signal, and reach integral frequency divisioil all the way
Device 281.That is, when frequency divider 280 switches to integral frequency divisioil pattern, frequency divider 280 can be regarded as only integer frequency divider
281。
According to one embodiment of the invention, when frequency divider 280 switches to integral frequency divisioil pattern, integer frequency divider 281 is received
To the integer-bit N of frequency dividing ratio, the integer frequency divider 281 is counted since 0 to the rising edge of clock signal clk 1, works as counting
When value is equal to the integer-bit N of frequency dividing ratio, exports enable signal EN and produce a pulse, and give integer frequency divider 281 1 to reset and believe
Number, it is allowed to count again since 0.
When frequency divider 280 switches to fractional frequency division pattern, divider clock generation circuit 282 is in complete enable shape
State.That is, when frequency divider 280 switches to fractional frequency division pattern, integer frequency divider 281 combines divider clock and produces electricity
Road 282 can be considered decimal frequency divider.When frequency divider 280 switches to fractional frequency division pattern, integer frequency divider output enable letter
Number EN acts on divider clock generation circuit 282, and receives clock signal clk 1 from divider clock generation circuit 282, with
Carry out fractional frequency division operation.
Divider clock generation circuit 282 utilizes at least one clock signal VCOCLK produced by voltage controlled oscillator 240,
Make the intermediate division of frequency divider 280 than being contained in using the integer-bit N of frequency dividing ratio as starting point, 1/2n-1(n is natural number) is step
Grow, using N+1 as the set of terminal, divider clock generation circuit 282 needs to utilize 2n-1Individual clock signal, and 2n-1Individual clock letter
Number it is equiphase interval, the phase intervals are 2 pi/2sn-1.In one embodiment, compatible integer and half-integral division to be realized
Decimal frequency divider, i.e., will make the frequency dividing ratio of frequency divider 280 be contained in set { N, N+1/2, N+1 }, clock generation circuit 282 needs
Utilize the first clock signal VCOCLK1 and second clock signal VCOCLK2 produced by voltage controlled oscillator 240, the first clock letter
Number VCOCLK1 and second clock signal VCOCLK2 is anti-phase.In another embodiment, it is contained in the frequency dividing ratio of frequency divider 280
The set of { N, N+1/4, N+1/2, N+3/4, N+1 }, the i.e. frequency dividing ratio of frequency divider 280 are { N, N+1/4, N+1/2, N+3/4, N+
During arbitrary value in 1 } gathering, n is equal to 3, and the divider clock generation circuit 282 is needed using being produced by voltage controlled oscillator 240
Phase intervals be pi/2 4 clocks.
According to one embodiment of the invention, divider clock generation circuit 282 is from containing divided by 2 circuit second is translated
Code device 270 obtain intermediate division than decimal place S, for convenience of operate, another assignment S be 2 subtract former intermediate division than decimal place
S, so such as when frequency divider 280 switches to fractional frequency division pattern, when the decimal place of frequency dividing ratio is one first signal, S is equal to
01, divider clock generation circuit 282 carries out the switching of the first predetermined number of times to the phase of clock signal clk 1, for example once；
When the decimal place of frequency dividing ratio is secondary signal, such as S is equal to 10, and divider clock generation circuit 282 is to clock signal clk 1
Phase carry out the second predetermined number of times switching, for example twice；When signal S is the 3rd signal, such as S is equal to 00 or 11, represents
A mistake is sunk into phase-locked loop operation, and now divider clock generation circuit 282 keeps laststate, until S is returned normally
01 or 10, otherwise do not perform switching.
Fig. 5 is the circuit diagram of the divider clock generation circuit 282 described in one embodiment of the invention, passes through the first decoding
The divider clock generation circuit 282 of device 250, the second decoder 270 and Fig. 5, can cut according to control signal SMODE value
Change to fractional frequency division pattern, realize that the decimal frequency divider of compatible integer and half-integral division, the i.e. frequency dividing ratio of frequency divider 280 can be with
For the arbitrary value in set { N, N+1/2, N+1 }, it is possible to be switched to integral frequency divisioil pattern according to control signal SMODE value.
As shown in figure 5, when control signal SMODE is equal to 0, frequency divider 280 switches to integral frequency divisioil pattern.Including the 2nd D
D-flip flop 530, the D flip-flop 550 of XOR gate (XOR) the 540, the 3rd and the second MUX 560.2nd D types are triggered
The output SW perseverances of device 530 are high level, and the signal sel of the 3rd D flip-flop 550 output is set, i.e. signal sel perseverances are high electricity
Flat or low level, the clock signal clk 1 that divider clock generation circuit 282 is exported is the pressure gathered by MUX 560
Certain of controlled oscillator 240 output signal all the way, in this embodiment, i.e. clock signal CLK1 perseverances export for voltage controlled oscillator 240
The second clock signal VCOCLK2 that are exported for voltage controlled oscillator 240 of the first clock signal VCOCLK1 or permanent, and reach integer
Frequency divider 281, thus, when frequency divider 280 switches to integral frequency divisioil pattern, frequency divider 280 can be regarded as only integral frequency divisioil
Device 281.
As shown in figure 5, when control signal SMODE is equal to 1, frequency divider 280 switches to fractional frequency division pattern.Divider clock
Generation circuit 282 is in complete enabled status, including the first D flip-flop 510, the first MUX 520, the 2nd D types are touched
Send out device 530, the D flip-flop 550 of XOR gate (XOR) the 540, the 3rd and the second MUX 560.First MUX
520 are respectively coupled to the first D flip-flop 510 and the second D flip-flop 530.When S is equal to 01, the first MUX 520
EN signals are exported to the second D flip-flop 530.When S is equal to 10, the first MUX 520 exports the first D flip-flop 510
Output signal to the second D flip-flop 530.When S is equal to 00 or 11, the first MUX 520 exports a low level to the
Two D flip-flops 530.Second D flip-flop 530 receives control signal SMODE, and output signal SW to XOR gate 540.It is different
OR gate 540 receives signal SW from the second D flip-flop 530, and receives signal sel from the 3rd D flip-flop 550.3rd D types
Trigger 550 receives the signal add that XOR gate 540 is exported, and output signal sel.When second MUX 560 receives first
Clock signal VCOCLK1 and second clock signal VCOCLK2, and the signal sel exported according to the 3rd D flip-flop 550, choosing
The first clock signal VCOCLK1 or second clock signal VCOCLK2 are selected as clock signal clk 1.Clock signal clk 1 is produced
Afterwards, the second MUX 560 sends clock signal clk 1 to integer frequency divider 281.
Fig. 6 is the timing diagram according to one embodiment of the invention.Timing diagram shown in Fig. 6 is based on shown in Fig. 5 points
The complete enabled status of frequency device clock generation circuit 282, i.e. frequency divider 280 switch to the situation of fractional frequency division pattern, the sequential
Figure is merely to illustrate Fig. 5 embodiment, and the present invention is not limited thereto.
As shown in fig. 6, oscillogram is from a to b, from c to d, from e to f, from g to h, from i to j, from k to l and from m to n
When part represents that the triggering D flip-flop of clock signal clk 1 is sampled to incoming level, reach D types from clock signal clk 1 and touch
Device is sent out, during to the D flip-flop output signal, the time delay t produced inside D flip-flop, so each D flip-flop
The rising edge in its clock signal clk 1 of triggering of output, there is time t delay, and delay t is because D flip-flop
Difference between individual, not fully unanimously, but delay t must be more than 0, and less than inverting clock signal VCOCLK1 or VCOCLK2
1/2 cycle.
Part correspondence S of the oscillogram from e to g is equal to 01 oscillogram, counts every time after terminating, enable signal EN produces high
Level, the high level lasting time is 1 cycle of clock signal clk 1, in the second D flip-flop 430,1 pair of clock signal clk
Signal EN is sampled, and output signal SW is the high level in 1 cycle of clock signal clk 1, and signal sel is overturn once, control clock letter
Number CLK1 is switched to signal VCOCLK2 from signal VCOCLK1, is accounted for from the rising edge e of clock signal clk 1 to its next rising edge
With 1/2 cycle that the time is inverting clock signal VCOCLK1 or VCOCLK2, so when S is equal to 01, divider clock produces electricity
Road 282 is equal to 01 using the decimal place S of frequency dividing ratio, realizes the meter to input clock signal VCOCLK1 or VCOCLK2 1/2
Number, makes divider clock generation circuit 282 together with integer frequency divider 281, and it is N that can realize actual frequency dividing ratio DIV_actual
+ 1/2 frequency dividing.
Part correspondence S of the oscillogram from k to o is equal to 10 oscillogram, counts every time after terminating, enable signal EN is high electricity
Usually, the first MUX 420 output high level, after the rising edge k of clock signal clk 1 arrives, the first MUX
420 output switching activities are low level, to after clock signal CLK1 rising edge m arrivings, in the second D flip-flop 430, the low level
Signal SW can be just passed to, before this, signal SW is the high level in lasting two cycles of clock signal clk 1, signal sel
Upset twice, so signal sel control clock signal clk 1 switch between signal VCOCLK2 and signal VCOCLK1 twice, from when
Clock signal CLK1 rising edge k to its next rising edge holding time be clock signal VCOCLK1 or VCOCLK2 1/2 cycle,
It is inverting clock signal VCOCLK1 or VCOCLK2 from the rising edge m of clock signal clk 1 to its next rising edge holding time
1/2 cycle, so when S is equal to 10, the decimal place S that divider clock generation circuit 282 receives frequency dividing ratio is equal to 10, realizes to defeated
Enter clock signal VCOCLK1 or VCOCLK2 (1/2+1/2) position, i.e., the counting of 1, make divider clock generation circuit 282 with it is whole
Modulus frequency divider 281 together, can realize the frequency dividing that actual frequency dividing ratio DIV_actual is N+1, and adjust because being integrated in difference
In the presence of device processed, the integer-bit N of frequency dividing ratio is the integer constantly fluctuated, N and N+1 and indistinction, also corresponds to frequency divider real
The frequency dividing of N is showed.
In summary, when frequency divider 280 switches to integral frequency divisioil pattern, combination difference sigma modulator, frequency divider 280 is defeated
The clock signal FBCLK gone out is several N integral frequency divisioil comprehensive and long-term actions, the fractional frequency division effect of realization.When frequency divider 280
Switch to fractional frequency division pattern, combination difference sigma modulator, the clock signal FBCLK that frequency divider 280 is exported is that several N are whole
Number frequency dividing and several half-integral division comprehensive and long-term actions, the fractional frequency division effect of realization.
The phase-locked loop 200 proposed according to embodiments of the present invention, when the decimal frequency divider using the present invention, except can
To reduce the introduced quantizing noise of difference sigma modulator to original 1/2 or lower, also as effectively utilizing frequency dividing ratio
The reason of decimal place, improves frequency dividing progress, clock signal FBCLK is more leveled off to the input clock signal FIN of phase-locked loop.
In addition, the phase-locked loop 200 that is proposed of the embodiment of the present invention can compatible integer frequency divider and decimal frequency divider simultaneously, thus
It is more flexible in the operation of phase-locked loop.
Fig. 7 is to show that the reduction according to one embodiment of the invention quantifies the flow chart 700 of Noise Method.Flow chart
Reduction shown in 700 quantifies Noise Method and is applicable phase-locked loop 200.In step S710, phase-locked loop 200 is by the first decoder
Produce the input signal of difference sigma modulator.In step S720, phase-locked loop 200 receives difference by one second decoder and accumulated
Divide the output signal of modulator, to produce the integer-bit of frequency dividing ratio and the decimal place of frequency dividing ratio.In step S730, phase-locked loop
The integer-bit of 200 transmission frequency dividing ratios and the decimal place of frequency dividing ratio are to frequency divider.In step S740, phase-locked loop 200 is according to control
Signal, determines that frequency divider switches to integral frequency divisioil pattern or fractional frequency division pattern.
Profit is implemented according to the present invention one, in the method shown in flow chart 700, the first decoder carries out multiplication operation, with
And second decoder carry out divide operations.
The step of implementing profit, flow chart 700 according to the present invention one also includes, when switching to above-mentioned integral frequency divisioil pattern,
Divider clock generation circuit in part enable frequency divider, and when switching to above-mentioned fractional frequency division pattern, complete enable
Above-mentioned divider clock generation circuit in above-mentioned frequency divider.
According to one embodiment of the invention, also include when the decimal place of frequency dividing ratio is the first signal the step of flow chart 700,
Output clock signal is switched to second clock signal from the first clock signal, the switching of the first predetermined number of times is performed, and
When the decimal place of frequency dividing ratio is secondary signal, output clock signal is switched to second clock signal from the first clock signal,
First clock signal is switched to from the second clock signal again, the switching of the second predetermined number of times is performed.
Fig. 8 is to show that the reduction according to one embodiment of the invention quantifies the flow chart 800 of Noise Method.Flow chart
Reduction shown in 800 quantifies Noise Method and is applicable frequency divider 280.In step S810, frequency divider 280 receives frequency dividing ratio from decoder
Integer-bit and frequency dividing ratio decimal place.In step S820, frequency divider 280 switches to integral frequency divisioil according to control signal, decision
Pattern or fractional frequency division pattern.
" embodiment " that is previously mentioned in this specification or " embodiment ", represent the specific spy relevant with embodiment
Levy, structure or characteristic are comprising at least embodiment according to the present invention, it is not intended that they are present in each implementation
In example.Therefore, " in one embodiment " or " in embodiment " phrase that different places occur in this manual is not necessarily
Represent the phase be the same as Example of the present invention.
Above paragraph is described using a variety of aspects.Obvious, this paper teaching may be implemented in a variety of ways, and in example
Disclosed any certain architectures or function are only a representational situation.According to this paper teaching, those skilled in the art should manage
Solution each aspect disclosed herein can independent implementation or two or more aspects can merge implementation.
Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore the protection model of the present invention
Enclose to work as and be defined depending on appended claims confining spectrum.
Claims (14)
1. a kind of phase-locked loop, including：
Difference sigma modulator, receives input signal；
Decoder, couples above-mentioned difference sigma modulator, produces the integer-bit of frequency dividing ratio and the decimal place of the frequency dividing ratio；And
Frequency divider, couples above-mentioned decoder, receives the integer-bit of above-mentioned frequency dividing ratio and the decimal place of above-mentioned frequency dividing ratio, and according to control
Signal processed switches to integral frequency divisioil pattern or fractional frequency division pattern.
2. phase-locked loop as claimed in claim 1, wherein above-mentioned decoder includes：
First decoder, including mlultiplying circuit, couple above-mentioned difference sigma modulator, produce being somebody's turn to do for above-mentioned difference sigma modulator
Input signal；And
On second decoder, including division circuit corresponding with above-mentioned mlultiplying circuit, the above-mentioned difference sigma modulator of coupling, reception
The output signal of difference sigma modulator is stated, and produces the integer-bit of above-mentioned frequency dividing ratio and the decimal place of above-mentioned frequency dividing ratio.
3. phase-locked loop as claimed in claim 1, wherein above-mentioned frequency divider includes：
Integer frequency divider, receives the integer-bit of above-mentioned frequency dividing ratio；And
Divider clock generation circuit, receives the decimal place and above-mentioned control signal of above-mentioned frequency dividing ratio.
4. phase-locked loop as claimed in claim 3, wherein when the frequency divider switches to above-mentioned integral frequency divisioil pattern, above-mentioned point
Frequency device clock generation circuit is part enabled status；And
When the frequency divider switches to above-mentioned fractional frequency division pattern, above-mentioned divider clock generation circuit is complete enabled status.
5. phase-locked loop as claimed in claim 4, in have 2n-1Individual phase intervals are 2 pi/2sn-1Above-mentioned point of clock signal input
Frequency device clock generation circuit, n is natural number；
When the decimal place of above-mentioned frequency dividing ratio is the first signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal；And
When the decimal place of above-mentioned frequency dividing ratio is secondary signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal, then from the second clock
Signal is switched to first clock signal.
6. a kind of frequency divider, including：
Integer frequency divider, receives the integer-bit of frequency dividing ratio；And
Divider clock generation circuit, is coupled to above-mentioned integer frequency divider, and receive the decimal place and control signal of frequency dividing ratio.
7. frequency divider as claimed in claim 6, wherein above-mentioned divider clock generation circuit, switches according to above-mentioned control signal
The frequency divider to integral frequency divisioil pattern or fractional frequency division pattern,
When the frequency divider switches to above-mentioned integral frequency divisioil pattern, above-mentioned divider clock generation circuit is part enabled status；
And
When the frequency divider switches to above-mentioned fractional frequency division pattern, above-mentioned divider clock generation circuit is complete enabled status.
8. frequency divider as claimed in claim 7, wherein having 2n-1Individual phase intervals are 2 pi/2sn-1Above-mentioned point of clock signal input
Frequency device clock generation circuit, n is natural number；
When the decimal place of above-mentioned frequency dividing ratio is the first signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal；And
When the decimal place of above-mentioned frequency dividing ratio is secondary signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal, then from the second clock
Signal is switched to first clock signal.
9. a kind of phase-lock technique, is applicable phase-locked loop, including：
Multiplication operation is carried out by the first decoder, the input signal of difference sigma modulator is produced；
The output signal of above-mentioned difference sigma modulator is received by the second decoder, division behaviour corresponding with multiplication operation is carried out
Make, produce the integer-bit of frequency dividing ratio and the decimal place of frequency dividing ratio；
The integer-bit of above-mentioned frequency dividing ratio and the decimal place of above-mentioned frequency dividing ratio are transmitted to frequency divider；And
According to control signal, determine that above-mentioned frequency divider switches to integral frequency divisioil pattern or fractional frequency division pattern.
10. phase-lock technique as claimed in claim 9, in addition to：
When the frequency divider switches to above-mentioned integral frequency divisioil pattern, the divider clock of the above-mentioned frequency divider of part enable produces electricity
Road；And
When the frequency divider switches to above-mentioned fractional frequency division pattern, the above-mentioned divider clock of the complete above-mentioned frequency divider of enable is produced
Circuit.
11. phase-lock technique as claimed in claim 10, in addition to：
Have 2n-1Individual phase intervals are 2 pi/2sn-1The above-mentioned divider clock generation circuit of clock signal input, n is natural number；
When the decimal place of above-mentioned frequency dividing ratio is the first signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal；And
When the decimal place of above-mentioned frequency dividing ratio is secondary signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal, then from the second clock
Signal is switched to first clock signal.
12. a kind of phase-lock technique, is applicable frequency divider, including：
The integer-bit of frequency dividing ratio and the decimal place of frequency dividing ratio are received from decoder；And
According to control signal, determine that above-mentioned frequency divider switches to integral frequency divisioil pattern or fractional frequency division pattern.
13. phase-lock technique as claimed in claim 12, in addition to：
When the frequency divider switches to above-mentioned integral frequency divisioil pattern, the divider clock of the above-mentioned frequency divider of part enable produces electricity
Road；And
When the frequency divider switches to above-mentioned fractional frequency division pattern, the above-mentioned divider clock of the complete above-mentioned frequency divider of enable is produced
Circuit.
14. phase-lock technique as claimed in claim 13, in addition to：
Have 2n-1Individual phase intervals are 2 pi/2sn-1The above-mentioned divider clock generation circuit of clock signal input, n is natural number；
When the decimal place of above-mentioned frequency dividing ratio is the first signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal；And
When the decimal place of above-mentioned frequency dividing ratio is secondary signal, the output clock signal of above-mentioned divider clock generation circuit is from 2n-1
Individual phase intervals are 2 pi/2sn-1Clock signal in the first clock signal be switched to second clock signal, then from the second clock
Signal is switched to first clock signal.
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| CN108039885A (en) * | 2018-02-11 | 2018-05-15 | 成都信息工程大学 | A kind of high speed dividing method and there is the high-speed frequency divider of duty cycle adjustment |
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