CN104300975A - Decimal and integer frequency divider circuit and implementation method thereof - Google Patents
Decimal and integer frequency divider circuit and implementation method thereof Download PDFInfo
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- CN104300975A CN104300975A CN201410494264.7A CN201410494264A CN104300975A CN 104300975 A CN104300975 A CN 104300975A CN 201410494264 A CN201410494264 A CN 201410494264A CN 104300975 A CN104300975 A CN 104300975A
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Abstract
The invention discloses a decimal and integer frequency divider circuit and an implementation method of the decimal and integer frequency divider circuit. The decimal and integer frequency divider circuit comprises an orthogonal clock generation module, a pulse swallowing circuit, a divide-by-2 divider, a mode control module and a clock selection module. The method includes the steps that firstly, an initial clock generates two pairs of difference clock signals which are orthogonal through the orthogonal clock generation module; secondly, a MODE signal generates a pulse swallowing control signal through the mode control module, and the number of pulse swallowing times is determined; thirdly, the clock selection module selects an output clock. According to the decimal and integer frequency divider circuit, the frequency division of different integer and decimal frequency division factors can be achieved by programming the MODE control signal and the clock selection signal, and the decimal and integer frequency divider circuit has the advantages of being high in frequency resolution, wide in frequency division factor range and high in module repeated utilization rate. The frequency divider is suitable for the field of programmable decimal frequency division phase-locked loop design, frequency synthesizer design and other clock system design.
Description
Technical field
The present invention relates generally to Clock System Design field, can be applicable to fractional frequency-division phase-locked loop, frequency synthesizer in radio frequency transceiver, particularly relates to a kind of decimal _ integer frequency divider circuit and its implementation, the design of broken number frequency division synthesizer is realized more simple and efficient.
Background technology
As the key modules in field of radio frequency communication, frequency synthesizer is mainly the carrier signal that transmitting system provides high frequency, realizes frequency modulation function simultaneously, realizes the frequency modulation(FM) of low-frequency digital signal to high-frequency signal; For receiving system, frequency synthesizer is mainly its accurate local oscillation signal providing frequency interval consistent with transmitting system.
For legacy frequencies synthesizer, output clock frequency meets Fre_out=N*Fre_ref, and wherein Fre_out is frequency synthesizer output clock frequency, and Fre_ref is the frequency of input reference clock, and N is the Frequency Dividing Factor of feedback divider.In order to obtain wide frequency range, precision is high and phase noise performance is good clock signal, frequency synthesizer generally adopts and reduces input reference clock frequency Fre_ref technology to improve the frequency resolution of output clock; Adopt and increase the frequency range that Frequency Dividing Factor N realizes output clock.But, adopt comparatively small frequency reference clock, mean that the loop bandwidth of frequency synthesizer needs to reduce thereupon, cause the loop-locking time can be thereupon elongated; Meanwhile, narrower loop bandwidth can make loop inadequate to the phase noise reduction ability of voltage controlled oscillator VCO, reduces the phase noise performance of frequency synthesizer; According to large Frequency Dividing Factor N, the phase noise that phase noise contribution can be made to be proportional to other submodules (as phase frequency detector, charge pump etc.) of Frequency Dividing Factor N increases, and can worsen the noiseproof feature of frequency synthesizer equally.
In order to solve the problems of the technologies described above, the present invention proposes a kind of decimal _ integer frequency divider circuit and its implementation.This frequency divider can when reference clock frequency be constant, realize the functional requirement of frequency synthesizer output clock frequency division of the frequency rate height and wide frequency range, ensure that the phase noise of clock signal meets design requirement simultaneously, solve that clock frequency point frequency is high, locking time long and poor phase noise contradiction.The high frequency clock signal that VCO produces by decimal _ integer frequency divider carries out decimal N.F frequency division, the object that when finally reaching locking, feedback clock frequency is identical with reference clock frequency, produce the clock signal of other frequency needs according to clock system demand, wherein N is integer, and F is decimal simultaneously.
Described decimal _ integer frequency divider, programmes to integer and the fractional frequency division factor, can realize different Frequency Dividing Factors, and final acquisition meets the target clock signal of the different frequency scope of target frequency resolution.
Summary of the invention
The problem to be solved in the present invention is: for prior art Problems existing, the invention provides a kind of decimal _ integer frequency divider circuit and its implementation, this frequency divider can realize the fractional frequency division N.F of different integral frequency divisioil factor N and the integral frequency divisioil of the different integral frequency divisioil factor, improve the design flexibility of decimal _ integer frequency divider, reduce the design redundancy of integer frequency divider in frequency division branch road after frequency synthesizer, expand the reference frequency output of same frequency synthesizer under same frequency resolution condition.
For realizing above-mentioned technical problem, the solution that the present invention proposes is: a kind of decimal _ integer frequency divider circuit and its implementation, is characterized in that: comprise orthogonal clock generation module, gulp down impulse circuit, two-divider, mode control module and clock selection module;
In above-mentioned frequency divider, described orthogonal clock generation module, it is characterized in that: high frequency clock signal CLK_IN is by orthogonal clock generation module, create two pairs of orthogonal each other differential signals, wherein first pair of differential signal is CLK1 and CLK1_BAR, second pair of differential signal is the phase shift of CLK1_90 and CLK1_90_BAR, CLK1 and CLK1_90 difference 90 degree;
In above-mentioned frequency divider, described mode control module, it is characterized in that: what mode control signal MODE produced four parallel-by-bits by mode control module gulps down impulse circuit control signal SEL<0:3>, whether the four road parallel clock signals generated for controlling orthogonal clock generation module export, wherein the high level pulsewidth of MODE signal is the octuple in input clock signal CLK_IN cycle, and low-level pulse width is the integral multiple of high level pulsewidth;
In above-mentioned frequency divider, described gulps down impulse circuit, it is characterized in that: when MODE signal is only containing a high pulse signal, gulps down impulse circuit and realize five frequency divisions; When MODE signal contains N number of high pulse signal, gulp down impulse circuit and realize N five frequency divisions;
In above-mentioned frequency divider, described two-divider one and two-divider two, is characterized in that: carry out two divided-frequency to input clock signal;
In above-mentioned frequency divider, described clock selection module, it is characterized in that: the multipath clock signal that decimal _ integer frequency divider produces is carried out selection and exports, obtain the clock signal corresponding with target frequency, wherein input signal is respectively CLK_1 (4 frequency division) clock that orthogonal clock generation module generates, gulp down CLK_2 (4/5 frequency division) clock that impulse circuit produces, CLK_4 (16/17 frequency division) clock that CLK_3 (8/9 frequency division) clock of first two-divider generation and second two-divider produce.
Compared with prior art, the invention has the advantages that:
1, the integer factor in programmable fractional frequency division factor N.F is realized.Compared with traditional point frequency structure, present invention employs the programmable Fractional Frequency-Dividing Technology of the integral frequency divisioil factor, under realizing the condition of same frequency resolution, improve the operating frequency range of frequency divider.
2, the Programmable Design of the integral frequency divisioil Summing Factor fractional frequency division factor is realized.Compared with traditional fraction frequency device, the present invention can produce the different clock signal of channelized frequencies precision according to master slave system demand actual time.
3, design flexibility is strong.Compared with traditional fraction frequency device, structure of the present invention is simple, can realize recycling, reduce design redundancy in same frequency synthesizer circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of decimal of the present invention _ integral frequency divisioil circuit;
Fig. 2 is the output waveform schematic diagram of orthogonal clock generation module of the present invention;
Fig. 3 is the output waveform schematic diagram of mode control module of the present invention;
Fig. 4 is the output waveform schematic diagram that the present invention gulps down impulse circuit;
Fig. 5 is the clock frequency information schematic diagram of decimal _ integer frequency divider of the present invention.
Embodiment
Below with reference to the drawings and specific embodiments, the present invention is described in further details.
Shown in Figure 1, a kind of decimal _ integral frequency divisioil main circuit of the present invention will comprise orthogonal clock generation module, gulp down impulse circuit, two-divider, mode control module and clock selection module.
Shown in composition graphs 1, first high frequency clock CLK_IN is passed through orthogonal clock generation module by described decimal _ integral frequency divisioil circuit, produce two pairs of orthogonal each other differential signals, wherein first pair of differential signal is CLK1 and CLK1_BAR, second pair of differential signal is CLK1_90 and CLK1_90_BAR, the phase shift of CLK1 and CLK1_90 difference 90 degree, its output waveform schematic diagram is as shown in Figure 2;
Simultaneously, what mode control signal MODE produced four parallel-by-bits by mode control module gulps down impulse circuit control signal SEL<0:3>, realize carrying out selection to four road parallel clock signals of orthogonal clock generating CMOS macro cell to export, wherein the high level pulsewidth of MODE signal is the octuple in input clock signal CLK_IN cycle, low-level pulse width is the integral multiple of high level pulsewidth, and Fig. 3 describes the corresponding relation of mode control module input-output wave shape;
The four road parallel clock signals that orthogonal clock generation module generates and the SEL signal that mode control module produces are as the input signal gulping down impulse circuit, and wherein SEL<0:3> carries out selection output to four road parallel clock signals; When adjacent two control signal generation saltus steps, the clock signal of current output can be turned off, and another clock signal of delayed 90 degree, this clock of selected phase exports simultaneously, thus realizes the effect gulping down pulse.When SEL<0:3> only have one adjacent along saltus step time, then gulp down impulse circuit and once can gulp down pulse operation, when SEL<0:3> occur N time adjacent along saltus step time, then gulp down impulse circuit can carry out gulping down pulse operation N time, wherein N is determined by the target fractional frequency division factor, and Fig. 4 describes twice adjacent output waveform gulping down impulse circuit along saltus step;
Gulp down after impulse circuit realizes 4 and 4+1 frequency division of different number of times, if carried out S 5 frequency divisions, P 4 frequency divisions, then the fractional frequency division factor shown is 4.F=(S*5+P*4)/(P+S); Its clock signal is by continuous print twice two divided-frequency, wherein first two-divider module achieves 8 and 8+1 frequency division, if carried out S 9 frequency divisions, P 8 frequency divisions, then the fractional frequency division factor shown is 8.F=(S*9+P*8)/(P+S); Its output clock is again by second two-divider, finally reach 16 and 16+1 frequency division to the different number of times of initial clock CLK_IN, if carried out S 17 frequency divisions, P 16 frequency divisions, the fractional frequency division factor then shown is 16.F=(S*17+P*16)/(P+S), wherein F is decimal, and Fig. 5 describes all clock frequency information of decimal _ integer frequency divider.
The different clocks signal of above-mentioned generation, will as clock selection module input signal, and clock selection signal, according to actual clock frequency requirement, carries out output clock selection, and final acquisition meets the clock of target frequency information.
Circuit shown in above embodiment is to describe patent of the present invention in detail; but the present invention is not limited to above-described embodiment; device is replaced simply caused circuit variation and also belong to protection scope of the present invention, protection scope of the present invention should be as the criterion with claims.
Claims (6)
1. decimal _ integer frequency divider circuit and an its implementation, is characterized in that: comprise orthogonal clock generation module, gulp down impulse circuit, two-divider, mode control module and clock selection module.
2. frequency divider as claimed in claim 1, it is characterized in that: high frequency clock signal CLK_IN is by orthogonal clock generation module, create two pairs of orthogonal each other differential signals, wherein first pair of differential signal is CLK1 and CLK1_BAR, second pair of differential signal is the phase shift of CLK1_90 and CLK1_90_BAR, CLK1 and CLK1_90 difference 90 degree.
3. frequency divider as claimed in claim 1, it is characterized in that: what mode control signal MODE produced four parallel-by-bits by mode control module gulps down impulse circuit control signal SEL<0:3>, realize carrying out selection to four road parallel clock signals of orthogonal clock generating CMOS macro cell to export, wherein the high level pulsewidth of MODE signal is the octuple in input clock signal CLK_IN cycle, and low-level pulse width is the integral multiple of high level pulsewidth.
4. frequency divider as claimed in claim 1, is characterized in that: when MODE signal is only containing a high pulse signal, gulps down impulse circuit and realize five frequency divisions; When MODE signal contains N number of high pulse signal, gulp down impulse circuit and realize N five frequency divisions.
5. frequency divider as claimed in claim 1, is characterized in that: described two-divider mainly carries out two divided-frequency to input clock signal.
6. frequency divider as claimed in claim 1, it is characterized in that: the multipath clock signal that decimal _ integer frequency divider produces is carried out selection and exports by described clock selection module, obtain the clock signal corresponding with target frequency, wherein input signal is respectively CLK_1 (4 frequency division) clock that orthogonal clock generation module generates, gulp down CLK_2 (4/5 frequency division) clock that impulse circuit produces, CLK_4 (16/17 frequency division) clock that CLK_3 (8/9 frequency division) clock of first two-divider generation and second two-divider produce.
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| CN105652660A (en) * | 2016-01-07 | 2016-06-08 | 北京北广科技股份有限公司 | Single-chip microcomputer-based method for acquiring crossover frequency control word |
| CN106059708A (en) * | 2016-05-06 | 2016-10-26 | 东南大学 | Multi-code rate data wireless transmission system |
| CN107250833A (en) * | 2015-03-04 | 2017-10-13 | 黑拉许克联合股份有限公司 | Radar installations |
| CN107294531A (en) * | 2017-06-21 | 2017-10-24 | 上海兆芯集成电路有限公司 | Phase-locked loop and frequency divider |
| CN108023578A (en) * | 2016-10-31 | 2018-05-11 | 联发科技股份有限公司 | Orthogonal clock generating means and communication system transmitter |
| CN108736882A (en) * | 2017-04-21 | 2018-11-02 | 展讯通信（上海）有限公司 | Fractional frequency divider circuit and rf terminal |
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| CN107294531B (en) * | 2017-06-21 | 2020-09-11 | 上海兆芯集成电路有限公司 | Phase locked loop and frequency divider |
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