CN116667847A - Beidou radio frequency synthesizer, method, device, phase-locked loop and storage medium - Google Patents

Beidou radio frequency synthesizer, method, device, phase-locked loop and storage medium Download PDF

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Publication number
CN116667847A
CN116667847A CN202310667690.5A CN202310667690A CN116667847A CN 116667847 A CN116667847 A CN 116667847A CN 202310667690 A CN202310667690 A CN 202310667690A CN 116667847 A CN116667847 A CN 116667847A
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China
Prior art keywords
frequency
phase
locked loop
reference frequency
divider
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CN202310667690.5A
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Chinese (zh)
Inventor
何方勇
谷平
高峰
许祥滨
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Techtotop Microelectronics Co Ltd
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Techtotop Microelectronics Co Ltd
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Priority to CN202310667690.5A priority Critical patent/CN116667847A/en
Publication of CN116667847A publication Critical patent/CN116667847A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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Abstract

The application discloses a Beidou radio frequency synthesizer, a method, a device, a phase-locked loop and a storage medium. The Beidou radio frequency synthesizer comprises a crystal oscillator, a reference frequency divider, a phase-locked loop and two different frequency dividers, wherein the phase-locked loop comprises a receiving path phase-locked loop and a transmitting path phase-locked loop; a crystal oscillator for generating a reference frequency required for the phase-locked loop; the reference frequency divider is used for dividing the reference frequency to obtain the reference frequency required by the phase-locked loop; the transmitting path phase-locked loop is used for generating a transmitting local oscillator frequency required by Beidou signal transmitting modulation according to the reference frequency; and the receiving path phase-locked loop is used for generating radio frequency related to the receiving path according to the reference frequency, and dividing the radio frequency by two different frequency dividers to respectively obtain the local oscillation frequency and the baseband reference frequency of the receiver. The application can reduce the power consumption and the cost by adopting the double phase-locked loop design.

Description

Beidou radio frequency synthesizer, method, device, phase-locked loop and storage medium
Technical Field
The embodiment of the application relates to the technical field of electronic communication, in particular to a Beidou radio frequency synthesizer, a method, a device, a phase-locked loop and a storage medium.
Background
At present, beidou short message application is mainly focused on occasions such as industry application, and application products are mainly oriented to a complete machine solution, so that low-power consumption design requirements of the products are not urgent. However, along with the rapid development of the internet of things, requirements for low power consumption of Beidou short messages are gradually provided in some application scenes with poor power supply capacity.
Fig. 1 is a schematic structural diagram of a beidou short message frequency synthesizer provided in the prior art, as shown in fig. 1, where the beidou short message frequency synthesizer includes a crystal Oscillator (Temperature Compensate X' tal) Oscillator (TCXO), a transmit path phase-locked loop, a receive path phase-locked loop, and a baseband processing phase-locked loop. All phase-locked loops are based on the time frequency reference of a crystal oscillator, the technical schemes adopted by each phase-locked loop are different, f1 is used for generating a transmitting carrier frequency, f2 is used for generating a receiving local oscillator, and f3 is used for generating a reference frequency of a baseband Analog-to-Digital Converter (ADC) and a subsequent baseband decoding.
The Beidou short message frequency synthesizer in the prior art has larger power consumption, higher required cost and can not meet the requirement of low-power consumption design.
Disclosure of Invention
The application provides a Beidou radio frequency synthesizer, a method, a device, a phase-locked loop and a storage medium, which are used for solving the problems of high consumption and high cost of the frequency synthesizer in the prior art.
According to an aspect of the present application, there is provided a Beidou radio frequency synthesizer including a crystal oscillator, a reference frequency divider, a phase-locked loop and two different frequency dividers, the phase-locked loop including a receive path phase-locked loop and a transmit path phase-locked loop;
the crystal oscillator is connected with the reference frequency divider, and the reference frequency divider is also connected with the one transmitting path phase-locked loop and the one receiving path phase-locked loop respectively;
the crystal oscillator is used for generating a reference frequency required by the phase-locked loop;
the reference frequency divider is used for dividing the reference frequency to obtain the reference frequency required by the phase-locked loop;
the transmitting path phase-locked loop is used for generating a transmitting local oscillation frequency required by Beidou signal transmitting modulation according to the reference frequency;
the receiving path phase-locked loop is used for generating radio frequency related to a receiving path according to the reference frequency, and dividing the radio frequency by two different frequency dividers to respectively obtain the local oscillation frequency and the baseband reference frequency of the receiver.
According to another aspect of the present application, there is provided a frequency allocation method performed by a receive path phase locked loop, the method comprising:
acquiring a reference frequency required by a phase-locked loop, wherein the reference frequency is generated by a reference frequency divider;
generating a radio frequency related to a receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through two different frequency dividers to respectively obtain a receiving local oscillation frequency and a baseband reference frequency;
the different frequency dividers receive frequency signals from the same phase source, and the receiving local oscillation frequency and the baseband reference frequency have synchronous phase characteristics.
According to another aspect of the present application, there is provided a frequency allocation apparatus, the apparatus comprising:
the acquisition module is used for acquiring a reference frequency required by the phase-locked loop, wherein the reference frequency is generated by the reference frequency divider;
and the processing module is used for generating radio frequency related to the receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through different frequency dividers to respectively obtain the receiving local oscillation frequency and the baseband reference frequency.
According to another aspect of the present application, there is provided a receive path phase locked loop comprising: at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the frequency allocation method of any one of the embodiments of the present application.
According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute the frequency allocation method according to any one of the embodiments of the present application.
The embodiment of the application provides a Beidou radio frequency synthesizer, a method, a device, a phase-locked loop and a storage medium. The Beidou radio frequency synthesizer comprises a crystal oscillator, a reference frequency divider, a phase-locked loop and two different frequency dividers, wherein the phase-locked loop comprises a receiving path phase-locked loop and a transmitting path phase-locked loop; the crystal oscillator is connected with the reference frequency divider, and the reference frequency divider is also connected with the one transmitting path phase-locked loop and the one receiving path phase-locked loop respectively; the crystal oscillator is used for generating a reference frequency required by the phase-locked loop; the reference frequency divider is used for dividing the reference frequency to obtain the reference frequency required by the phase-locked loop; the transmitting path phase-locked loop is used for generating a transmitting local oscillation frequency required by Beidou signal transmitting modulation according to the reference frequency; the receiving path phase-locked loop is used for generating radio frequency related to a receiving path according to the reference frequency, and dividing the radio frequency by two different frequency dividers to respectively obtain the local oscillation frequency and the baseband reference frequency of the receiver. The application solves the problems of high consumption and high cost of the frequency synthesizer in the prior art by adopting the double phase-locked loop design, and can reduce the power consumption and the cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a beidou short message frequency synthesizer provided in the prior art;
fig. 2 is a schematic structural diagram of a beidou rf frequency synthesizer according to a first embodiment of the present application;
fig. 3 is a schematic diagram of generating a digital intermediate frequency signal according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another beidou rf frequency synthesizer according to an embodiment of the present application;
fig. 5 is a flow chart of a frequency allocation method according to a second embodiment of the present application;
fig. 6 is a schematic structural diagram of a frequency allocation device according to a third embodiment of the present application;
fig. 7 is a schematic structural diagram of a receiving-path pll according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application. It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
The names of messages or information interacted between the devices in the embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of such messages or information.
Example 1
Fig. 2 is a schematic structural diagram of a beidou radio frequency synthesizer provided by the first embodiment of the present application, where the present embodiment may be suitable for a situation of frequency allocation, and the beidou radio frequency synthesizer may be implemented by using hardware and/or hardware, and may execute a frequency allocation method provided by the present application.
As shown in fig. 2, a beidou rf frequency synthesizer provided in the first embodiment of the present application includes a crystal oscillator 10, a reference frequency divider 20, a phase-locked loop and two different frequency dividers 50, where the phase-locked loop includes a receiving path phase-locked loop 40 and a transmitting path phase-locked loop 30;
the crystal oscillator 10 is connected with the reference frequency divider 20, and the reference frequency divider 20 is also connected with a transmitting path phase-locked loop 30 and a receiving path phase-locked loop 40 respectively;
a crystal oscillator 10 for generating a reference frequency required for the phase-locked loop;
a reference frequency divider 20 for dividing the reference frequency to obtain a reference frequency required by the phase-locked loop;
a transmit path pll 30, configured to generate a transmit local oscillator frequency required for transmitting and modulating the beidou signal according to the reference frequency;
and a receiving path phase-locked loop 40, configured to generate a radio frequency related to the receiving path according to the reference frequency, and divide the radio frequency by two different frequency dividers 50 to obtain a receiver local oscillation frequency and a baseband reference frequency, respectively.
The crystal oscillator 10 may be an electronic oscillator circuit for vibrating the mechanical resonance of a crystal of piezoelectric material. The crystal oscillator frequency may be the frequency generated by crystal oscillator 10. The reference frequency divider 20 may be a frequency divider that performs reference frequency division. The phase locked loop reference frequency may be a reference frequency of a phase locked loop.
In this embodiment, the crystal oscillator 10 may be connected to the reference frequency divider 20 to send the generated crystal oscillator frequency to the reference frequency divider 20, and after receiving the crystal oscillator frequency, the reference frequency divider 20 may divide the crystal oscillator frequency by a reference frequency to obtain a pll reference frequency, and send the pll reference frequency to the transmit path pll 30 and the receive path pll 40.
The phase-locked loop refers to a circuit or a module for processing a received signal and extracting phase information of a certain clock from the signal. The phase-locked loop can control the frequency and the phase of an oscillation signal in the loop by utilizing an externally input reference signal, so that the automatic tracking of the output signal frequency to the input signal frequency is realized, and the phase-locked loop is generally used for a closed-loop tracking circuit. The transmit path phase locked loop 30 may be a phase locked loop for the transmit path and the transmit carrier frequency may be a carrier frequency generated by the transmit path phase locked loop 30. The receive path phase locked loop 40 may be a phase locked loop for the receive path and the radio frequency may be the frequency generated by the receive path phase locked loop 40.
The frequency divider 50 is a basic device of a sequential circuit, and the frequency divider 50 can divide a system clock or other clocks to generate required clock signals. The receiver local oscillator frequency may be a local oscillator frequency of the receiver. The local oscillation frequency can be generated by a local oscillation circuit and can be used in a superheterodyne receiver. The baseband reference frequency may be a reference frequency of the baseband. The baseband may be a frequency band (frequency bandwidth) inherent to an original electric signal which is sent out by a transmitting end and is not modulated (frequency spectrum shifting and transforming), and is called a baseband for short. The baseband is a special frequency bandwidth with a frequency range around zero frequency (from dc to several hundred KHz).
In this embodiment, the transmit path pll 30 may receive the pll reference frequency sent by the base divider 20, and may generate a corresponding transmit carrier frequency according to the pll reference frequency. After the receiving path pll 40 receives the pll reference frequency sent by the reference frequency divider 20, the pll reference frequency may divide its own rf frequency by two different frequency dividers 50 to obtain the receiver local oscillator frequency and the baseband reference frequency.
Alternatively, the frequency division processing may include integer frequency division and fractional frequency division. The integer frequency division may be based on an integer, and the integer frequency division may also include an even frequency division and an odd frequency division. For example, integer divide may include divide by 2, divide by 5, divide by 6, divide by 76, and so on.
In this embodiment, the different frequency dividers receive frequency signals from the same phase source, and the receiving local oscillation frequency and the baseband reference frequency have synchronous phase characteristics.
It will be appreciated that the division of the radio frequency by the different frequency dividers 50 enables the receiver local oscillator frequency f2 and the baseband reference frequency f3 to be derived from the division of the output frequency of the same receive path pll, enabling the receiver local oscillator frequency f2 and the baseband reference frequency f3 to have synchronized phase characteristics. The first embodiment of the present application provides a Beidou radio frequency synthesizer, which comprises a crystal oscillator 10, a reference frequency divider 20, a phase-locked loop and two different frequency dividers 50, wherein the phase-locked loop comprises a receiving path phase-locked loop 40 and a transmitting path phase-locked loop 30; the crystal oscillator 10 is connected with the reference frequency divider 20, and the reference frequency divider 20 is also connected with a transmitting path phase-locked loop 30 and a receiving path phase-locked loop 40 respectively; a crystal oscillator 10 for generating a reference frequency required for the phase-locked loop; a reference frequency divider 20 for dividing the reference frequency to obtain a reference frequency required by the phase-locked loop; a transmit path pll 30, configured to generate a transmit local oscillator frequency required for transmitting and modulating the beidou signal according to the reference frequency; and a receiving path phase-locked loop 40, configured to generate a radio frequency related to the receiving path according to the reference frequency, and divide the radio frequency by two different frequency dividers 50 to obtain a receiver local oscillation frequency and a baseband reference frequency, respectively. The application adopts the double phase-locked loop design to carry out the co-integration design of the receiving phase-locked loop and the baseband processing phase-locked loop, thereby reducing one phase-locked loop, reducing the power consumption, simultaneously reducing the complexity of chip design and the cost of chips, and solving the problems of high power consumption and high cost of a frequency synthesizer in the prior art.
In one embodiment, two different frequency dividers 50 include a first frequency divider and a second frequency divider;
the frequency division number of the first frequency divider is preset by a user, and the first frequency divider is used for generating receiving local oscillation frequency;
the frequency division number of the second frequency divider is preset by a user, and the second frequency divider is used for generating a baseband reference frequency;
the receiving local oscillation frequency performs down-conversion processing on the receiving Beidou signal, and obtains an analog intermediate frequency signal after intermediate frequency amplification and filtering; the baseband reference frequency is provided as a sampling clock frequency to the analog-to-digital converter; the analog intermediate frequency signal is sampled and quantized in the analog-to-digital converter based on the sampling clock frequency to obtain a digital intermediate frequency signal, and the phase of the digital intermediate frequency signal is related to the phase of the Beidou signal; the baseband reference frequency is also sent to digital baseband circuitry for digital signal processing.
The first frequency divider may be a frequency divider for generating a receive local oscillator frequency. The number of divisions may be the number of divisions by the divider. The number of divisions may be set by the user according to the actual situation, and for example, the number of divisions may be 2, 5, 6, 76 or any other number. The second frequency divider may be a frequency divider for generating a baseband reference frequency. The baseband analog-to-digital converter may be an analog-to-digital converter for baseband, which refers to a device that converts a continuously variable analog signal into a discrete digital signal. The down-conversion may be a processing mode in which the intermediate frequency signal obtained after the mixing is lower in emission than the original signal. The digital intermediate frequency signal may be a signal obtained by frequency conversion of a high frequency signal, the intermediate frequency is relative to a baseband signal and a radio frequency signal, the intermediate frequency may have one or more stages, and the intermediate frequency is a bridge for transition between the baseband and the radio frequency.
In this embodiment, two different frequency dividers, such as a first frequency divider and a second frequency divider, may be provided to generate the receive local oscillator frequency and the baseband reference frequency, respectively, where the baseband reference frequency may be used for the baseband analog-to-digital converter and the reference frequency for subsequent baseband decoding.
Fig. 3 is a schematic diagram illustrating generation of a digital intermediate frequency signal according to an embodiment of the present application. As shown in fig. 3, the receive path phase locked loop generates a receive local oscillator frequency f2 and a baseband reference frequency f3, which provide a sampling clock fs to the analog-to-digital converter ADC (i.e., f3=fs) and to subsequent digital baseband circuitry.
The method comprises the steps that a radio frequency signal (Beidou signal) RFin is subjected to down-conversion treatment by a receiving local oscillator f2, and after intermediate frequency amplification and filtering, an analog intermediate frequency A_IF is obtained; in the ADC, the analog intermediate frequency a_if is sampled and quantized by the sampling clock fs, so as to obtain a digital intermediate frequency d_if, and finally, the baseband reference frequency may be sent to a subsequent digital baseband circuit for digital signal processing (Digital Signal Processing, DSP).
If the initial transient phase of the received Beidou signal is: phi 0 (t) receiving a synchronous phase difference between the local oscillation frequency f2 and the baseband reference frequency f3 as delta phi (t), and sampling by the baseband analog-to-digital converter to obtain a digital intermediate frequency phase as follows: phi 0 (t) +ΔΦ (t) (ΔΦ (t) relative to Φ) 0 (t) is a high order small amount). Therefore, the phase of the digital intermediate frequency is mainly related to the phase of the input Beidou signal, and the decoding performance of the baseband signal can be effectively improved under the condition that delta phi (t) meets the stable random process. The embodiment is based on a double phase-locked loop, and can realize homologous phase synchronization of the receiving local oscillation frequency and the baseband reference frequency, so that the digital intermediate frequency phase is weakly related to the relative phase error of the receiving local oscillation frequency and the baseband reference frequency, and the decoding performance of the baseband is improved.
In one embodiment, the sampling clock frequency and the intermediate frequency signal satisfy the following condition:
the ratio of the sampling clock frequency to the maximum frequency of the analog intermediate frequency signal is greater than or equal to 2;
the sampling clock frequency is consistent with the center frequency of the digital intermediate frequency signal.
Wherein the center frequency may be a geometric average of the band pass filter (or band reject filter) frequencies. The bandwidth may be the difference between the highest frequency and the lowest frequency of a certain frequency band. The maximum frequency may be the maximum value of the frequency of the digital intermediate frequency signal.
In this embodiment, the ratio of the sampling clock frequency to the maximum frequency of the analog intermediate frequency signal needs to be greater than or equal to 2; the sampling clock frequency needs to be consistent with the center frequency of the digital intermediate frequency signal.
In one embodiment, the reference frequency generated by the crystal oscillator is 26MHz; the reference frequency of 26MHz is subjected to reference frequency division by the reference frequency divider to obtain the reference frequency of 1MHz required by the phase-locked loop; the receiving path phase-locked loop generates 5016MHz radio frequency according to the 1MHz reference frequency; the radio frequency of 5016MHz is subjected to frequency division by the first frequency divider to obtain the receiving local oscillation frequency of 2508MHz, and the transmitting local oscillation frequency of 5016MHz is subjected to frequency division by the second frequency divider to obtain the baseband reference frequency of 66MHz.
In this embodiment, the crystal oscillator frequency of the crystal oscillator is further set to 26MHz (the crystal oscillator of this frequency point is widely used and is good in price, which is beneficial to reducing the design cost of the whole module), and the frequency division number of different frequency dividers, so that the frequency distribution of the double phase-locked loop can be based, the phase-locked loop can obtain the required performance requirement by adopting integer frequency division, and the spurious and phase accumulation error problem caused by fractional frequency division is reduced. The 26MHz universal crystal oscillator is adopted, so that the product cost can be reduced. It is understood that the number of frequency divisions of the first frequency divider and the second frequency divider may be set to other values according to the actual situation.
Fig. 4 is a schematic structural diagram of another beidou rf frequency synthesizer according to an embodiment of the present application. As shown in fig. 4, the beidou radio frequency synthesizer of the embodiment can reasonably select the relationship between the baseband reference frequency f3 and the receiving local oscillation frequency f 2. The frequency of the selected crystal oscillator can be 26MHz, the reference frequency of the phase-locked loop of 1MHz is obtained after the reference frequency division of the reference frequency divider f0, the receiving path phase-locked loop generates the radio frequency of 5016MHz according to the reference frequency of the phase-locked loop, the radio frequency obtains the receiving local oscillation frequency f2 (2508 MHz) after the frequency division of 2, and the baseband reference frequency is 66MHz after the frequency division of 76. The phase-locked loop can adopt the integer frequency division principle, thereby reducing the problems of spurious and phase accumulation errors caused by fractional frequency division.
If the receiving frequency band of the Beidou 3-generation satellite radio navigation service (Radio Navigation Satellite System, RDSS) is 2491.75 MHz+ -8.16 MHz (i.e. 2483.59 MHz-2499.91 MHz), the generated digital intermediate frequency signal is 16.25 MHz+ -8.16 MHz (i.e. 8.09 MHz-24.41 MHz), and the ratio of the baseband reference frequency to the highest frequency of the data intermediate frequency signal is: 66 MHz/24.41 MHz approximately 2.7, where 2.7 > 2, it is apparent that the baseband reference frequency can meet the fundamental requirements of Nexter sampling.
Example two
Fig. 5 is a flow chart of a frequency allocation method according to a second embodiment of the present application, where the method is applicable to a case of allocating frequencies, and the method may be performed by a frequency allocation device, where the device may be implemented by software and/or hardware and is generally integrated on a receiving path pll.
As shown in fig. 5, a frequency allocation method provided in a second embodiment of the present application is performed by a receiving path phase-locked loop, and includes the following steps:
s210, acquiring a reference frequency required by the phase-locked loop, wherein the reference frequency is generated by a standard frequency divider.
The phase-locked loop may be a receive path phase-locked loop, and the reference frequency divider may be a frequency divider that performs reference frequency division. The reference frequency may be a reference frequency of a phase locked loop.
In this embodiment, the receive path pll may receive the reference frequency generated by the base divider.
S220, generating radio frequency related to a receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through two different frequency dividers to respectively obtain a receiving local oscillation frequency and a baseband reference frequency.
The different frequency dividers receive frequency signals from the same phase source, and the receiving local oscillation frequency and the baseband reference frequency have synchronous phase characteristics.
The radio frequency may be a frequency generated by a receive path phase locked loop. The frequency divider is a basic device of the timing circuit, and the frequency divider can divide a system clock or other clocks to generate a required clock signal. The receiver local oscillator frequency may be a local oscillator frequency of the receiver. The baseband reference frequency may be a reference frequency of the baseband.
In this embodiment, the receiving path pll may divide the radio frequency generated by itself by different frequency dividers according to the reference frequency, to obtain the receiver local oscillation frequencies and the baseband reference frequency of different frequencies.
The frequency allocation method provided by the second embodiment of the application comprises the following steps: acquiring a reference frequency required by a phase-locked loop, wherein the reference frequency is generated by a reference frequency divider; and generating radio frequency related to a receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through two different frequency dividers to respectively obtain a receiving local oscillation frequency and a baseband reference frequency. The radio frequency is divided by different frequency dividers according to the reference frequency of the phase-locked loop, so that the local oscillation frequency and the baseband reference frequency of the receiver are obtained, the problems of high consumption and high cost of the frequency synthesizer in the prior art are solved, and the power consumption and the cost can be reduced.
On the basis of the above embodiments, modified embodiments of the above embodiments are proposed, and it is to be noted here that only the differences from the above embodiments are described in the modified embodiments for the sake of brevity of description.
In one embodiment, the frequency division process includes, but is not limited to, integer frequency division.
The integer frequency division may be based on an integer, and the integer frequency division may also include an even frequency division and an odd frequency division.
In this embodiment, the frequency division processing may be performed on the radio frequency by selecting an integer division method, or other division processing methods may be selected. Integer frequency division may include divide by 2, divide by 5, divide by 6, divide by 76, and the like.
In one embodiment, the dividing the radio frequency by two different frequency dividers to obtain a receiving local oscillation frequency and a baseband reference frequency respectively includes:
generating a local oscillator frequency of the receiver by a first frequency divider; generating a baseband reference frequency by a second frequency divider;
the receiving local oscillation frequency performs down-conversion processing on the receiving Beidou signal, and obtains an analog intermediate frequency signal after intermediate frequency amplification and filtering; the baseband reference frequency is provided as a sampling clock frequency to the analog-to-digital converter; the analog intermediate frequency signal is sampled and quantized in the analog-to-digital converter based on the sampling clock frequency to obtain a digital intermediate frequency signal, and the phase of the digital intermediate frequency signal is related to the phase of the Beidou signal; the baseband reference frequency is also sent to digital baseband circuitry for digital signal processing.
Wherein the first frequency divider may be a frequency divider for generating a receiver local oscillator frequency. The second frequency divider may be a frequency divider for generating a baseband reference frequency. The baseband analog-to-digital converter may be an analog-to-digital converter for baseband, which refers to a device that converts a continuously variable analog signal into a discrete digital signal.
In this embodiment, two different frequency dividers, such as a first frequency divider and a second frequency divider, may be provided to generate the receiver local oscillator frequency and the baseband reference frequency, respectively, where the baseband reference frequency may be used for the baseband analog-to-digital converter and the reference frequency for subsequent baseband decoding.
In one embodiment, the sampling clock frequency and the intermediate frequency signal satisfy the following condition:
the ratio of the sampling clock frequency to the maximum frequency of the analog intermediate frequency signal is greater than or equal to 2;
the sampling clock frequency is consistent with the center frequency of the digital intermediate frequency signal.
The digital intermediate frequency signal may be a signal obtained by frequency-converting a high frequency signal. The digital intermediate frequency signal may be generated by a baseband analog-to-digital converter based on a baseband reference frequency. The center frequency may be a geometric average of the band pass filter (or band reject filter) frequencies. The bandwidth may be the difference between the highest frequency and the lowest frequency of a certain frequency band. The highest frequency may be the maximum of the frequency of the digital intermediate frequency signal.
In this embodiment, the baseband reference frequency generated by the second frequency divider needs to meet the corresponding condition that the center frequency of the digital intermediate frequency signal is consistent with the bandwidth of the digital center signal, the center frequency needs to be small enough (e.g. ten M), and the ratio of the baseband reference frequency to the highest frequency of the digital intermediate frequency signal should be greater than 2.
In one embodiment, the reference frequency generated by the reference frequency divider is obtained by performing reference frequency division on the crystal oscillator frequency generated by the crystal oscillator; wherein, the reference frequency generated by the crystal oscillator is 26MHz; the reference frequency of 26MHz is subjected to reference frequency division by the reference frequency divider to obtain the reference frequency of 1MHz required by the phase-locked loop; the receiving path phase-locked loop generates 5016MHz radio frequency according to the 1MHz reference frequency; the radio frequency of 5016MHz is subjected to frequency division by the first frequency divider to obtain the receiving local oscillation frequency of 2508MHz, and the transmitting local oscillation frequency of 5016MHz is subjected to frequency division by the second frequency divider to obtain the baseband reference frequency of 66MHz.
The crystal oscillator may be an electronic oscillator circuit for vibrating the mechanical resonance of the crystal of piezoelectric material. The crystal oscillator frequency may be the frequency generated by a crystal oscillator.
In this embodiment, the crystal oscillator frequency of the crystal oscillator may be set to 26MHz, the first frequency divider is set to divide by 2, and the second frequency divider is set to divide by 76, so that the frequency allocation of the dual phase-locked loop may be based on, so that the phase-locked loop may obtain the required performance requirement by adopting integer frequency division, and the spurious and phase accumulation error problem caused by fractional frequency division is reduced. The 26MHz universal crystal oscillator is adopted, so that the product cost can be reduced. It is understood that the number of frequency divisions of the first frequency divider and the second frequency divider may be set to other values according to the actual situation.
Example III
Fig. 6 is a schematic structural diagram of a frequency allocation device according to a third embodiment of the present application, which is applicable to a case of allocating frequencies, wherein the device may be implemented by software and/or hardware and is generally integrated on a receiving path phase-locked loop.
As shown in fig. 6, the apparatus includes:
an acquisition module 310 for acquiring a reference frequency required by the phase-locked loop, the reference frequency being generated by a reference frequency divider;
and the processing module 320 is configured to generate a radio frequency related to the receiving channel according to the reference frequency, and divide the radio frequency by different frequency dividers to obtain a receiving local oscillator frequency and a baseband reference frequency respectively.
A third embodiment of the present application provides a frequency allocation apparatus, including: an acquisition module 310 for acquiring a reference frequency required by the phase-locked loop, the reference frequency being generated by a reference frequency divider; and the processing module 320 is configured to generate a radio frequency related to the receiving channel according to the reference frequency, and divide the radio frequency by different frequency dividers to obtain a receiving local oscillator frequency and a baseband reference frequency respectively. The radio frequency is divided by different frequency dividers according to the reference frequency of the phase-locked loop, so that the local oscillation frequency and the baseband reference frequency of the receiver are obtained, the problems of high consumption and high cost of the frequency synthesizer in the prior art are solved, and the power consumption and the cost can be reduced.
Further, the different frequency dividers receive frequency signals from the same phase source, and the received local oscillator frequency and the baseband reference frequency have synchronous phase characteristics.
Further, the frequency division process includes, but is not limited to, integer frequency division.
Further, the processing module 320 includes:
generating a local oscillator frequency of the receiver by a first frequency divider; generating a baseband reference frequency by a second frequency divider;
the receiving local oscillation frequency performs down-conversion processing on the receiving Beidou signal, and obtains an analog intermediate frequency signal after intermediate frequency amplification and filtering; the baseband reference frequency is provided as a sampling clock frequency to the analog-to-digital converter; the analog intermediate frequency signal is sampled and quantized in the analog-to-digital converter based on the sampling clock frequency to obtain a digital intermediate frequency signal, and the phase of the digital intermediate frequency signal is related to the phase of the Beidou signal; the baseband reference frequency is also sent to digital baseband circuitry for digital signal processing.
Further, the sampling clock frequency and the intermediate frequency signal satisfy the following conditions:
the ratio of the sampling clock frequency to the maximum frequency of the analog intermediate frequency signal is greater than or equal to 2;
the sampling clock frequency is consistent with the center frequency of the digital intermediate frequency signal.
Further, the reference frequency generated by the reference frequency divider is obtained by performing reference frequency division on the crystal oscillator frequency generated by the crystal oscillator; wherein, the reference frequency generated by the crystal oscillator is 26MHz; the reference frequency of 26MHz is subjected to reference frequency division by the reference frequency divider to obtain the reference frequency of 1MHz required by the phase-locked loop; the receiving path phase-locked loop generates 5016MHz radio frequency according to the 1MHz reference frequency; the radio frequency of 5016MHz is subjected to frequency division by the first frequency divider to obtain the receiving local oscillation frequency of 2508MHz, and the transmitting local oscillation frequency of 5016MHz is subjected to frequency division by the second frequency divider to obtain the baseband reference frequency of 66MHz.
The frequency allocation device can execute the frequency allocation method provided by any embodiment of the application, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 7 shows a schematic diagram of a receive path phase locked loop that may be used to implement an embodiment of the present application. As shown in fig. 7, the receive path phase locked loop includes: at least one processor 41 and a memory 42 communicatively coupled to the at least one processor. In fig. 7, a processor 41 is taken as an example; a processor 41 and a memory 42 in the receive path phase locked loop, in fig. 7 by way of example a bus connection.
The memory 42 is a computer readable storage medium, and may be used to store a software program, a computer executable program, and modules, such as program instructions/modules corresponding to the frequency allocation method in the embodiment of the present application. The processor 41 executes various functional applications of the receive path phase locked loop and data processing, i.e. implements the frequency allocation method described above, by running software programs, instructions and modules stored in the memory 42.
The memory 42 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the terminal, etc. In addition, memory 42 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, memory 42 may further comprise memory remotely located with respect to processor 41, which may be connected to the receive path phase locked loop through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present application are achieved, and the present application is not limited herein.
The above embodiments do not limit the scope of the present application. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of the present application.

Claims (10)

1. The Beidou radio frequency synthesizer is characterized by comprising a crystal oscillator, a reference frequency divider, a phase-locked loop and two different frequency dividers, wherein the phase-locked loop comprises a receiving path phase-locked loop and a transmitting path phase-locked loop;
the crystal oscillator is connected with the reference frequency divider, and the reference frequency divider is also connected with the one transmitting path phase-locked loop and the one receiving path phase-locked loop respectively;
the crystal oscillator is used for generating a reference frequency required by the phase-locked loop;
the reference frequency divider is used for dividing the reference frequency to obtain the reference frequency required by the phase-locked loop;
the transmitting path phase-locked loop is used for generating a transmitting local oscillation frequency required by Beidou signal transmitting modulation according to the reference frequency;
the receiving path phase-locked loop is used for generating radio frequency related to a receiving path according to the reference frequency, and dividing the radio frequency by two different frequency dividers to respectively obtain the local oscillation frequency and the baseband reference frequency of the receiver.
2. The Beidou RF frequency synthesizer of claim 1 wherein,
the different frequency dividers receive frequency signals from the same phase source, and the received local oscillator frequency and the baseband reference frequency have synchronous phase characteristics.
3. The Beidou radio frequency synthesizer of claim 1, wherein the frequency division process includes, but is not limited to, integer frequency division.
4. The beidou rf frequency synthesizer of claim 1 wherein the two different frequency dividers include a first frequency divider and a second frequency divider;
the frequency division number of the first frequency divider is preset by a user, and the first frequency divider is used for generating receiving local oscillation frequency;
the frequency division number of the second frequency divider is preset by a user, and the second frequency divider is used for generating a baseband reference frequency;
the receiving local oscillation frequency performs down-conversion processing on the receiving Beidou signal, and obtains an analog intermediate frequency signal after intermediate frequency amplification and filtering; the baseband reference frequency is provided as a sampling clock frequency to the analog-to-digital converter; the analog intermediate frequency signal is sampled and quantized in the analog-to-digital converter based on the sampling clock frequency to obtain a digital intermediate frequency signal, and the phase of the digital intermediate frequency signal is related to the phase of the Beidou signal; the baseband reference frequency is also sent to digital baseband circuitry for digital signal processing.
5. A beidou radio frequency synthesizer according to claim 3, wherein said sampling clock frequency and said intermediate frequency signal satisfy the following condition:
the ratio of the sampling clock frequency to the maximum frequency of the analog intermediate frequency signal is greater than or equal to 2;
the sampling clock frequency is consistent with the center frequency of the digital intermediate frequency signal.
6. The Beidou radio frequency synthesizer of claim 4 wherein the crystal oscillator generates a reference frequency of 26MHz; the reference frequency of 26MHz is subjected to reference frequency division by the reference frequency divider to obtain the reference frequency of 1MHz required by the phase-locked loop; the receiving path phase-locked loop generates 5016MHz radio frequency according to the 1MHz reference frequency; the radio frequency of 5016MHz is subjected to frequency division by the first frequency divider to obtain the receiving local oscillation frequency of 2508MHz, and the transmitting local oscillation frequency of 5016MHz is subjected to frequency division by the second frequency divider to obtain the baseband reference frequency of 66MHz.
7. A method of frequency allocation performed by a receive path phase locked loop, the method comprising:
acquiring a reference frequency required by a phase-locked loop, wherein the reference frequency is generated by a reference frequency divider;
generating a radio frequency related to a receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through two different frequency dividers to respectively obtain a receiving local oscillation frequency and a baseband reference frequency;
the different frequency dividers receive frequency signals from the same phase source, and the receiving local oscillation frequency and the baseband reference frequency have synchronous phase characteristics.
8. A frequency allocation apparatus, the apparatus comprising:
the acquisition module is used for acquiring a reference frequency required by the phase-locked loop, wherein the reference frequency is generated by the reference frequency divider;
and the processing module is used for generating radio frequency related to the receiving channel according to the reference frequency, and carrying out frequency division processing on the radio frequency through different frequency dividers to respectively obtain the receiving local oscillation frequency and the baseband reference frequency.
9. A receive path phase locked loop, the receive path phase locked loop comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the frequency allocation method of claim 6.
10. A computer readable storage medium storing computer instructions for causing a processor to perform the frequency allocation method of claim 6.
CN202310667690.5A 2023-06-06 2023-06-06 Beidou radio frequency synthesizer, method, device, phase-locked loop and storage medium Pending CN116667847A (en)

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