CN103684445A

CN103684445A - Multiphase high-resolution phase locked loop

Info

Publication number: CN103684445A
Application number: CN201210334324.XA
Authority: CN
Inventors: 不公告发明人
Original assignee: CHENGDU RUICHENG XINWEI TECHNOLOGY Co Ltd
Current assignee: Chengdu Rui core micro Polytron Technologies Inc
Priority date: 2012-09-11
Filing date: 2012-09-11
Publication date: 2014-03-26
Anticipated expiration: 2032-09-11
Also published as: CN103684445B

Abstract

The invention discloses a high-resolution phase locked loop. The high-resolution loop phase locked loop comprises an input frequency divider, a phase detector connected with a reference frequency divider, a low pass filter connected with the phase detector, a voltage-controlled oscillator connected with the low pass filter, a multiphase loop frequency divider connected with the voltage-controlled oscillator and a phase frequency detector, and an output frequency divider connected with the voltage-controlled oscillator. The high-resolution phase locked loop provides high-resolution and low-noise clock signals, and the multiphase loop frequency divider provides high-resolution feedback signals for the phase frequency detector. The high-resolution phase locked loop improves the resolution of output signals of a phase locked loop in conditions of reducing loop analysis difficulty and reducing resource consumption.

Description

Leggy high-resolution phase-locked loop

Technical field

The present invention relates to frequency retrieval and synthetic technology, be specifically related to a kind of leggy high-resolution phase-locked loop.

Background technology

Phase-locked loop, in modern electronic technology, is widely used.In microprocessor, utilize phase-locked loop to provide high-quality system clock for system.At wireless communication field, utilize PHASE-LOCKED LOOP PLL TECHNIQUE to carry out Up/Down Conversion, modulation /demodulation etc.

Phase-locked loop basic structure is by phase frequency detector (FPD), low pass filter (LPF), voltage controlled oscillator (VCO).Phase discriminator produces the voltage with the linear ratio of phase difference; Low pass filter is used for suppressing the radio-frequency component of phase discriminator output voltage; Voltage controlled oscillator vibrates and exports respective frequencies signal under the control of low pass filter output voltage signal; Loop divider (1/N) provides feedback clock for phase frequency detector; Between input reference clock and phase frequency detector, insert an input frequency divider (1/Q), at the output of voltage controlled oscillator, insert an output frequency divider (1/M), to improve resolution; When input is fr with reference to s clock frequency, output frequency fout is:

f_{out} = \frac{f_{r} * N}{q * M}

According to the output resolution ratio of above formula phase-locked loop, by variable Q and M, determined, can regulate the value of Q, M and N to control output frequency resolution rate.Conventionally by regulating the value of Q, M and N to improve resolution, be very limited; Regulate Q to improve resolution, essence is to reduce the frequency of the reference clock of input phase discriminator, and general low reference frequency requires the less bandwidth of low pass filter, reduces loop bandwidth, has increased output noise; If regulate M to improve output resolution ratio, will make voltage controlled oscillator output frequency just need to raise, voltage controlled oscillator output frequency has the upper limit, and high output frequency causes the increase of power consumption; The resolution that regulates Q and M to obtain is very limited.In actual application, often need higher resolution, the phase-locked loop of traditional structure cannot satisfy the demands.The phase-locked loop of bimodulus decimal frequency divider structure and the phase-locked loop of delta sigma structure had been there is afterwards.

Bimodulus fractional frequency division principle is exactly in the cycle, to make many meters of certain several cycle or to count less a number at several frequency divisions, thus the result that is corresponding fractional frequency division at the mean value of the output frequency of a period of time inner ring road frequency divider.For example to realize A/B frequency division, within B cycle, export A cycle and just can realize fractional frequency division.But A cycle do not equate completely, and the output signal of loop divider has very large jitter.The advantage of this structure is, improved the resolution of output frequency, realizes simple; Shortcoming is that loop cannot suppress the low-frequency noise that has fractional frequency division to produce, therefore output signal to noise ratio is larger;

The principle of Delta_sigma phase-locked loop produces loop frequency-dividing ratio with Delta_sigma modulator, pushes the noise of loop divider to high band, and the low pass filter of the noise of high frequency in phase-locked loop suppresses.Delta_sigma phase-locked loop is widely used in radio communication.Delta_sigma phase-locked loop advantage is that output resolution ratio is high, and noise is low; Shortcoming is that loop design analysis is too complicated, and Delta_sigma modulator is the problem of existence and stability also, and design work amount is very large;

Summary of the invention

In view of above content, be necessary to provide a kind of design analysis simple, be easy to realize, possess high score resolution, low noise phase-locked loop.

A high-resolution phase-locked loop, described high-resolution phase-locked loop comprises a parametric frequency divider, a phase discriminator being connected with described parametric frequency divider, a low pass filter being connected with described phase discriminator, a voltage controlled oscillator being connected with described low pass filter, a leggy loop divider being connected with described phase frequency detector with described voltage controlled oscillator, an output frequency divider being connected with described sub-controlled oscillator.Described high-resolution phase-locked loop provides high-resolution low noise clock signal, and described leggy loop divider provides high-resolution feedback signal for described phase frequency detector.The present invention is reducing loop analysis difficulty and is reducing the resolution that has improved pll output signal in resource overhead situation.

The present invention utilizes leggy frequency divider to complete loop frequency division, obtains higher resolution and does not introduce the feedback signal of too high noise; Guarantee phase-locked loop low noise high resolution output; Simple in structure being easy to of leggy loop divider realized;

Accompanying drawing explanation

Fig. 1 is leggy high-resolution phase-locked loop.

Fig. 2 is leggy loop divider.

Embodiment

In Fig. 1: DIVQ. inputs frequency divider; PD. phase discriminator; LP. low pass filter; VCO. voltage controlled oscillator; DIVM. output frequency divider; DIVNK. leggy loop divider;

In Fig. 2: dual-mode frequency divider; Phase controller; D type flip flop DFF ₀, DFF ₁, DFF ₂, DFF _k-1; MUX. MUX;

Below in conjunction with accompanying drawing, the present invention is elaborated.

Leggy high-resolution phase-locked loop, core concept be to utilize the multi-phase signals of voltage controlled oscillator output to carry out the fractional frequency division of zero jitter.So only need to solve and how to obtain multi-phase signals and how to utilize leggy to carry out the fractional frequency division of zero jitter.

In described Fig. 1, input signal fin is connected with input frequency device, by input frequency divider, carries out 1/Q frequency division; The output of input frequency divider is connected with phase-locked loop phase frequency detector reference signal end; The output of phase discriminator is connected with the input of low pass filter, by low pass filter, filters high-frequency noise; The output of low pass filter is connected with the input of voltage controlled oscillator, and voltage controlled oscillator adopts ring oscillator, and multi-phase clock signal output is provided; The multi-phase clock signal P of voltage controlled oscillator output ₀-P _k-1yi road is connected with the input of output frequency divider, by output frequency divider, is undertaken exporting after 1/M frequency division; The multi-phase clock signal CLKP of the multi-phase clock signal of voltage controlled oscillator output ₀-CLKP _k-1be connected with the input of leggy loop divider, leggy frequency divider utilizes multi-phase signals to carry out N+j/K frequency division; The output of leggy frequency divider is connected with the feedback end of phase-locked loop phase discriminator.

In described Fig. 2, decimal frequency dividing control word is connected with the input of zero phase clock signal clk P0 and dual-mode frequency divider; The output signal of dual-mode frequency divider is connected with the D end of d type flip flop DFF0-DFFK-1 respectively; Multi-phase clock signal CLKP0-CLKPK-1 holds the CK end being connected to be connected with the D of d type flip flop DFF0-DFFK-1 respectively; The output signal of fractional frequency division control word and dual-mode frequency divider is connected with the input of phase controller; The SEL end of the output of phase controller and MUX MUX is connected; The Q end of d type flip flop DFF0-DFFK-1 is connected with the A0-AK-1 end of MUX respectively; Finally by DEC_OUT, exported;

VCO in phase-locked loop adopts ring oscillator to be easy to just can obtain the multi-phase signals of needs.Ring oscillator is by some stage gain the electric circuit constitutes.The resulting signal frequency of each node of these gain circuitries is the same, but they exist phase difference.The progression of suitably choosing gain circuitry can be easy to obtain the multi-phase signals that many designs need, for leggy frequency divider improves multi-phase signals;

Leggy fractional frequency division is emphasis of the present invention, and its performance directly affects the performance of phase-locked loop.First utilize dual-mode frequency divider to multi-phase signals CLKP ₀do N+j/K fractional frequency division; Bimodulus refers to N and N+1; Utilize leggy handoff technique to offset the one-period that dual-mode frequency divider increases or reduces.Dual-mode frequency divider can utilize following methods to realize: design one register DEC superposes to decimal j, and when the value of DEC is greater than 1, mould is got N+1, register DEC zero clearing simultaneously, and ready for calculating next time, all the other situation moulds are got N; Work as CLKP ₀-CLKP _k-1to dual-mode frequency divider output signal sampling obtain frequency equate adjacent phase poor be the K road signal (DIVP of 2*pi/K ₀-DIVP _k-1).DIVP ₀-DIVP _k-1the adjacent periods of signal may not equate completely, has very large jitter.Utilize phase controller to produce Phase-switching control word, then select corresponding signal to export by MUX.Phase-switching controller principle is: i is the subscript of the DIVP of current selection signal, and so next selection signal is DIVPx (x=i+j when i+j<k-1; When i+j >=k-1, x=i+j-k).Final output signal (DIV_DEC) is the zero jitter signal all equating in a cycle.DIV_DEC is the N+j/K fractional frequency signal of CLKP.DIV_DEC is sent into phase discriminator, obtain high-resolution output signal.Leggy loop divider can complete 1/k+N to (k-1)/k+N frequency division, exports so input signal resolution and improves k doubly.

The present invention utilizes leggy handoff technique to complete the fractional frequency division of the zero jitter of loop divider, improves the output resolution ratio of this phase-locked loop and guarantees low noise output.

Claims

1. one input frequency divider, a phase discriminator being connected with described parametric frequency divider, a low pass filter being connected with described phase discriminator, a voltage controlled oscillator being connected with described low pass filter, a leggy loop divider being connected with described phase frequency detector with described voltage controlled oscillator, an output frequency divider being connected with described sub-controlled oscillator.

2. high-resolution phase-locked loop described in claim 1, is characterized in that: the leggy loop divider of being with comprises a dual-mode frequency divider; One phase controller being connected with described dual-mode frequency divider; K the trigger DFF being connected with described dual-mode frequency divider ₀, DFF ₁, DFF ₂, DFF _k-1; The one selector MUX being connected with described trigger.