CN113872596A - Fractional prescaler for phase-locked loop containing multiphase oscillator - Google Patents
Fractional prescaler for phase-locked loop containing multiphase oscillator Download PDFInfo
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- 238000013461 design Methods 0.000 abstract description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
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Abstract
The invention discloses a decimal prescaler for a phase-locked loop containing a multiphase oscillator, which belongs to the technical field of high-speed simulation and radio frequency chip design, and when the four-mode decimal prescaler (quad-module fractional prescaler) is matched with the multiphase oscillator in the phase-locked loop for use, decimal frequency division is realized through phase switching so as to reduce phase noise generated by a sum-difference modulator (SDM) of an output clock of the phase-locked loop, and the decimal prescaler and a programmable frequency divider are combined into a loop feedback frequency divider so as to reduce the lower limit of the continuous frequency division ratio of the whole loop feedback frequency divider; the invention can obviously reduce the phase noise generated by SDM of the output clock of the phase-locked loop after the decimal prescaler is configured in the phase-locked loop, and the decimal prescaler is combined with the programmable frequency divider to form the loop feedback frequency divider, so that the lower limit of the continuous frequency dividing ratio of the whole loop feedback frequency divider can be reduced, therefore, the phase-locked loop chip adopting the invention does not need to additionally increase a multiphase output divider, and the power consumption and the area of the chip are obviously reduced.
Description
Technical Field
The invention belongs to the technical field of high-speed simulation and radio frequency chip design, and particularly relates to a fractional prescaler for a phase-locked loop containing a multiphase oscillator.
Background
With the increasing progress of radio frequency and microwave communication technology and semiconductor technology, the operating frequency standard of wireless communication chips is also higher and higher. For example, ultra-wideband (UWB) maximum operating frequencies reach 10.6-GHz, while the latest WLAN band standard (802.11ad) defines microwave Wi-Fi with a frequency of 60 GHz. The first challenge of chip design is the design technique of frequency synthesizer (frequency synthesizer) with such high frequency, and the high-speed prescaler is usually the speed bottleneck of the frequency synthesizer.
In some applications, such as laser communication contained in high-end MCUs, a laser transmitter drive current is required to generate a specific waveform. Such waveforms may be synthesized by the superposition of the outputs of multiple digital-to-analog converters (DACs) driven by multiphase clocks. The structure of a conventional pll frequency synthesizer is shown in fig. 1. In the example of fig. 1, we need to generate 20 phases of clock outputs around 500MHz, i.e. the phase difference between adjacent clocks is 18 °. The disadvantage of this conventional structure is that the oscillator frequency is very high, up to 10 GHz. Thus requiring a high-speed and expensive chip processing process. Moreover, three modules in the whole phase-locked loop, namely an oscillator, a prescaler and a multiphase output divider, operate at such high frequency, so that the power consumption and the area of the chip are remarkably increased.
Disclosure of Invention
The invention aims to provide a decimal prescaler for a phase-locked loop containing a multiphase oscillator, wherein the decimal prescaler is arranged in the phase-locked loop, so that the phase noise generated by a sum-difference modulator (SDM) of an output clock of the phase-locked loop can be obviously reduced, and the decimal prescaler and a programmable frequency divider are combined to form a loop feedback frequency divider, so that the lower limit of the continuous frequency dividing ratio of the whole loop feedback frequency divider can be reduced.
In order to achieve the purpose, the invention provides the following technical scheme: when the four-modulus fractional prescaler is matched with the multi-phase oscillator in the phase-locked loop for use, fractional frequency division is realized through phase switching so as to reduce phase noise generated by a sum-difference modulator (SDM) of an output clock of the phase-locked loop, and the fractional prescaler and a programmable frequency divider are combined into a loop feedback frequency divider so as to reduce the lower limit of the continuous frequency dividing ratio of the whole loop feedback frequency divider.
Preferably, the fractional prescaler switches from a lagging phase to a leading phase.
Preferably, the fractional prescaler is a four-mode phase-shifted fractional divider.
Preferably, the four-mode phase-shifted fractional divider comprises:
the phase shift control module is used for deciding the selection of the next phase according to the current clock phase and the phase shift control;
and the phase selection module is used for selecting the phase corresponding to the control bit as the output of the prescaler.
Preferably, the multiphase oscillator generates 20 phases by 10 differential inverters, and the differential input and differential output of each differential inverter are 180 ° out of phase.
Preferably, the delay of the differential inverters themselves is equal to 18 ° of phase, and in a phase locked loop the delay of all differential inverters in a multiphase oscillator is controlled by voltage or current.
Compared with the prior art, the invention has the beneficial effects that:
(1) the present invention avoids the high speed and expensive chip processing requirements by reducing the maximum operating frequency.
(2) The invention reduces the power consumption and area of the chip by reducing the highest working frequency.
(3) The invention successfully realizes the multi-mode fractional prescaler based on phase shift.
(4) The invention reduces the lower limit of the continuous frequency dividing ratio of the total loop frequency divider by four-modulus fractional pre-frequency division.
(5) The invention can be widely applied to the phase-locked loop frequency synthesizer which needs multiphase clock output.
Drawings
Fig. 1 is a conventional phase locked loop for multiphase clock outputs.
Fig. 2 is a phase locked loop for a multiphase clock output of the present invention.
Fig. 3 is an oscillator of the 20-phase clock output of the present invention.
Fig. 4 is a phase relationship diagram of the 20-phase output clock of the present invention.
Fig. 5 is a four-modulus fractional division principle of the present invention based on phase shifting implementation.
Fig. 6 is a four mode phase shifted fractional divider of the present invention.
Fig. 7 is a digital logic circuit implementation of the phase shift control of the present invention.
Fig. 8 is a phase shift control and division ratio of the present invention.
Fig. 9 is the phase selection digital logic of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, the fractional prescaler for a phase-locked loop including a multi-phase oscillator, when the four-modulus fractional prescaler is used in cooperation with the multi-phase oscillator in the phase-locked loop, realizes fractional frequency division through phase switching to reduce phase noise generated by a sum-difference modulator (SDM) of an output clock of the phase-locked loop, and combines with a programmable frequency divider to form a loop feedback frequency divider to reduce a lower limit of a continuous division ratio of the overall loop feedback frequency divider.
As shown in fig. 5, the principle of fractional division by phase switching, or phase shifting, is explained. Assuming that the current fractional divider output phase corresponds to the oscillator output clock P9, if the phase is not switched, the division ratio of the prescaler can be considered to be 1. If we start switching to the oscillator output clock P7 after the rising edge of the prescaler output clock, then the next pout period is 36 deg. shorter oscillator phase. That is, the dynamic divide ratio corresponding to the prescaler is a fractional number, 18/20. Similarly, the dynamic divide ratio when pout switches from P7 to P4 is fractional, 17/20. Still next, the dynamic divide ratio when switching from is fractional, 16/20.
As an embodiment of the present invention, the fractional prescaler switches from a lagging phase to a leading phase. This arrangement has two benefits: firstly, the circuit delay in the switching process does not need to be accurately controlled and can be finished in a quite wide time window; on the output clock of the prescaler, frequency division errors caused by burr generation can be avoided. Second, a presorting ratio of less than 1 and up to four presorting modules helps to achieve a smaller lower bound on the continuous division ratio.
As one embodiment of the present invention, the fractional prescaler is a four mode phase shifted fractional divider.
As an embodiment of the present invention, the four-mode phase-shifted fractional divider comprises:
the phase shift control module is used for deciding the selection of the next phase according to the current clock phase and the phase shift control;
and the phase selection module is used for selecting the phase corresponding to the control bit as the output of the prescaler.
As shown in fig. 6 and 7, in fig. 6, the input RSTZ sets the phase of the output clock at the initial time. The phase SHIFT control module determines the selection (SEL <0:19>) of the next phase, i.e. how much the phase is shifted forward from the current phase, based on the current clock (CLK, pout) phase and the phase SHIFT control (SHIFT <1:0 >). The 20-bit selection of 20 phases, SEL <0:19>, has only one active high and the other 19 inactive low. The function of the phase selection module is simple and direct, namely selecting the phase corresponding to the control bit to be output by the prescaler.
As shown in fig. 7, initially RSTZ is active low, outputting phase selection P0; after RSTZ becomes invalid, from this point on, each output clock period determines whether to SHIFT phase or not and how much to SHIFT phase, i.e. the fractional prescaler ratio of the transient state, according to the phase SHIFT control, SHIFT <1:0 >.
As shown in fig. 8, if the select control bit for which phase is high, that phase is selected as the output of the prescaler. In practical circuit implementation, to minimize phase error, the circuit delay to the output when each phase is selected needs to be designed to be the same without systematic delay mismatch (delay mismatch); meanwhile, according to the requirement of system indexes, the random delay adaptation is reduced.
As an embodiment of the present invention, as shown in fig. 3, the multiphase oscillator generates 20 phases by 10 differential inverters, and a differential input and a differential output phase difference of each differential inverter is 180 °.
As an embodiment of the present invention, as shown in fig. 3, the delay of the differential inverter itself is equal to a phase of 18 °, and in the phase-locked loop, the delay of all the differential inverters in the multiphase oscillator is controlled by voltage or current.
As shown in FIG. 4, the adjacent phase differences noted P <0:19> or P0-P19 in the 20-phase output clock are 18.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The decimal prescaler is used for a phase-locked loop containing a multiphase oscillator, and is characterized in that when the four-modulus decimal prescaler is matched with the multiphase oscillator in the phase-locked loop for use, decimal frequency division is realized through phase switching so as to reduce phase noise generated by a sum-difference modulator (SDM) of an output clock of the phase-locked loop, and the decimal prescaler and a programmable frequency divider are combined into a loop feedback frequency divider so as to reduce the lower limit of the continuous frequency division ratio of the whole loop feedback frequency divider.
2. The fractional prescaler of claim 1, wherein the fractional prescaler switches from a lagging phase to a leading phase.
3. The fractional prescaler of claim 1 or 2 for use in a phase locked loop comprising a multiphase oscillator, wherein the fractional prescaler is a four mode phase shifted fractional divider.
4. The fractional prescaler for a phase locked loop containing a multiphase oscillator of claim 3, wherein the four mode phase shifted fractional divider comprises:
the phase shift control module is used for deciding the selection of the next phase according to the current clock phase and the phase shift control;
and the phase selection module is used for selecting the phase corresponding to the control bit as the output of the prescaler.
5. The fractional prescaler for a phase locked loop comprising a multiphase oscillator of claim 1, wherein the multiphase oscillator generates 20 phases by 10 differential inverters, and wherein the differential input and differential output of each differential inverter are 180 ° out of phase.
6. The fractional prescaler for a phase locked loop comprising a multiphase oscillator of claim 5, wherein the delay of the differential inverters themselves is equal to a phase of 18 °, and in the phase locked loop, the delay of all the differential inverters in the multiphase oscillator is controlled by voltage or current.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117595865A (en) * | 2023-12-12 | 2024-02-23 | 深圳新港海岸科技有限公司 | Circuit for reducing clock signal jitter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684444A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Frequency synthesizer supporting ultra-low input clock frequency |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
| CN112039521A (en) * | 2020-08-27 | 2020-12-04 | 珠海市一微半导体有限公司 | Four-mode frequency divider for fractional frequency division, fractional phase-locked loop and chip |
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- 2021-09-17 CN CN202111090234.6A patent/CN113872596A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684444A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Frequency synthesizer supporting ultra-low input clock frequency |
| CN103684445A (en) * | 2012-09-11 | 2014-03-26 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phase locked loop |
| CN106209093A (en) * | 2016-03-02 | 2016-12-07 | 北京大学 | A kind of digital fractional frequency-division phase-locked loop structure |
| CN112039521A (en) * | 2020-08-27 | 2020-12-04 | 珠海市一微半导体有限公司 | Four-mode frequency divider for fractional frequency division, fractional phase-locked loop and chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117595865A (en) * | 2023-12-12 | 2024-02-23 | 深圳新港海岸科技有限公司 | Circuit for reducing clock signal jitter |
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