CN115378425A - Half-integer step divider and divider including the same - Google Patents
Half-integer step divider and divider including the same Download PDFInfo
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- CN115378425A CN115378425A CN202211140273.7A CN202211140273A CN115378425A CN 115378425 A CN115378425 A CN 115378425A CN 202211140273 A CN202211140273 A CN 202211140273A CN 115378425 A CN115378425 A CN 115378425A
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- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
Abstract
The invention relates to a half-integer step size frequency divider and a frequency divider comprising the same. A half integer step divider in accordance with an aspect of the invention comprises: a logic processing unit configured to operate in response to rising and falling edges of a clock signal to generate an output signal, wherein a minimum step size of the output signal is half a period of the clock signal and an output level of the output signal is generated with a predetermined logic; and a data delay unit configured to receive the output signal, and store the output signal triggered by a rising edge of the clock signal and feed back the output signal to the logic processing unit triggered by a falling edge of the clock signal.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a half-integer step size frequency divider and a frequency divider including the half-integer step size frequency divider.
Background
Frequency dividers are important components, such as clock generators, frequency synthesizers, etc., that are essential to processing radio frequency clock signals in many wireless radio frequency communication chips. The frequency divider may be divided into an integer divider and a fractional divider according to the division type.
With the development of wireless communication systems, higher requirements are placed on the frequency accuracy and the frequency switching time of the frequency synthesizer. In order to achieve smaller settling times, phase locked loops are required to have wide loop bandwidths. For an integer divider, since the frequency resolution can only be an integer multiple of the reference signal frequency, a smaller input reference signal frequency is generally selected to achieve the required frequency progression, and the loop bandwidth needs to be less than one tenth of the reference frequency for loop stability. However, a smaller loop bandwidth for the integer divider will result in an increased frequency switching time. In addition, a smaller reference signal frequency also results in a larger frequency division ratio, thereby amplifying noise at the input of the phase frequency detector.
For the fractional frequency divider, because the output frequency can be a decimal multiple of the reference frequency, a higher reference frequency and a larger loop bandwidth can be adopted, so that the frequency switching time is reduced, and meanwhile, the requirements on phase noise, frequency precision, locking speed and the like are considered.
It is therefore desirable to provide an improved fractional divider.
Disclosure of Invention
To solve or at least alleviate one or more of the above problems, the following technical solutions are provided.
According to a first aspect of the present invention, there is provided a half integer step size divider, comprising: a logic processing unit configured to operate in response to rising and falling edges of a clock signal to generate an output signal, wherein a minimum step size of the output signal is half of a period of the clock signal and an output level of the output signal is generated with predetermined logic; and a data delay unit configured to receive the output signal, and store the output signal triggered by a rising edge of the clock signal and feed back the output signal to the logic processing unit triggered by a falling edge of the clock signal.
According to an embodiment of the present invention, the half integer step divider, wherein the predetermined logic comprises: in a first half cycle of the clock signal, an output level of the output signal is high; in a second half cycle of the clock signal, the output level of the output signal is low; and in a third half cycle of the clock signal, the output level of the output signal is low.
The half integer step divider according to an embodiment of the present invention or any of the above embodiments, wherein the logic processing unit includes: a first data selector including first and third transmission gates connected in series to a first branch and second and fourth transmission gates connected in series to a second branch connected in parallel to the first branch; and a nor gate having an input terminal connected to the output terminal of the first data selector and the output terminal of the data delay unit, and an output terminal connected to the input terminal of the first data selector.
The half-integer step divider according to an embodiment of the invention or any of the above embodiments, wherein the clock signals include a first clock signal and a second clock signal that is inverted from the first clock signal, the first data selector is configured to: turning on the second and third transmission gates and turning off the first and fourth transmission gates triggered by rising edges of the first and second clock signals, so that the second transmission gate buffers a signal output from the nor gate and the third transmission gate outputs the buffered signal output from the nor gate as an output signal; and turning on the first transmission gate and the fourth transmission gate and turning off the second transmission gate and the third transmission gate triggered by a rising edge of the second clock signal and a falling edge of the first clock signal, so that the first transmission gate buffers a signal output by the nor gate and the fourth transmission gate outputs the buffered signal output by the nor gate as an output signal.
The half integer step divider according to an embodiment of the present invention or any of the above embodiments, wherein the data delay unit includes: a second data selector including first and third transmission gates connected in series to a first branch and second and fourth transmission gates connected in series to a second branch connected in parallel to the first branch; a first nand gate, the input end of which is connected to the output end of the logic processing unit and the mode control signal, and the output end of which is connected to the input end of the second data selector; and the input end of the second NAND gate is connected to the output end of the second data selector and the enable signal, and the output end of the second NAND gate is connected to the logic processing unit.
The half-integer step divider according to an embodiment of the invention or any of the above embodiments, wherein the clock signal comprises a first clock signal and a second clock signal that is inverted with respect to the first clock signal, the second data selector is configured to: triggered by rising edges of the first clock signal and falling edges of the second clock signal, turning on the second transmission gate and the third transmission gate and turning off the first transmission gate and the fourth transmission gate, so that the second transmission gate buffers a signal output by the first nand gate and the third transmission gate inputs the buffered signal output by the first nand gate to the second nand gate; and the rising edge of the second clock signal and the falling edge of the first clock signal trigger to turn on the first transmission gate and the fourth transmission gate and turn off the second transmission gate and the third transmission gate, so that the first transmission gate buffers the signal output by the first nand gate and the fourth transmission gate inputs the buffered signal output by the first nand gate to the second nand gate.
The half-integer-step divider according to an embodiment of the invention or any of the embodiments above, wherein the mode control signal is configured to: when the mode control signal is at a low level, controlling the data delay unit to be turned on so that the half-integer step size frequency divider operates as a DIV1.5 frequency divider; and when the mode control signal is at a high level, controlling the data delay unit to be turned off so that the half integer step size divider operates as a DIV1 divider.
The half-integer step divider according to an embodiment of the invention or any of the above embodiments, wherein the enable signal is configured to: when the enable signal is at a high level, the data delay unit is turned on so that the half integer step size frequency divider operates as a DIV1.5 frequency divider; and when the enable signal is at a low level, the data delay unit is turned off such that the half integer step size divider operates as a DIV1 divider.
The half integer step divider according to an embodiment of the present invention or any of the above embodiments, wherein the logic processing unit includes: a DIV2 divider configured to divide the clock signal by two to generate a divided signal having a frequency of 1/2 of a frequency of the clock signal; and a third data selector including a first path having a first nand gate and a first transmission gate, and a second path having a second nand gate and a second transmission gate, wherein inputs of the first nand gate and the second nand gate are connected to the frequency-divided signal generated by the DIV2 frequency divider, an output of the first nand gate is connected to the first transmission gate, and an output of the second nand gate is connected to the second transmission gate.
The half-integer step divider according to an embodiment of the invention or any of the above embodiments, wherein the clock signal includes a first clock signal and a second clock signal that is inverted with respect to the first clock signal, the DIV2 divider is further configured to divide the first clock signal and the second clock signal by two to generate a first divided signal, a second divided signal, a third divided signal, and a fourth divided signal, respectively, in the following manner: inverting the first and second divided signals; inverting the third divided signal and the fourth divided signal; causing the phases of the first and fourth divided signals to differ by a half cycle of the clock signal; and phase-shifting the second frequency-divided signal and the third frequency-divided signal by half a cycle of the clock signal.
The half-integer step size divider according to an embodiment of the invention or any one of the above embodiments, wherein inputs of the first nand gate are connected to the first frequency-divided signal and the fourth frequency-divided signal, and inputs of the second nand gate are connected to the second frequency-divided signal and the third frequency-divided signal.
The half-integer step divider according to an embodiment of the invention or any of the above embodiments, wherein the third data selector is configured to: turning on the second path and turning off the first path triggered by rising edges of the first clock signal and falling edges of the second clock signal such that an output signal is generated by the second NAND gate based on the second divided signal and the third divided signal; and turning on the first path and turning off the second path triggered by a rising edge of the second clock signal and a falling edge of the first clock signal, such that an output signal is generated by the first nand gate based on the first frequency-divided signal and the fourth frequency-divided signal.
According to a second aspect of the invention there is provided a frequency divider comprising a half integer step divider according to the first aspect of the invention.
The frequency divider according to an embodiment of the present invention, wherein the half-integer step size frequency divider is cascaded as a first stage with the one or more integer frequency dividers.
The half-integer step frequency divider according to one or more embodiments of the invention has the advantages of simple structure, easy realization, low cost, low transmission delay and low power consumption, and can be applied to various application scenes with high speed and low power consumption.
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The above and/or other aspects and advantages of the present invention will become more apparent and more readily appreciated from the following description of the various aspects of the invention taken in conjunction with the accompanying drawings, in which like or similar elements are represented by like reference numerals. In the drawings:
FIG. 1 shows a half integer step divider in accordance with one or more embodiments of the invention.
Fig. 2 shows a transmission gate according to an embodiment of the invention.
Fig. 3 illustrates a half integer step divider in accordance with one or more embodiments of the present invention.
Fig. 4 illustrates a half integer step divider in accordance with one or more embodiments of the present invention.
Fig. 5 shows a timing diagram of signals for a half integer step divider in accordance with one or more embodiments of the invention.
FIG. 6 shows a timing diagram of signals for a half integer step divider in accordance with one or more embodiments of the invention.
Fig. 7 shows a frequency divider in accordance with one or more embodiments of the invention.
Detailed Description
The following description of the specific embodiments is merely exemplary in nature and is in no way intended to limit the disclosed technology or the application and uses of the disclosed technology. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
In the following detailed description of embodiments, numerous specific details are set forth in order to provide a more thorough understanding of the disclosed technology. It will be apparent, however, to one of ordinary skill in the art that the disclosed techniques may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.
Words such as "comprise" and "comprise" mean that in addition to having elements and steps which are directly and explicitly stated in the description, the present solution does not exclude the presence of other elements and steps which are not directly or explicitly stated. Terms such as "first" and "second" do not denote an order of the elements in time, space, size, etc., but rather are used to distinguish one element from another.
Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 shows a half-integer step divider in accordance with one or more embodiments of the invention.
As shown in fig. 1, half integer step divider 100 includes a logic processing unit 110 and a data delay unit 120. The logic processing unit 110 may be configured to operate in response to rising and falling edges of a clock signal to generate an output signal, wherein a minimum step size of the output signal is half a period of the clock signal and an output level of the output signal is generated at a predetermined logic. The data delay unit 120 may be configured to receive the output signal from the logic processing unit 110, and store the output signal triggered by a rising edge of the clock signal and feed back the output signal to the logic processing unit 110 triggered by a falling edge of the clock signal.
Optionally, the predetermined logic may include: in a first half cycle of the clock signal, the output level of the output signal is high; in the second half period of the clock signal, the output level of the output signal is low; and in a third half cycle of the clock signal, the output level of the output signal is low. As an example, when the clock signal is a square wave signal with a duty ratio of 1/2 and a period of T, the output signal generated by the logic processing unit 110 with a predetermined logic is a square wave signal with a duty ratio of 1/3 and a period of 1.5T, that is, a divided-by-1.5 frequency signal.
Alternatively, the logic processing unit 110 and the data delay unit 120 may be implemented by means of a combination of a plurality of transmission gates and logic gates. The structure and function of a single transmission gate is described below with the aid of fig. 2.
Fig. 2 shows a transmission gate according to an embodiment of the invention. As shown in FIG. 2, CKP and CKN represent input clock signals, respectively, where CKN = ~ CKP, i.e., CKP and CKN are the same in amplitude and opposite in phase, i.e., 180 degrees out of phase. D represents the input signal and OUT represents the output signal. OUT = ~ D when CKN =1,CKP = 0; and when CKN =0,ckp =1, OUT is in a high-impedance state, i.e., an open state. It is understood that when CKN =1, ckp =0, the transmission gate operates as an inverter; and when CKN =0, ckp =1, the transmission gate is in an off state. Illustratively, CKP and CKN may be square wave signals of the same amplitude and opposite phase
Fig. 3 illustrates a half integer step divider in accordance with one or more embodiments of the present invention.
As shown in fig. 3, half integer step divider 300 includes a logic processing unit 310 and a data delay unit 320.
The logic processing unit 310 may include a first data selector 3101 and a NOR gate 3102, wherein the first data selector 3101 includes a first transmission gate D1 and a third transmission gate D3 connected in series in a first branch and a second transmission gate D2 and a fourth transmission gate D4 connected in series in a second branch connected in parallel with the first branch, an input terminal of the NOR gate 3102 is connected to an output terminal OUT of the first data selector 3101 and an output terminal MOD _ F of the data delay unit 320, and an output terminal NOR of the NOR gate 3102 is connected to an input terminal of the first data selector 3101.
As shown in FIG. 3, CIP and CIN represent the input clock signals input to the respective transmission gates D1, D2, D3 and D4, respectively, where CIP = ~ CIN, i.e., CIP and CIN are the same in amplitude and opposite in phase, i.e., 180 degrees out of phase. VDDR and AVSS denote power and ground, respectively. In the following description, CIP is taken as the first clock signal and CIN is taken as the second clock signal.
As further shown in fig. 3, first data selector 3101 may be configured to: the second and third transmission gates D2 and D3 are turned on and the first and fourth transmission gates D1 and D4 are turned off triggered by the rising edge of the first clock signal CIP and the falling edge of the second clock signal CIN, so that the second transmission gate D2 buffers the signal NOR output from the NOR gate 3102 and the third transmission gate D3 outputs the buffered signal Q1 output from the NOR gate 3102 as the output signal OUT; and turning on the first and fourth transmission gates D1 and D4 and turning off the second and third transmission gates D2 and D3 triggered by a rising edge of the second clock signal CIN and a falling edge of the first clock signal CIP, so that the first transmission gate D1 buffers the signal NOR output from the NOR gate 3102 and the fourth transmission gate D4 outputs the buffered signal Q2 output from the NOR gate 3102 as the output signal OUT. It is understood that the first data selector 3101 may divide the signal NOR output from the NOR gate 3102 into two parts, respectively output as the output signal OUT through the first and third transmission gates D1 and D3 connected in series in a first branch that collects data at a falling edge of the first clock signal CIP and transmits data at a rising edge of the first clock signal CIP, and the second and fourth transmission gates D2 and D4 connected in series in a second branch connected in parallel with the first branch that collects data at a rising edge of the first clock signal CIP and transmits data at a falling edge of the first clock signal CIP. Thus, the first data selector 3101 can reduce the minimum step size of the output signal OUT to 1/2 of the first clock signal CIP and/or the second clock signal CIN.
The data delay unit 320 may include a second data selector 3201, a first nand gate 3202, and a second nand gate 3203, wherein the second data selector 3201 includes a first transmission gate D1 and a third transmission gate D3 connected IN series IN the first branch, and a second transmission gate D2 and a fourth transmission gate D4 connected IN series IN the second branch connected IN parallel with the first branch, an input of the first nand gate 3202 is connected to the output OUT of the logic processing unit 310 and the mode control signal MOQB, an output MOQ _ IN of the first nand gate 3202 is connected to an input of the second data selector 3201, an input of the second nand gate 3203 is connected to the output MOQ _ M of the second data selector 3201 and the enable signal CL, and an output MOD _ F of the second nand gate 3203 is connected to the logic processing unit 310.
As further shown in fig. 3, the second data selector 3201 may be configured to: the second and third transmission gates D2 and D3 are turned on and the first and fourth transmission gates D1 and D4 are turned off triggered by a rising edge of the first clock signal CIP and a falling edge of the second clock signal CIN, so that the second transmission gate D2 buffers the signal MOQ _ IN output from the first nand gate 3202 and the third transmission gate D3 inputs the buffered signal MOQ1 output from the first nand gate to the second nand gate 3203; and turning on the first and fourth transmission gates D1 and D4 and turning off the second and third transmission gates D2 and D3 triggered by the rising edge of the second clock signal CIN and the falling edge of the first clock signal CIP, so that the first transmission gate D1 buffers the signal MOQ _ IN output from the first nand gate 3202 and the fourth transmission gate D4 inputs the buffered signal MOQ2 output from the first nand gate 3202 to the second nand gate 3203.
As input signals to the first nand gate 3202, the mode control signal MOQB may be configured to: when the mode control signal MOQB is at a low level, the data delay unit 320 is controlled to be turned on so that the half integer step size frequency divider 300 operates as a DIV1.5 frequency divider; and controls the data delay unit 320 to be turned off such that the half integer step size divider 300 operates as the DIV1 divider when the mode control signal MOQB is at a high level. It is to be understood that when the mode control signal MOQB is at a high level, the signal input to the first nand gate 3202 through the not gate is at a low level, so that the data delay unit 320 is in an off state, thereby causing the first data selector 3101 in the half integer step divider 300 to be in an operating state, and thus the half integer step divider 300 operates as a DIV1 divider.
As input signals to the second nand gate 3203, the enable signal CL may be configured to: when the enable signal CL is at a high level, the data delay unit 320 is turned on so that the half-integer step size divider 300 operates as a DIV1.5 divider; and when the enable signal CL is at a low level, the data delay unit 320 is turned off so that the half integer step size divider 300 operates as a DIV1 divider. It will be appreciated that when the enable signal CL is at a low level, the data delay unit 320 is in an off state, such that the first data selector 3101 in the half integer step divider 300 is in an active state, and thus the half integer step divider 300 operates as a DIV1 divider.
As shown in fig. 3, the logic relationship between the output signal (OUT) and the input signals (NOR, MOD _ F) of the logic processing unit 310 is a NOR gate relationship, and the truth table thereof is shown in table 1 below. In table 1, 1UI denotes a first period of the first clock signal CIP and/or the second clock signal CIN, 2UI denotes a second period of the first clock signal CIP and/or the second clock signal CIN, 3UI denotes a third period of the first clock signal CIP and/or the second clock signal CIN, and so on. Rise represents the rising edge of the clock cycle and Fall represents the falling edge of the clock cycle.
TABLE 1 logical relationship between output signals (OUT) and input signals (NOR, MOD _ F)
Table 1:
fig. 4 illustrates a half integer step divider in accordance with one or more embodiments of the present invention.
As shown in fig. 4, half integer step divider 400 includes a logic processing unit 410 and a data delay unit 420.
The logic processing unit 410 may include a DIV2 divider 4101 and a third data selector 4102. The DIV2 divider 4101 may be configured to divide by two the clock signals (clock signals CKN and CKP shown in fig. 4) to generate divided signals Q1, Q1B, Q2, and Q2B having a frequency of 1/2 of the frequency of the clock signals. The third data selector 4102 may include a first path having a first nand gate 4102A and a first transmission gate 4102B, and a second path having a second nand gate 4102D and a second transmission gate 4102C, wherein inputs of the first and second nand gates 4102A and 4102D are connected to the frequency-divided signals Q1, Q2B and Q1B, Q2 generated by the DIV2 frequency divider 4101, an output of the first nand gate 4102A is connected to the first transmission gate 4102B, and an output of the second nand gate 4102D is connected to the second transmission gate 4102C. It should be noted that the first transmission gate 4102B and the second transmission gate 4102C of the third data selector 4102 can be implemented by a single transmission gate as described with reference to fig. 2.
As shown in fig. 4, the DIV2 divider 4101 may be further configured to divide by two the first clock signal CKN and the second clock signal CKP to generate a first divided signal Q1, a second divided signal Q1B, a third divided signal Q2, and a fourth divided signal Q2B, respectively, in the following manner: inverting the first frequency-divided signal Q1 and the second frequency-divided signal Q1B; inverting the third frequency-divided signal Q2 and the fourth frequency-divided signal Q2B; phase of the first and fourth frequency-divided signals Q1 and Q2B is made different by a half period of the clock signal (i.e., the first clock signal CKN and/or the second clock signal CKP); and the phases of the second and third frequency-divided signals Q1B and Q2 are made different by a half period of the clock signal (i.e., the first clock signal CKN and/or the second clock signal CKP). The input terminals of the first nand gate 4102A are connected to the first frequency-divided signal Q1 and the fourth frequency-divided signal Q2B, and the input terminals of the second nand gate 4102D are connected to the second frequency-divided signal Q1B and the third frequency-divided signal Q2. The first clock signal CKN and the second clock signal CKP respectively represent the input clock signals of the DIV2 divider 4101, wherein CKN = ~ CKP, i.e. CKP and CKN have the same amplitude and opposite phases, i.e. 180 degrees apart. Illustratively, CKP and CKN may be square wave signals of the same amplitude and opposite phase.
The third data selector 4102 may be configured to: the second path is turned on and the first path is turned off triggered by a rising edge of the first clock signal CKP and a falling edge of the second clock signal CKN, so that the output signal CKO is generated by the second nand gate 4102D based on the second frequency-divided signal Q1B and the third frequency-divided signal Q2; and turning on the first path and turning off the second path triggered by a rising edge of the second clock signal CKN and a falling edge of the first clock signal CKP, such that the output signal CKO is generated by the first nand gate 4102A based on the first and fourth frequency-divided signals Q1 and Q2B. It is understood that the third data selector 4102 may be implemented as an inverter having a switching function, and the second path having the second nand gate 4102D and the second transmission gate 4102C is turned on by being triggered by the rising edge of the first clock signal CKP and the falling edge of the second clock signal CKN, so that the second frequency-divided signal Q1B and the third frequency-divided signal Q2 generate the output signal CKO via the second nand gate 4102D; the first path having the first nand gate 4102A and the first transmission gate 4102B is turned on triggered by the rising edge of the second clock signal CKN and the falling edge of the first clock signal CKP, so that the first frequency-divided signal Q1 and the fourth frequency-divided signal Q2B generate the output signal CKO via the first nand gate 4102A.
As shown in fig. 4, in the data delay unit 420, CIP and CIN represent input clock signals input to the respective transmission gates D1, D2, D3 and D4, CIP = -CIN, namely the CIP and CIN are identical in amplitude and opposite in phase, namely the phase difference is 180 degrees. VDDR and AVSS denote power and ground, respectively. It will be appreciated that the data delay unit 420 has a similar function and structure to the data delay unit 320 described in fig. 3. As further shown in fig. 4, the output signal CKO of the third data selector 4102 is used as an input to the data delay unit 420, and the output signals of the data delay unit 420 are clock signals CKN and CKP, which can be used as input signals to the DIV2 divider 4101.
The data delay unit 420 may include a fourth data selector 4201, a third nand gate 4202 and a fourth nand gate 4203, wherein the fourth data selector 4201 includes a first transmission gate D1 and a third transmission gate D3 connected IN series to the first branch and a second transmission gate D2 and a fourth transmission gate D4 connected IN series to the second branch connected IN parallel to the first branch, inputs of the third nand gate 4202 are connected to the output CKO of the logic processing unit 410 and the mode control signal MOQB, an output MOQ _ IN of the third nand gate 4202 is connected to an input of the fourth data selector 4201, an input of the fourth nand gate 4203 is connected to an output of the fourth data selector 4201 and the enable signal CL, and an output of the fourth nand gate 4203 is connected to the DIV2 frequency divider 4101 as an input signal of the DIV2 frequency divider 4101.
As input signals to the third nand gate 4202, the mode control signal MOQB may be configured to: when the mode control signal MOQB is at a low level, the data delay unit 420 is controlled to be turned on so that the half integer step size frequency divider 400 operates as a DIV1.5 frequency divider; and when the mode control signal MOQB is at a high level, controls the data delay unit 420 to be turned off such that the half integer step size divider 400 operates as a DIV1 divider.
As input signals to the fourth nand gate 4203, the enable signal CL may be configured to: when the enable signal CL is at a high level, the data delay unit 420 is turned on so that the half integer step size divider 400 operates as a DIV1.5 divider; and when the enable signal CL is at a low level, the data delay unit 420 is turned off so that the half integer step size divider 400 operates as a DIV1 divider.
The half-integer step frequency divider according to one or more embodiments of the invention has the advantages of simple structure, easy realization, low cost, low transmission delay and low power consumption, and can be applied to various application scenes with high speed and low power consumption.
Fig. 5 shows a timing diagram of signals for a half integer step divider in accordance with one or more embodiments of the invention.
FIG. 5 shows the results of a logic simulation of half integer step divider 300 as shown in FIG. 3 in accordance with one or more embodiments of the present invention. In fig. 5, CIP and CIN, i.e., CIP and CIN having the same amplitude and opposite phases, i.e., 180 degrees different phases, respectively, represent input clock signals input to the respective transmission gates D1, D2, D3, and D4 in fig. 3. OUT1 represents the output signal generated by the half-integer step divider 300 operating as a DIV1.5 divider when the mode control signal MOQB is at a low level, and OUT2 represents the output signal generated by the half-integer step divider 300 operating as a DIV1 divider when the mode control signal MOQB is at a high level.
FIG. 6 shows a timing diagram of signals for a half integer step divider in accordance with one or more embodiments of the invention.
FIG. 6 shows the results of a logic simulation of half integer step divider 400 as shown in FIG. 4 in accordance with one or more embodiments of the present invention. In fig. 6, CIP denotes input clock signals input to the respective transmission gates D1, D2, D3, and D4 of the data delay unit 420 in fig. 4, Q1B, Q2, and Q2B denote divided signals generated by the DIV2 divider 4101 in fig. 4 dividing the clock signals (clock signals CKN and CKP shown in fig. 4) by two to generate a frequency 1/2 of the frequency of the clock signals, respectively, and CKO denotes an output signal generated by the half-integer-step divider 400 operating as the DIV1.5 divider when the mode control signal MOQB is at a low level. As shown in fig. 6, the first frequency-divided signal Q1 and the second frequency-divided signal Q1B are inverted, the third frequency-divided signal Q2 and the fourth frequency-divided signal Q2B are inverted, the phases of the first frequency-divided signal Q1 and the fourth frequency-divided signal Q2B differ by a half cycle of the clock signal, and the phases of the second frequency-divided signal Q1B and the third frequency-divided signal Q2 differ by a half cycle of the clock signal.
Additionally, as described above, the present invention may also be embodied as a frequency divider comprising a half integer step divider and one or more integer dividers in accordance with an aspect of the present invention.
Fig. 7 shows a frequency divider in accordance with one or more embodiments of the invention.
As shown in fig. 7, the frequency divider 700 includes a half integer step divider 710 and an integer divider 720 in accordance with an aspect of the present invention. It is noted that half integer step divider 710 may be implemented by half integer step divider 300 and half integer step divider 400 described in conjunction with fig. 3 and 4. Although only one integer divider 720 is shown in fig. 7, the divider 700 may include two or more integer dividers, where the half-integer step divider 710 may be cascaded as a first stage with one or more integer dividers. By cascading the half-integer step size frequency divider 710 as a first stage with one or more integer frequency dividers, frequency dividers of various integer or half-integer step sizes, such as DIV1, DIV1.5, DIV2, DIV2.5, DIV3, DIV3.5, etc., can be obtained. Therefore, the application scenes of traditional integer frequency division and decimal frequency division can be filled, the frequency range of the input signal is wider, the requirement of low power consumption can be met, and the method can be applied to various application scenes of high speed and low power consumption.
The embodiments and examples set forth herein are presented to best explain embodiments in accordance with the invention and its particular application and to thereby enable those skilled in the art to make and utilize the invention. However, those skilled in the art will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. The description as set forth is not intended to cover all aspects of the invention or to limit the invention to the precise form disclosed.
Claims (13)
1. A half integer step size divider, comprising:
a logic processing unit configured to operate in response to rising and falling edges of a clock signal to generate an output signal, wherein a minimum step size of the output signal is half a period of the clock signal and an output level of the output signal is generated with a predetermined logic; and
a data delay unit configured to receive the output signal and to store the output signal triggered by a rising edge of the clock signal and to feed back the output signal to the logic processing unit triggered by a falling edge of the clock signal,
wherein the logical processing unit comprises:
a first data selector including first and third transmission gates connected in series to a first branch and second and fourth transmission gates connected in series to a second branch connected in parallel to the first branch; and
a nor gate having an input terminal connected to the output terminal of the first data selector and the output terminal of the data delay unit, and an output terminal connected to the input terminal of the first data selector.
2. The half integer step divider of claim 1, wherein the predetermined logic comprises:
in a first half cycle of the clock signal, an output level of the output signal is high;
in a second half cycle of the clock signal, the output level of the output signal is low; and
in a third half cycle of the clock signal, the output level of the output signal is low.
3. The half integer step divider of claim 1, wherein the clock signal comprises a first clock signal and a second clock signal that is inverted from the first clock signal, the first data selector configured to:
turning on the second and third transmission gates and turning off the first and fourth transmission gates triggered by rising edges of the first and second clock signals, so that the second transmission gate buffers a signal output from the nor gate and the third transmission gate outputs the buffered signal output from the nor gate as an output signal; and
the first and fourth transmission gates are turned on and turned off triggered by rising edges of the second clock signal and falling edges of the first clock signal, so that the first transmission gate buffers a signal output from the nor gate and the fourth transmission gate outputs the buffered signal output from the nor gate as an output signal.
4. The half integer step divider of claim 1, wherein the data delay unit comprises:
a second data selector including first and third transmission gates connected in series to a first branch and second and fourth transmission gates connected in series to a second branch connected in parallel to the first branch;
a first nand gate, the input end of which is connected to the output end of the logic processing unit and the mode control signal, and the output end of which is connected to the input end of the second data selector; and
and the input end of the second NAND gate is connected to the output end of the second data selector and the enable signal, and the output end of the second NAND gate is connected to the logic processing unit.
5. The half integer step divider of claim 4, wherein the clock signal comprises a first clock signal and a second clock signal that is inverted from the first clock signal, the second data selector configured to:
triggered by rising edges of the first clock signal and falling edges of the second clock signal, turning on the second transmission gate and the third transmission gate and turning off the first transmission gate and the fourth transmission gate, so that the second transmission gate buffers a signal output by the first nand gate and the third transmission gate inputs the buffered signal output by the first nand gate to the second nand gate; and
the first transmission gate and the fourth transmission gate are turned on and turned off triggered by a rising edge of the second clock signal and a falling edge of the first clock signal, so that the first transmission gate buffers a signal output from the first nand gate and the fourth transmission gate inputs a buffered signal output from the first nand gate to the second nand gate.
6. The half integer step divider of claim 4, wherein the mode control signal is configured to:
when the mode control signal is at a low level, controlling the data delay unit to be turned on so that the half integer step size frequency divider operates as a DIV1.5 frequency divider; and
when the mode control signal is at a high level, the data delay unit is controlled to be turned off so that the half integer step size divider operates as a DIV1 divider.
7. The half integer step divider of claim 4, wherein the enable signal is configured to:
when the enable signal is at a high level, the data delay unit is turned on so that the half-integer step size frequency divider operates as a DIV1.5 frequency divider; and
when the enable signal is at a low level, the data delay unit is turned off such that the half integer step divider operates as a DIV1 divider.
8. The half integer step divider of claim 1, wherein the logic processing unit comprises:
a DIV2 divider configured to divide the clock signal by two to generate a divided signal having a frequency that is 1/2 of a frequency of the clock signal; and
a third data selector comprising a first path having a first NAND gate and a first transmission gate, and a second path having a second NAND gate and a second transmission gate, wherein inputs of the first NAND gate and the second NAND gate are connected to the frequency-divided signal generated by the DIV2 frequency divider, an output of the first NAND gate is connected to the first transmission gate, and an output of the second NAND gate is connected to the second transmission gate.
9. The half integer step divider of claim 8, wherein the clock signal comprises a first clock signal and a second clock signal that is inverted from the first clock signal, the DIV2 divider further configured to divide the first clock signal and the second clock signal by two to generate a first divided signal, a second divided signal, a third divided signal, and a fourth divided signal, respectively, in the following manner:
inverting the first and second divided signals;
inverting the third divided signal and the fourth divided signal;
causing the phases of the first and fourth divided signals to differ by a half cycle of the clock signal; and
such that the second and third divided signals are out of phase by one half cycle of the clock signal.
10. The half integer stride divider of claim 9, wherein inputs of the first nand gate are connected to the first and fourth divided signals, and inputs of the second nand gate are connected to the second and third divided signals.
11. The half integer step divider of claim 9, wherein the third data selector is configured to:
turning on the second path and turning off the first path triggered by rising edges of the first clock signal and falling edges of the second clock signal such that an output signal is generated by the second NAND gate based on the second divided signal and the third divided signal; and
the first path is turned on and the second path is turned off triggered by rising edges of the second clock signal and falling edges of the first clock signal, such that an output signal is generated by the first NAND gate based on the first frequency-divided signal and the fourth frequency-divided signal.
12. A frequency divider, wherein the frequency divider comprises:
the half integer step divider of any one of claims 1-11; and
one or more integer dividers.
13. The frequency divider of claim 12, wherein the half-integer step divider is cascaded as a first stage with the one or more integer dividers.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116405025A (en) * | 2023-03-30 | 2023-07-07 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
| CN116527045A (en) * | 2023-07-03 | 2023-08-01 | 麦斯塔微电子(深圳)有限公司 | Frequency division control circuit and method applied to multi-mode frequency divider |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116405025A (en) * | 2023-03-30 | 2023-07-07 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
| CN116405025B (en) * | 2023-03-30 | 2024-03-29 | 上海物骐微电子有限公司 | Local oscillation signal generating circuit, local oscillation signal generating method and wireless communication system |
| CN116527045A (en) * | 2023-07-03 | 2023-08-01 | 麦斯塔微电子(深圳)有限公司 | Frequency division control circuit and method applied to multi-mode frequency divider |
| CN116527045B (en) * | 2023-07-03 | 2023-10-20 | 麦斯塔微电子(深圳)有限公司 | Frequency division control circuit and method applied to multi-mode frequency divider |
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