CN103647553B - Direct current frequency modulation reference source circuit of broadband ultra low phase noise - Google Patents
Direct current frequency modulation reference source circuit of broadband ultra low phase noise Download PDFInfo
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Abstract
The invention provides a direct current frequency modulation reference source circuit of broadband ultra low phase noise. The direct current frequency modulation reference source circuit comprises a digital-to-analog conversion circuit, a data processing and control circuit, a DDS circuit, a band pass filter, a loop filter and an integration frequency synthesis chip. The digital-to-analog conversion circuit controls minimal modulation signals fm to obtain frequency modulation data after conversion of the digital-to-analogue conversion circuit, the frequency modulation data controls the operation with the frequency control words of the DDS circuit through the data processing and control circuit to control the output of the DDS circuit so that modulated signals with ultra low phase noise and ultra low straying, and the modulated signals, after passing through the band pass filter, are sent to the integration frequency synthesis chip to serve as reference signals of a phase-locked loop. By using such a scheme, by use of an analog-to-digital conversion and digital signal processing technologies and DDS and PLL mixing frequency synthesis technologies, direct current frequency modulation of broadband signals by minimal simulation signals can be realized.
Description
Technical field
The invention belongs to phase noise technical field of measurement and test, more particularly to a kind of broadband ultralow phase noise can be straight
Stream chirp reference source circuit.
Background technology
In phase noise field tests, frequency discrimination/Phase Demodulation is one of main method of measurement phase noise, with measurement spirit
The features such as sensitivity height, measurement range width, separable AM noise and be used widely.But the sensitivity for measuring is subject to reference source
The restriction of phase noise, reference signal itself must select equal frequency, and reference signal phase place to make an uproar according to measured signal
Sound is better than the phase noise of measured source, so reference source signal must be the synthesized frequency signal of broadband ultralow phase noise；
In addition, during frequency discrimination/Phase Demodulation measurement phase noise, measured signal is mixed phase demodulation with reference source signal, and phase discriminator is extracted
The small noise signal for going out is digitally sampled, and the tuning tip for driving reference source, composition closed loop lock are removed Jing after digital filter process
Phase loop, this requires that reference source possesses the function that direct current frequency modulation is carried out by small noise signal.
Frequency synthesis technique experienced three generations, i.e. Direct Digital Frequency Synthesizer Technology (DS, Direct Frequency
Synthesis), phase-locked Frequency Synthesis Technique Controlled (PLL) and direct digital frequency synthesis technology DDS (Direct Digital
Synthesis)。
Direct Digital Frequency Synthesizer Technology is as reference source, through mixing, frequency dividing, frequency multiplication and band logical with a crystal oscillator
Filtering etc. is obtaining more multifrequency frequency content.Direct Digital Frequency Synthesizer Technology has prominent in terms of low phase noise frequency synthesis
The advantage for going out, but it is low using the Technology design reference source resolution, and direct current frequency modulation cannot be realized.
Phase-locked Frequency Synthesis Technique Controlled is, using one or several reference frequency sources, by the mode such as mixing or frequency dividing one to be produced
The combination frequency of series, then with phaselocked loop the frequency locker of voltage controlled oscillator in reference frequency.Have an advantage in that phaselocked loop
Road can well select the signal of required frequency equivalent to a narrow band tracking filter, suppress spurious components, be conducive to
Integrated and miniaturization.In recent years Fractional Frequency-Dividing Technology was widely used on Phase locking frequency synthesis, made direct current frequency modulation in lock phase
It is achieved in frequency synthesis technique.
DDS is a kind of new frequency, phase waveform synthetic technology, and it takes full advantage of the fast of large scale integrated circuit
The features such as speed, low-power consumption, Large Copacity, small volume, compared with traditional frequency synthesizer, with phase noise is low, frequency discrimination
The advantages of rate is high, conversion is rapid, its frequency, phase place change seriality can be used for phase place and frequency modulation(PFM).But DDS output frequencies
With limited, actual maximum operating frequency will obey Nyquist law, only the half of clock frequency, typically take clock frequency
40% or so；The DDS's brought due to the non-ideal characteristic of phase truncation, amplitude quantization error and digital-to-analogue conversion is spuious
It is many.
The appearance of DDS technologies is caused to develop high performance frequency source and is possibly realized, that is, by DDS and synthesis of front two generation skill
Art is used in mixed way so as to comprehensive their advantage, and this frequency synthesizer is referred to as hybrid frequency synthesizer (Hybrid
Frequency Synthesis).The scheme that DDS and PLL are used in mixed way is a lot, the characteristics of different schemes has difference, is adapted to not
Same requirement of engineering.
Fig. 1 show existing solution, and it is using frequency range needed for the synthesis of the phaselocked loop with decimal frequency divider
And frequency resolution, modulated signal being carried out after analog to digital conversion, the fractional frequency division that is added to is come than upper by changing fractional frequency division ratio
Change the frequency of composite signal, realize direct current frequency modulation.The fractional-N PLL circuit includes：Reference clock, phase discriminator, integration
Device, voltage controlled oscillator, prescalar, sigma-delta decimal frequency divider and modulated signal modulate circuit.
The output signal of voltage controlled oscillator, directly exports all the way, another to route prescalar and sigma-delta decimal frequency divider
Frequency dividing is realized, phase discriminator carries out phase demodulation to the reference signal of the signal after frequency dividing and reference clock output, and integrator is to phase discriminator
The phase demodulation error signal of output is integrated filtering, generates voltage controlled oscillator tuning error controling signal, controls voltage controlled oscillator
Output signal and it is locked on reference clock frequency.Sigma-delta decimal frequency divider is FPGA circuitry.Modulated signal is by increasing
Benefit, the control modulated signal gain of biasing control module and biasing, and analog digital conversion is realized through analog-digital converter, export 16 digits
Word signal is to sigma-delta decimal frequency divider.Sigma-delta decimal frequency divider also includes depositor, stores fractional frequency division ratio.Modulated signal Jing
Cross and be loaded on the relevant position of depositor by 16 position datawires after 16 analog-digital converter conversions, so as to change decimal point
The frequency dividing ratio of frequency, because the frequency dividing ratio of decimal frequency divider changes according to the change of modulated signal, the output letter of voltage controlled oscillator
Number also by this rule change, it is achieved thereby that direct current frequency modulation.
Realize that fractional frequency division can be subject to device operating frequencies and the resolution of fractional frequency division to be limited using FPGA circuitry, it is impossible to
Work to higher frequency, can only work under relatively low phase demodulation frequency, and higher phase demodulation frequency is to phase-locked loop frequency synthesizer
Phase noise there is improvement result, therefore mentioned prior art cannot be such that the phase noise of composite signal reaches most preferably.
Frequency synthesis is carried out using single phaselocked loop, in the case where reference frequency is relatively low, if improving the output of composite signal
Frequency must just improve the frequency dividing ratio of loop, and improving frequency dividing ratio can cause the deterioration of phase noise of composite signal and improper
It is used as the reference source of phase noise test.
If further improving the phase noise of composite signal in prior art basis, need nested using multiple phaselocked loops
Structure, can so make frequency synthesis scheme become extremely complex, and increased cost.
Therefore, prior art existing defects, need to improve.
The content of the invention
The technical problem to be solved is for the deficiencies in the prior art, there is provided a kind of broadband ultralow phase noise
Can direct current chirp reference source circuit.
Technical scheme is as follows：
A kind of broadband ultralow phase noise can direct current chirp reference source circuit, wherein, including D/A converting circuit, data
Process and control circuit, DDS circuit, band filter, loop filter and integrated frequency synthesizer HMC830；The digital-to-analogue
Change-over circuit controls small modulated signal fmFrequcny modulation data is obtained after analog to digital conversion circuit conversion, at frequcny modulation data Jing data
Reason and control circuit control carry out computing with the frequency control word of DDS circuit, control the output of DDS circuit, produce ultralow phase place
The ultralow spuious transferred signal of noise, the transferred signal is sent to integrated frequency synthesizer after band filter
HMC830, as the reference signal of phaselocked loop.
Described reference source circuit, wherein, the D/A converting circuit includes gain bias control circuit and A/D conversion electricity
Road；The gain bias control circuit is made up of difference ADC driver AD8138 and resistance, electric capacity, inductance component, small tune
Signal f processedmIt is input to the shape that direct current biasing and amplitude after gain bias control circuit are adjusted to suitable A/D change-over circuits conversion
A/D change-over circuits are input to after state；The A/D change-over circuits are by 1.8V, 12,250Msps analog-digital converter MAX1215EGK
And Resistor-Capacitor Unit is constituted, input signal is carried out output signal DATA1 after digital-to-analogue conversion by A/D change-over circuits.
Described reference source circuit, wherein, the Digital Signal Processing and control circuit, by digital signal processor, when
Clock process circuit and Resistor-Capacitor Unit are constituted, and the digital signal processor is used to carry out digital filter to 12 position digital signal DATA1
Ripple process, to meet the characteristics of signals required by different test conditions, carries out digital filtering output signal DATA2；The clock
Process circuit is clock signal f to being input intoclkEnter line frequency and amplitude conversion, reach the use for meeting digital signal processor
Require.
Described reference source circuit, wherein, the DDS circuit by two spurious reduction passages direct synthesizer
AD9912 is constituted, by 1000MHz ultra-low noise reference signals frefAD9912 is connected to Jing after the single-ended conversion to both-end as being
System clock, frequency control word CtrlDATA1 produces Jing interface circuits and delivers to FPGA by CPU, inside FPGA, frequcny modulation data
DATA2 is added with frequency control word CtrlDATA1 and obtains the output that new frequency control word CtrlDATA2 controls AD9912；Its
In, frequency control word CtrlDATA1 is constant after being set, and frequcny modulation data DATA2 does not stop to be received under synchronised clock effect, and
Computing is done with frequency control word CtrlDATA1, new frequency control word CtrlDATA2, frequency control word is ceaselessly produced
CtrlDATA2 does not stop the output frequency for changing AD9912 under synchronised clock effect, realizes the tune to AD9912 output frequencies
System, output signal f1。
Described reference source circuit, wherein, the phaselocked loop is used to extend to 1.6 to the reference frequency output of DDS circuit
～2.4GHz；The phaselocked loop includes loop filter and integrated frequency synthesizer HMC830, integrated frequency synthesizer
HMC830 has been internally integrated VCO, variable frequency divider, phase discriminator, charge pump；DDS circuit output signal f1Jing bandpass filterings
After device, band filter output f2The reference input of phaselocked loop phase discriminator is connected to, the signal f with variable frequency divider output3Carry out
Phase demodulation, the error signal of charge pump output is connected with loop filter, and loop filter filters the radio-frequency component in error signal,
The output frequency of VCO is adjusted, makes phaselocked loop obtain final output signal f of 1.6～2.4GHzout；The bandwidth of phase lock loop is arranged
For 450-550kHz, band stray that DDS circuit is carried and phase demodulation is spuious is suppressed by loop.
Using such scheme：1st, using analog digital conversion and Digital Signal Processing and DDS and PLL hybrid frequencies synthesis skill
Art, is capable of achieving direct current frequency modulation of the minute analog signal to wide-band microwave signal.2nd, it is higher using advanced DDS integrated chips synthesis
The ultralow phase noise reference signal of frequency, using high phase comparison frequency horizontal lock is entered, and reduces phaselocked loop to reference signal phase place
The deterioration of noise, it is ensured that the ultralow phase noise characteristic of the broadband signal of synthesis.3rd, using the phase-locked loop circuit of superior performance,
It has been internally integrated the circuits such as phase discriminator, charge pump, frequency divider and VCO, and VCO reference frequency outputs are high, without the need for again after lock phase
Frequency can directly obtain higher composite signal frequency.
Description of the drawings
Fig. 1 is the circuit diagram for realizing direct current frequency modulation in prior art by changing frequency dividing ratio.
Fig. 2 be broadband ultralow phase noise of the present invention can direct current chirp reference source circuit figure.
Fig. 3 is DDS circuit figure in the present invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
The present invention's realizes principle as shown in Fig. 2 mainly including that D/A converting circuit, data processing and control, DDS are electric
Road, band filter, loop filter and integrated frequency synthesizer HMC830 totally 6 parts, integrated frequency synthesizer
HMC830 is made up of phase discriminator, charge pump, voltage controlled oscillator and variable frequency divider.
Small modulated signal fmComputing is carried out with the frequency control word of DDS after analog digital conversion, the output of DDS is controlled,
Ultralow phase noise, ultralow spuious transferred signal are produced, transferred signal gives phaselocked loop phase discriminator after band filter,
As the reference signal of phaselocked loop.Broadband signal frequency synthesis is realized by controlling the variable frequency divider of phaselocked loop.
Wherein, the major function of D/A converting circuit is by small modulated signal fmDigital to analog conversion is carried out, 12 are transformed to
Digital signal.Two parts are converted comprising gain, biasing control and A/D in the circuit, gain, biasing are controlled small modulated signal
fmBe adjusted to be adapted to A/D conversion state, to greatest extent improve A/D converter effective utilization, A/D walk around device use low mistake
Very, difference ADC driver AD8138 and 1.8V, 12,250Msps analog-digital converters MAX1215EGK and Resistor-Capacitor Unit are constituted.
The effect of Digital Signal Processing and control circuit is processed and by after process obtaining 12 position digital signals
Data deliver to DDS module.The circuit is made up of digital signal processor, clocked processing circuits and related Resistor-Capacitor Unit.Numeral letter
The effect of number processor is to carry out digital filtering process to 12 position digital signals, to meet the signal required by different test conditions
Characteristic；Clocked processing circuits are that the clock signal to being input into enters line frequency and amplitude conversion, reach and meet digital signal processor
Use requirement.
It is illustrated in figure 3 high-purity DDS module theory diagram.To realize ultralow phase noise, ultralow spuious, high-purity DDS moulds
Block is from the direct synthesizer AD9912 with two spurious reduction passages.1000MHz ultra-low noise reference signals frefJing
AD9912 is connected to after the single-ended conversion to both-end as system clock, frequency control word CtrlDATA1 is by CPU Jing interface circuits
FPGA is delivered to, inside FPGA, frequcny modulation data is added with frequency control word CtrlDATA1 and obtains new frequency control word
CtrlDATA2 controls the output of AD9912.Frequency control word CtrlDATA1 is constant after being set, and frequcny modulation data is in synchronised clock
Ceaselessly received under effect, and computing is done with frequency control word CtrlDATA1, ceaselessly produced new frequency control word
CtrlDATA2, frequency control word CtrlDATA2 do not stop the output frequency for changing AD9912 under synchronised clock effect, realize
Modulation to AD9912 output frequencies.
Phaselocked loop is that the reference frequency output of high-purity DDS module is extended to into 1.6～2.4GHz.Phaselocked loop is filtered including loop
Ripple device and integrated frequency synthesizer HMC830, integrated frequency synthesizer HMC830 be internally integrated VCO, variable frequency divider,
The functional units such as phase discriminator, charge pump.High-purity DDS module output signal is connected to the defeated of phaselocked loop phase discriminator Jing after band filter
Enter end, with the signal of variable frequency divider output phase demodulation is carried out.The error signal of charge pump output is connected with loop filter, loop
Wave filter filters the radio-frequency component in error signal, adjusts the output frequency of VCO, make VCO output frequencies be locked in 1.6～
2.4GHz.Phase-locked loop bandwidth is set to 500kHz or so, band stray that DDS signals are carried and phase demodulation is spuious is pressed down by loop
System.
Embodiment 2
On the basis of above-described embodiment, further, as shown in Fig. 2-Fig. 3, a kind of broadband ultralow phase noise can be straight
Stream chirp reference source circuit, wherein, including D/A converting circuit, data processing and control circuit, DDS circuit, band filter,
Loop filter and integrated frequency synthesizer HMC830；The D/A converting circuit controls small modulated signal fmThrough modulus
Frequcny modulation data, frequcny modulation data Jing data processings and control circuit control and the frequency control of DDS circuit are obtained after change-over circuit conversion
Word processed carries out computing, controls the output of DDS circuit, produces the ultralow spuious transferred signal of ultralow phase noise, described to be adjusted letter
Number integrated frequency synthesizer HMC830 is sent to after band filter, as the reference signal of phaselocked loop.
The D/A converting circuit includes gain, bias control circuit and A/D change-over circuits；The gain, biasing control
Circuit is made up of difference ADC driver AD8138 and resistance, electric capacity, inductance component, small modulated signal fmIt is input to gain
Direct current biasing and amplitude are adjusted to after the state of suitable A/D change-over circuits conversion and are input to A/D conversions after bias control circuit
Circuit；The A/D change-over circuits are made up of 1.8V, 12,250Msps analog-digital converters MAX1215EGK and Resistor-Capacitor Unit, A/D
Input signal is carried out output signal DATA1 after digital-to-analogue conversion by change-over circuit.
The Digital Signal Processing and control circuit, by digital signal processor, clocked processing circuits and Resistor-Capacitor Unit structure
Into the digital signal processor is used to carry out digital filtering process to 12 position digital signal DATA1, to meet different test strip
Characteristics of signals required by part, carries out digital filtering output signal DATA2；The clocked processing circuits are the clock letters to being input into
Number fclkEnter line frequency and amplitude conversion, reach the use requirement for meeting digital signal processor.
The DDS circuit is made up of the direct synthesizer AD9912 of two spurious reduction passages, and 1000MHz is ultralow
Noise reference signal frefAD9912 is connected to Jing after the single-ended conversion to both-end as system clock, frequency control word
CtrlDATA1 produces Jing interface circuits and delivers to FPGA by CPU, inside FPGA, frequcny modulation data DATA2 and frequency control word
CtrlDATA1 is added and obtains the output that new frequency control word CtrlDATA2 controls AD9912；Wherein, frequency control word
CtrlDATA1 is constant after being set, and frequcny modulation data DATA2 does not stop to be received under synchronised clock effect, and and frequency control word
CtrlDATA1 does computing, ceaselessly produces new frequency control word CtrlDATA2, and frequency control word CtrlDATA2 is when synchronous
Do not stop the output frequency for changing AD9912 under clock effect, realize the modulation to AD9912 output frequencies, output signal f1。
The phaselocked loop is used to extend to 1.6～2.4GHz to the reference frequency output of DDS circuit；The phaselocked loop includes
Loop filter and integrated frequency synthesizer HMC830, integrated frequency synthesizer HMC830 be internally integrated VCO, can variation
Frequency device, phase discriminator, charge pump；DDS circuit output signal f1Jing after band filter, wave filter output f2It is connected to phaselocked loop
The reference input of phase discriminator, the signal f with variable frequency divider output3Carry out phase demodulation, the error signal and ring of charge pump output
Path filter is connected, and loop filter filters the radio-frequency component in error signal, adjusts the output frequency of VCO, obtains phaselocked loop
Obtain final output signal f of 1.6～2.4GHzout；The bandwidth of phase lock loop is set to 450-550kHz, the band that DDS circuit is carried
Outward spuious and phase demodulation is spuious is suppressed by loop.
Using such scheme：1st, using analog digital conversion and Digital Signal Processing and DDS and PLL hybrid frequencies synthesis skill
Art, is capable of achieving direct current frequency modulation of the minute analog signal to wide-band microwave signal.2nd, it is higher using advanced DDS integrated chips synthesis
The ultralow phase noise reference signal of frequency, using high phase comparison frequency horizontal lock is entered, and reduces phaselocked loop to reference signal phase place
The deterioration of noise, it is ensured that the ultralow phase noise characteristic of the broadband signal of synthesis.3rd, using the phase-locked loop circuit of superior performance,
It has been internally integrated the circuits such as phase discriminator, charge pump, frequency divider and VCO, and VCO reference frequency outputs are high, without the need for again after lock phase
Frequency can directly obtain higher composite signal frequency.
It should be appreciated that for those of ordinary skills, can according to the above description be improved or be converted,
And all these modifications and variations should all belong to the protection domain of claims of the present invention.
Claims (3)
1. a kind of broadband ultralow phase noise can direct current chirp reference source circuit, it is characterised in that being included in can direct current frequency modulation
D/A converting circuit, data processing and control circuit, the DDS being sequentially connected between the input and outfan of reference source circuit is electric
Road, band filter, loop filter and integrated frequency synthesizer HMC830；The integrated frequency synthesizer HMC830 with
The loop filter forms phaselocked loop；The D/A converting circuit controls small modulated signal fmTurn through D/A converting circuit
Frequcny modulation data is obtained after changing, frequcny modulation data Jing data processings and control circuit control are transported with the frequency control word of DDS circuit
Calculate, control the output of DDS circuit, produce the ultralow spuious transferred signal of ultralow phase noise, the transferred signal is through band logical
Integrated frequency synthesizer HMC830 is sent to after wave filter, as the reference signal of phaselocked loop；The D/A converting circuit bag
Include gain, bias control circuit and A/D change-over circuits；The gain, bias control circuit by difference ADC driver AD8138 and
Resistance, electric capacity, inductance component are constituted, small modulated signal fmIt is input to gain, bias control circuit, direct current biasing and amplitude
It is adjusted to after the state of suitable A/D change-over circuits conversion and is input to A/D change-over circuits；The A/D change-over circuits by 1.8V, 12
Position, 250Msps analog-digital converters MAX1215EGK and Resistor-Capacitor Unit are constituted, and input signal is carried out digital-to-analogue and turned by A/D change-over circuits
Change rear output signal DATA1；
The data processing and control circuit, are made up of digital signal processor, clocked processing circuits and Resistor-Capacitor Unit, the number
Word signal processor is used for carrying out at digital filtering through 12 position digital signal DATA1 produced by D/A converting circuit process
Reason, to meet the characteristics of signals required by different test conditions, carries out digital filtering output signal DATA2；The clock is processed
Circuit is clock signal f to being input intoclkEnter line frequency and amplitude conversion, reach the use requirement for meeting digital signal processor.
2. reference source circuit as claimed in claim 1, it is characterised in that the DDS circuit is by FPGA and Direct frequency synthesizer
Device AD9912 is constituted, by 1000MHz ultra-low noise reference signals frefIt is connected to direct frequency Jing after the single-ended conversion to both-end to close
AD9912 grow up to be a useful person as system clock, frequency control word CtrlDATA1 produces Jing interface circuits and delivers to FPGA by CPU, in FPGA
Inside, frequcny modulation data DATA2 is added with frequency control word CtrlDATA1 and obtains new frequency control word CtrlDATA2 controls directly
Connect the output of frequency synthesizer AD9912；Wherein, frequency control word CtrlDATA1 is constant after being set, and frequcny modulation data DATA2 exists
Do not stop to be received under synchronised clock effect, and computing is done with frequency control word CtrlDATA1, ceaselessly produce new FREQUENCY CONTROL
Word CtrlDATA2, frequency control word CtrlDATA2 do not stop to change direct synthesizer AD9912's under synchronised clock effect
Output frequency, realizes the modulation to direct synthesizer AD9912 output frequencies, output signal f1。
3. reference source circuit as claimed in claim 1, it is characterised in that the phaselocked loop is used for the output frequency to DDS circuit
Rate range expansion is to 1.6～2.4GHz；The phaselocked loop includes loop filter and integrated frequency synthesizer HMC830, integrated
Frequency synthesizer HMC830 be internally integrated VCO, variable frequency divider, phase discriminator, charge pump；The DDS circuit output signal
f1Jing after band filter, band filter output f2The reference input of the phase discriminator of phaselocked loop is connected to, it is defeated with variable frequency divider
The signal f for going out3Phase demodulation is carried out, the error signal of charge pump output is connected with loop filter, and loop filter filters error letter
Radio-frequency component in number, adjusts the output frequency of VCO, makes phaselocked loop obtain final output signal f of 1.6～2.4GHzout；Institute
State bandwidth of phase lock loop and be set to 450-550kHz, band stray that DDS circuit is carried and phase demodulation is spuious is suppressed by loop.
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| CN104124966B (en) * | 2014-07-21 | 2017-07-14 | 中国电子科技集团公司第四十一研究所 | A kind of Direct frequency synthesizer method for producing linear FM signal |
| CN104345764A (en) * | 2014-11-07 | 2015-02-11 | 绵阳市维博电子有限责任公司 | Constant-flow source |
| CN105515575A (en) * | 2015-12-05 | 2016-04-20 | 青岛盛嘉信息科技有限公司 | Sinusoidal signal frequency generator |
| US10367672B2 (en) * | 2016-09-28 | 2019-07-30 | Qualcomm Incorporated | Enhancements to phase-noise compensation reference signal design and scrambling |
| CN108512549A (en) * | 2018-06-07 | 2018-09-07 | 贵州航天天马机电科技有限公司 | A kind of Frequency Hopping Synthesizer |
| CN109462565A (en) * | 2018-12-25 | 2019-03-12 | 成都前锋电子仪器有限责任公司 | A kind of broadband FM signal source |
| CN109936363B (en) * | 2019-03-06 | 2023-08-04 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency division phase-locked loop system and spurious optimization method thereof |
| CN110504962B (en) * | 2019-07-17 | 2023-04-28 | 晶晨半导体(上海)股份有限公司 | Digital compensation analog fractional frequency division phase-locked loop and control method |
| CN112653459A (en) * | 2020-12-28 | 2021-04-13 | 成都美数科技有限公司 | Radio frequency signal source capable of being calibrated in real time |
| CN113271140B (en) * | 2021-05-17 | 2022-06-03 | 东南大学 | Method for realizing precise phase shift by using digital switch mode |
| CN115425967B (en) * | 2022-08-31 | 2023-11-14 | 北京北方华创微电子装备有限公司 | Phase synchronization device and method, radio frequency power supply and semiconductor process equipment |
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