CN103490777B - low spurious frequency synthesizer - Google Patents
low spurious frequency synthesizer Download PDFInfo
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- CN103490777B CN103490777B CN201310460310.7A CN201310460310A CN103490777B CN 103490777 B CN103490777 B CN 103490777B CN 201310460310 A CN201310460310 A CN 201310460310A CN 103490777 B CN103490777 B CN 103490777B
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Abstract
The invention relates to the technical field of digital communication and discloses a low spurious frequency synthesizer. The low spurious frequency synthesizer comprises a reference clock circuit and a phase-locked loop circuit. The reference clock circuit comprises a direct digital synthesizer (DDS), a frequency mixer and a first frequency divider which are sequentially connected in series. The frequency mixer performs frequency mixing on output signals of the DS. The first frequency divider enables the mixed signal frequencies to be reduced through frequency division and outputs the signal frequencies for serving as reference signals to a frequency synthesis circuit. The phase-locked loop circuit utilizes the reference signals sent by the reference clock circuit to control the frequencies and phases of oscillation signals inside a loop and outputs specified broadband signals. Compared with traditional frequency synthesizers and when the output frequencies are identical, spurious suppression indexes of the low spurious frequency synthesizer are obviously improved, and broadband signals with specified frequencies and bandwidths can be conveniently and flexibly achieved.
Description
Technical field
The present invention relates to digital communication technology field, more particularly to a kind of low spurious frequency synthesizer.
Background technology
Modern communication system and radar system, suppress the requirement of index increasingly to improve to Frequency Synthesizer Spuriousness.Frequency
The noise restraint of synthesizer will directly affect the sensitivity of receiver, and especially the near-end of frequency synthesizer is spuious among these,
Impact to receiver is even more huge.
In order to realize the broadband frequency synthesizer of low spurious, while meeting system again to phase noise and frequency step
Requirement, traditional is achieved in that DDS (Direct Digital Synthesizer, Direct Digital Synthesizer)
Output signal as PLL (Phase Locked Loop, phaselocked loop) reference signal, excitation PLL produce needed for frequency, such as
(wherein PLL is made up of phase discriminator, loop filter and voltage controlled oscillator VCO) shown in Fig. 1.The frequency realized by this way is closed
Grow up to be a useful person, the spuious degree of suppression of its output signal near-end depends primarily on the feedback point of the near-end noise restraint and phaselocked loop of DDS
The size of frequency ratio N, is formulated as：SPSYNTH=SPDDS+ 20lgN, wherein SPSYNTHFor the near of frequency synthesizer output signal
End noise restraint, unit are-dBc, SPDDSFor the near-end noise restraint of DDS, unit is similarly-dBc.Can be seen by the formula
Go out, the scheme shown in Fig. 1, its near-end noise restraint is on the basis of DDS near-end noise restraints to deteriorate 20lgN.Defeated
In the case of going out signal frequency determination, low spurious will be obtained by this way and is accomplished by improving phase demodulation frequency FPFDSo as to reduce N or
Reduce DDS near-ends spuious.
But, some obvious shortcomings are equally existed using above-mentioned existing mode：Improving phase demodulation frequency then needs to improve DDS
Output frequency, and for a DDS, its output frequency is higher, near-end is spuious also poorer, therefore this mode is to spuious
Improvement degree be very limited；Equally, the near-end of DDS to be reduced is spuious, for a DDS, is only improved DDS's
System clock frequency, but the raising of DDS system clock frequencys be also it is limited, and the higher DDS chips of system clock into
This is also higher.
The content of the invention
For the drawbacks described above of prior art, the technical problem to be solved is how to reduce to quickness and high efficiency
The near-end of DDS is spuious.
For solving above-mentioned technical problem, the invention provides a kind of low spurious frequency synthesizer, the frequency synthesizer bag
Include：Reference clock circuit and frequency synthesis phase-locked loop circuit；Improve frequency by improving the near-end spurious reduction of DDS output signals
The near-end noise restraint of synthesizer output signal；Wherein,
The reference clock circuit includes DDS, frequency mixer and the first frequency divider being sequentially connected in series；The frequency mixer is by DDS
Output signal be mixed；Signal frequency after the mixing is reduced by first frequency divider through frequency dividing, is exported to institute
Frequency synthesizer circuit is stated as reference signal；
The reference signal control loop internal oscillation signal that the phase-locked loop circuit is sent using reference clock circuit
Frequency and phase place, export the broadband signal specified.
Preferably, crystal oscillator, point frequency source and the second frequency divider are also included in the reference clock circuit；Wherein,
The input in the outfan coupling point frequency source of the crystal oscillator；
The outfan in the point frequency source couples the input of the DDS and second frequency divider simultaneously；
The outfan of second frequency divider couples the local oscillation signal input of the frequency mixer.
Preferably, the phase-locked loop circuit includes phase discriminator, loop filter and voltage controlled oscillator；Wherein,
The input of the phase discriminator is coupled with the outfan of the reference clock circuit, the feedback signal of the phase discriminator
Input is coupled with the outfan of the voltage controlled oscillator；
The input of the loop filter is coupled with the outfan of the phase discriminator, the outfan of the loop filter
Couple the input of the voltage controlled oscillator；
The outfan of voltage controlled oscillator outfan and the phase demodulation simultaneously as the low spurious frequency synthesizer
The feedback signal input terminal of device.
Preferably, frequency divider of the frequency divider for frequency dividing ratio digital controllable.
Preferably, first frequency divider and second frequency divider have different frequency dividing ratios.
Preferably, the frequency dividing ratio of first frequency divider is higher than second frequency divider.
Preferably, more than 20, the frequency dividing ratio of second frequency divider is below 5 for the frequency dividing ratio of first frequency divider.
Preferably, the frequency mixer is also filtered to the output signal of the DDS simultaneously.
Preferably, it is described carry out being mixed down carry out up-conversion.
Preferably, the frequency of the broadband signal is located at L-band between K-band.
Compared with prior art, low spurious frequency synthesizer of the present invention is when output frequency is identical, its spuious suppression
Index processed be improved significantly, it is spuious with the near-end that relatively low cost and complexity significantly improve output signal, realize
Low spurious, the signal output of little stepping.
Description of the drawings
Fig. 1 is the structural representation of prior art frequency synthesizer.
Fig. 2 is the structural representation of the low spurious frequency synthesizer described in one embodiment of the present of invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described.Obviously, described embodiment is to implement the better embodiment of the present invention, and the description is to illustrate the present invention
Rule for the purpose of, be not limited to the scope of the present invention.Protection scope of the present invention should be with claim institute circle
The person of determining is defined, and based on the embodiment in the present invention, those of ordinary skill in the art are not on the premise of creative work is made
The every other embodiment for being obtained, belongs to the scope of protection of the invention.
The broadband frequency synthesizer that the mode of traditional utilization DDS excitation PLL is realized, or by the output for improving DDS
Frequency, or by the system clock frequency for improving DDS, the improvement spuious to near-end of various modes is all very limited, and its effect is simultaneously
It is less desirable.In an embodiment of the present invention, signal spurious reduction characteristic can be improved by studying discovery signal frequency split, profit
This principle is used, DDS output signals is changed to into a higher frequency through frequency conversion, then the signal is divided, so as to enter
One step improves the near-end spurious reduction of DDS output signals.
Referring to Fig. 2, in one embodiment of the invention, C-band, a small step are realized by signal frequency split mode
Enter, the broadband frequency source of low spurious.In the embodiment of fig. 2, low spurious frequency synthesizer includes：Reference clock circuit and lock phase
Loop circuit；Wherein, reference clock circuit includes DDS, frequency mixer and the first frequency divider being sequentially connected in series, will in reference clock circuit
The output signal of DDS upconverts to a higher frequency by mixing, then reduces frequency through frequency dividing again, is made with this
For the reference signal of phase-locked loop circuit；Shake inside the reference signal control loop that phase-locked loop circuit is sent using reference clock circuit
Swing the frequency and phase place of signal, the broadband signal that final output is specified.Preferably, frequency mixer output signal also simultaneously to DDS
It is filtered.
In fig. 2, crystal oscillator, point frequency source and the second frequency divider are also included in reference clock circuit；Wherein, (crystal shakes crystal oscillator
Swing device) for producing stable initial signal, crystal oscillation signal is converted into fixed output frequency and is supplied to DDS (to make by point frequency source
For the reference clock signal of DDS) and the second frequency divider, the second frequency divider will be supplied to mixing after the output frequency frequency dividing in a frequency source
Local oscillation signal of the device as up-conversion.Preferably, frequency divider of second frequency divider for two divided-frequency.Due to the local oscillator of DDS up-conversions
Signal is produced after frequency dividing by the reference clock of DDS so that the equipment volume of the present invention further reduces, while reduce setting
Standby cost.
Additionally, phase-locked loop circuit includes：Phase discriminator, loop filter and voltage controlled oscillator VCO；Wherein, phase discriminator pair
The feedback signal that the reference signal of input and voltage controlled oscillator are sent enters the comparison of line frequency and phase place, exports one and represents both
The signal of difference；Radio-frequency component in the signal that phase discriminator is exported by loop filter is filtered, and reservation direct current component is delivered to voltage-controlled
Agitator；Voltage controlled oscillator exports the periodic signal controlled by input voltage by a frequency, the signal of voltage controlled oscillator output
Also phase discriminator is sent back to simultaneously for feeding back.Preferably, the phase discriminator is digital phase discriminator.
Present invention achieves the low spurious characteristic of output signal, it is critical only that and employ this ginseng for being different from traditional scheme
Examine clock circuit.In traditional scheme, reference clock is directly produced by DDS, and its spurious reduction index is also by DDS without spuious dynamic
State scope (the namely noise restraint of DDS) is directly determined.And the scheme that the present invention is adopted, output of the reference clock by DDS
Signal is produced Jing after up-conversion and frequency dividing, and its spurious reduction index has on the basis of DDS SFDRs greatly
Improve.
In a preferred embodiment of the invention, frequency divider of the frequency divider for being adopted for frequency dividing ratio digital controllable, from
And can more flexibly set the frequency dividing mode of signal, so as to for frequency mixer or PLL circuit provide different local oscillation signals or
Reference signal, so that flexibly easily obtain the different output broadband signal of frequency and/or scope so that the equipment of the present invention can
With suitable for more application occasions.Preferably, the first and second frequency dividers have different frequency dividing ratios；Wherein, the first frequency dividing
Device is used for producing the reference signal of PLL circuit, with higher frequency dividing ratio；Second frequency divider is used for producing the local oscillator letter of frequency mixer
Number, with relatively low frequency dividing ratio.It is highly preferred that the frequency dividing ratio of the first frequency divider is more than 20, the frequency dividing ratio of the second frequency divider is 5
Below.Additionally, the bandwidth of the broadband signal of final output is determined by VCO output signal bandwidth, one can be typically reached even
Two octaves；The frequency of broadband signal is also determined by VCO, by selecting the VCO of different model, it is possible to achieve L-band is to K ripples
The output of section.Typically, from the VCO of Z-COMM companies production, SMV1100C-LF types can export 980MHz-1200MHz's
L-band signal；SMV3400C-LF types can export the S-band signal of 3180-3430；SMV5550B-LF types can be exported
C-band signal of 5000MHz-6000MHz etc..
For example, the first frequency divider is the frequency divider of 20 frequency dividings (frequency is reduced to the 1/20 of primary frequency), and second divides
When device is two-divider, the output that VCO realizes C-band is chosen, obtain width signal of the frequency for 4GHz-8GHz.In the enforcement
In example, as the arrowband SFDR of DDS chips can reach -95dBc (the DDS models that hypothesis is used
AD9914), the near-end spurious reduction of the reference clock signal of frequency synthesizer for therefore obtaining Jing after 20 frequency dividings can reach-
95dBc-20lg20=-121dBc.The reference clock signal directly produced with DDS is compared, its spurious reduction improves 26dB.Again
Through frequency synthesizer circuit, the signal of final output 4GHz-8GHz.Calculate according to highest output frequency 8GHz, output signal
Reachable-the 121dBc+20lg80=-83dBc of near-end spurious reduction.
Technical scheme compares traditional frequency synthesizer when output frequency is identical, and its spurious reduction index is obtained
To being obviously improved, while low spurious, low phase noise are realized, the width of characteristic frequency and bandwidth can be easily and flexibly realized
Band signal, it is spuious with the near-end that relatively low cost and complexity significantly improve output signal, realize low spurious, little stepping
Signal output.
Described above illustrates and describes some preferred embodiments of the present invention, but as previously mentioned, it should be understood that the present invention
Be not limited to form disclosed herein, be not to be taken as the exclusion to other embodiment, and can be used for various other combinations,
Modification and environment, and can be in invention contemplated scope described herein, by above-mentioned teaching or the technology or knowledge of association area
It is modified.And change that those skilled in the art are carried out and change be without departing from the spirit and scope of the present invention, then all should be at this
In the protection domain of bright claims.
Claims (6)
1. a kind of low spurious frequency synthesizer, it is characterised in that the frequency synthesizer includes：Reference clock circuit and frequency are closed
Into phase-locked loop circuit；By improve the near-end spurious reduction of DDS output signals improve frequency synthesizer output signal near-end it is miscellaneous
Scattered degree of suppression；Wherein,
The reference clock circuit includes DDS, frequency mixer and the first frequency divider being sequentially connected in series；The frequency mixer is by the defeated of DDS
Go out signal to be mixed；Signal frequency after mixing is reduced by first frequency divider through frequency dividing, is exported and is closed to the frequency
Into circuit as reference signal；
Also include crystal oscillator, point frequency source and the second frequency divider in the reference clock circuit；The outfan coupling of the crystal oscillator is described
The input in point frequency source；The outfan in the point frequency source couples the input of the DDS and second frequency divider simultaneously；It is described
The outfan of the second frequency divider couples the local oscillation signal input of the frequency mixer；First frequency divider and second frequency dividing
Device has different frequency dividing ratios for the frequency divider of frequency dividing ratio digital controllable；
The phase-locked loop circuit includes phase discriminator, loop filter and voltage controlled oscillator；Wherein,
The input of the phase discriminator is coupled with the outfan of the reference clock circuit, the feedback signal input of the phase discriminator
The outfan with the voltage controlled oscillator is held to couple；
The input of the loop filter is coupled with the outfan of the phase discriminator, the outfan coupling of the loop filter
The input of the voltage controlled oscillator；
The outfan of voltage controlled oscillator outfan and the phase discriminator simultaneously as the low spurious frequency synthesizer
Feedback signal input terminal described in inside the reference signal control loop sent using reference clock circuit of phase-locked loop circuit
The frequency and phase place of oscillator signal, exports the broadband signal specified.
2. low spurious frequency synthesizer as claimed in claim 1, it is characterised in that the frequency dividing ratio of first frequency divider is higher than
Second frequency divider.
3. low spurious frequency synthesizer as claimed in claim 2, it is characterised in that the frequency dividing ratio of first frequency divider is 20
More than, the frequency dividing ratio of second frequency divider is below 5.
4. low spurious frequency synthesizer as claimed in claim 1, it is characterised in that the frequency mixer is also simultaneously to the DDS
Output signal be filtered.
5. low spurious frequency synthesizer as claimed in claim 1, it is characterised in that it is described carry out being mixed down carry out up-conversion.
6. low spurious frequency synthesizer as claimed in claim 1, it is characterised in that the frequency of the broadband signal is located at L ripples
Section is between K-band.
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| CN105372512B (en) * | 2014-08-26 | 2019-06-18 | 苏州普源精电科技有限公司 | Radio-frequency measurement device with phase fixed function |
| CN104579335A (en) * | 2014-09-26 | 2015-04-29 | 中国人民解放军总参谋部第六十三研究所 | Frequency design method for frequency synthesizer |
| CN104320133A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | Electric circuit and method for restraining fractional stray of fractional phase locking loops |
| CN104393871A (en) * | 2014-12-02 | 2015-03-04 | 贵州航天计量测试技术研究所 | Frequency synthesizer for driving phase-locked loop after up-converting DDS |
| CN104467827B (en) * | 2014-12-31 | 2018-09-21 | 陕西烽火电子股份有限公司 | A kind of fractional-N frequency synthesizer spurious reduction method |
| CN106656176A (en) * | 2016-12-30 | 2017-05-10 | 重庆华伟工业（集团）有限责任公司 | Wide-frequency-band agile frequency synthesizer |
| CN106533439B (en) * | 2017-01-09 | 2023-06-06 | 成都西蒙电子技术有限公司 | Low phase noise frequency synthesizer |
| CN109412589B (en) * | 2017-08-16 | 2024-04-05 | 天津乾铁科技有限公司 | Optimizing method and system for integer boundary spurious of fractional frequency synthesizer |
| CN108092663B (en) * | 2017-12-26 | 2022-01-21 | 海能达通信股份有限公司 | Frequency generating device and frequency generating method |
| WO2020041967A1 (en) * | 2018-08-28 | 2020-03-05 | 华为技术有限公司 | Phase locked loop circuit and device using same |
| CN110176928A (en) * | 2019-05-29 | 2019-08-27 | 江苏华讯电子技术有限公司 | A kind of extra small stepping based on DDS and PLL structure, low spurious broadband frequency synthesizer |
| CN111835340B (en) * | 2020-09-21 | 2020-12-08 | 成都雷通科技有限公司 | Double-loop frequency source for driving PLL (phase locked loop) by fine stepping broadband PLL |
| CN112653426A (en) * | 2020-12-21 | 2021-04-13 | 贵州航天计量测试技术研究所 | Broadband extremely-narrow pulse signal generating circuit |
| CN113726334B (en) * | 2021-07-20 | 2024-03-08 | 江苏华讯电子技术有限公司 | S-band low-phase-noise low-stray fine stepping frequency source assembly and use method |
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| US5859570A (en) * | 1994-09-29 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL |
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| CN202978896U (en) * | 2012-11-09 | 2013-06-05 | 北京中科飞鸿科技有限公司 | Combined broadband rapid frequency hopping source |
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