CN104320133A - Electric circuit and method for restraining fractional stray of fractional phase locking loops - Google Patents
Electric circuit and method for restraining fractional stray of fractional phase locking loops Download PDFInfo
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- CN104320133A CN104320133A CN201410561889.0A CN201410561889A CN104320133A CN 104320133 A CN104320133 A CN 104320133A CN 201410561889 A CN201410561889 A CN 201410561889A CN 104320133 A CN104320133 A CN 104320133A
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Abstract
The invention provides an electric circuit for restraining fractional stray of fractional phase locking loops. The electric circuit for restraining the fractional stray of the fractional phase locking loops comprises at least two levels of the fractional phase locking loops, wherein the front level fractional phase locking loop is connected with the back level fractional phase locking loop through a frequency divider, an output signal of the front level fractional phase locking loop is used as a reference input signal of the back level fractional phase locking loop after frequency division is performed on the output signal of the front level fractional phase locking loop by the frequency divider, and the front level fractional phase locking loop and the back level fractional phase locking loop are of the same structure. The method for restraining the fractional stray of the fractional phase locking loops includes the steps that fractional frequency division is performed by the frequency divider on an output signal of a voltage controlled oscillator, phase discrimination operation is performed by a phase discriminator on the input signal after the frequency division and the reference input signal, an output signal of the phase discriminator is sent into a loop filter, and the loop filter generates voltage controlled voltage of the voltage controlled oscillator. The electric circuit and the method for restraining the fractional stray of the fractional phase locking loops can directly change fractional stray frequency, are not influenced by nonlinear circuits of the phase discriminator, the frequency divider and the like in a circuit, and have good stray restraining effects. Additionally, the fractional stray frequency of the fractional phase locking loops is shifted out of the bandwidth of the fractional phase locking loops and filtered out by the loop filter, and therefore the purpose of restraining the fractional stray is achieved.
Description
Technical field
The present invention relates to technical field of measurement and test, particularly a kind of circuit suppressing fractional phase lock loop fractional stray, also relate to a kind of method suppressing fractional phase lock loop fractional stray.
Background technology
The advantages such as fractional phase lock loop is high because of frequency resolution, output frequency range is wide, are widely used in all kinds of frequency synthesizer.Although fractional phase lock loop output signal frequency is the little several times of N.F of reference signal frequency, in fractional phase lock loop, the instantaneous frequency dividing ratio of frequency divider is not decimal, but integer.The frequency dividing ratio of frequency divider is in continuous change, and the average divide just in many cycles is than being decimal.To realize 100.1 frequency dividing ratios, need to have carried out 9 100 frequency divisions, 1 101 frequency division, average divide is than being (100 × 9+101)/10=100.1, therefore under instantaneous state, there is phase error in output signal of frequency divider and reference signal, this phase error makes phase discriminator export corresponding periodically stepped voltage waveform, the loop filter of fractional phase lock loop is low pass filter, staircase waveform will carry out periodic frequency modulation by loop filter to voltage controlled oscillator, produce parasitic stray, this spuious be exactly fractional stray.Frequency difference between fractional stray and output signal is identical with the frequency component of periodicity stepped voltage waveform, is also equal to frequency difference Δ f between reference signal harmonic wave and output signal.When Δ f is greater than loop filter bandwidth, periodically stepped voltage waveform can by loop filter filtering, fractional stray is effectively suppressed, and when reference signal harmonic frequency closely output signal frequency, to such an extent as to Δ f is when being less than loop filter bandwidth, fractional stray appears near output signal spectrum, can affect the performance technologies index of frequency synthesizer time serious.
Summary of the invention
The present invention proposes a kind of circuit and the method that suppress fractional phase lock loop fractional stray, solves the problem that the fractional stray of decimal pll output signal in prior art is larger.
Technical scheme of the present invention is achieved in that
A kind of circuit suppressing fractional phase lock loop fractional stray, comprise at least two-stage fractional phase lock loop, front and back stages fractional phase lock loop is connected by frequency divider, the output signal of prime fractional phase lock loop after frequency divider frequency division as the reference-input signal of rear class fractional phase lock loop;
Prime fractional phase lock loop and rear class fractional phase lock loop adopt same structure, comprise: the output signal of voltage controlled oscillator carries out fractional frequency division through N.F frequency divider, signal after frequency division and reference-input signal carry out phase demodulation operation at phase discriminator, phase detector output signal sends into loop filter, and loop filter produces the voltage-controlled voltage of voltage controlled oscillator.
Alternatively, described N.F frequency divider inside adopts ∑ Delta modulator to control the frequency dividing ratio of integer frequency divider.
Alternatively, described ∑ Delta modulator adopts over-sampling mode to control the frequency dividing ratio of integer frequency divider.
Present invention also offers a kind of method suppressing fractional phase lock loop fractional stray, adopt at least two-stage fractional phase lock loop structure, front and back stages fractional phase lock loop is connected by frequency divider, the output signal of prime fractional phase lock loop after frequency divider frequency division as the reference-input signal of rear class fractional phase lock loop; When output signal frequency is constant, by the fractional frequency division ratio of the frequency and front and back stages fractional phase lock loop that arrange rear class fractional phase lock loop reference-input signal, change the frequency-splitting Δ f between reference-input signal harmonic wave and output signal, make frequency-splitting Δ f outside loop filter bandwidth, then carry out filtering by loop filter.
The invention has the beneficial effects as follows:
(1) directly change the frequency of fractional stray, not by the impact of the nonlinear circuit such as phase discriminator, frequency divider in circuit, there is better spurious reduction effect;
(2) the fractional stray frequency translation of fractional phase lock loop is outside bandwidth of phase lock loop, by loop filter filtering, thus reaches the object suppressing fractional stray.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of control block diagram suppressing fractional phase lock loop fractional stray circuit of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The reference signal frequency of fractional phase lock loop changes with frequency dividing ratio change, the circuit of suppression fractional phase lock loop fractional stray of the present invention adopts at least two-stage fractional phase lock loop structure, front and back stages fractional phase lock loop is connected by frequency divider M, as shown in Figure 1, the output signal fouta of prime fractional phase lock loop A as the reference-input signal frb of rear class fractional phase lock loop B, suppresses the spuious of former fractional phase lock loop mutually by many ring locks after frequency divider M frequency division.
Prime fractional phase lock loop A and rear class fractional phase lock loop B adopts same structure, the output signal fouta/foutb of voltage controlled oscillator VCO carries out fractional frequency division through N.F frequency divider, signal after frequency division and reference-input signal fra/frb carry out phase demodulation operation at phase discriminator, phase detector output signal sends into loop filter, and loop filter produces the voltage-controlled voltage of voltage controlled oscillator.
N.F frequency divider adopts ∑ Delta modulator to control the frequency dividing ratio of integer frequency divider.∑ Delta modulator adopts oversampling technique, has noise shaping effect, can suppress low-frequency noise and low-frequency noise is focused on high frequency region.Control the frequency dividing ratio of integer frequency divider with ∑ Delta modulator, can suppress, by the noise of phase error generation between output signal of frequency divider and reference signal and spuious, its energy to be moved to high frequency region, then passes through loop filter filtering.
The present invention is by rationally arranging the frequency of rear class fractional phase lock loop reference-input signal and the fractional frequency division ratio of front and back stages fractional phase lock loop, when ensureing that output signal frequency is constant, change the frequency-splitting Δ f between reference-input signal harmonic wave and output signal, make frequency-splitting Δ f outside loop filter bandwidth, carry out filtering by loop filter again, reach the object suppressing fractional stray.
The output signal fouta of fractional phase lock loop A is the reference-input signal frb of fractional phase lock loop B after frequency division, thus can change the reference-input signal frequency of fractional phase lock loop B, changes the spurious frequency that fractional phase lock loop B exports further.
Be given by the specific embodiment that the present invention suppresses fractional phase lock loop fractional stray below:
Fractional phase lock loop B reference-input signal frb frequency is 50MHz, supposes that the fractional frequency division of fractional phase lock loop B is than 100.001, loop filter bandwidth 100kHz, then output signal frequency 5.00005GHz.The 20 subharmonic difference DELTA f of output signal foutb and reference signal frb are 50kHz, are less than loop filter bandwidth 100kHz, therefore cannot, by loop filter filtering, are modulated in the output of voltage controlled oscillator, form fractional stray.
The reference input frequency reducing fractional phase lock loop B is frequency 49.753731343283582MHz, changing fractional frequency division ratio is 100.1, output signal frequency is 5.00005GHz, frequency remains unchanged, the 20 subfrequency difference DELTA f of output signal foutb and reference signal frb are 4.9753731343283582MHz, much larger than cycle of phase-locked loop filter bandwidht, by the effective filtering of loop filter, can suppress spuious.
Fractional phase lock loop A reference-input signal fra frequency fixes 50MHz, the loop filter bandwidth of fractional phase lock loop A is similarly 100kHz, output signal fouta frequency is 4.9753731343283582GHz, M=100, fouta=100*frb, frb=49.753731343283582MHz, fractional phase lock loop A outputs signal fouta and self fractional stray signal frequency difference is 24.6268656716418MHz, much larger than the loop filter bandwidth of fractional phase lock loop A, can by the effective filtering of loop filter, the fractional stray of self that fractional phase lock loop A outputs signal fouta is very little, fractional phase lock loop B can not be had influence on export.
Therefore, by rationally arranging the operating state of two fractional phase lock loops, while the fractional stray suppressing fractional phase lock loop B, can not introduce new spuious from fractional phase lock loop A.
Circuit of the present invention and method directly can change the frequency of fractional stray, not by the impact of the nonlinear circuit such as phase discriminator, frequency divider in circuit, have better spurious reduction effect; The fractional stray frequency translation of fractional phase lock loop, outside bandwidth of phase lock loop, by loop filter filtering, thus reaches the object suppressing fractional stray.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. one kind is suppressed the circuit of fractional phase lock loop fractional stray, it is characterized in that, comprise at least two-stage fractional phase lock loop, front and back stages fractional phase lock loop is connected by frequency divider, the output signal of prime fractional phase lock loop after frequency divider frequency division as the reference-input signal of rear class fractional phase lock loop;
Prime fractional phase lock loop and rear class fractional phase lock loop adopt same structure, comprise: the output signal of voltage controlled oscillator carries out fractional frequency division through N.F frequency divider, signal after frequency division and reference-input signal carry out phase demodulation operation at phase discriminator, phase detector output signal sends into loop filter, and loop filter produces the voltage-controlled voltage of voltage controlled oscillator.
2. a kind of circuit suppressing fractional phase lock loop fractional stray as claimed in claim 1, is characterized in that, described N.F frequency divider inside adopts ∑ Delta modulator to control the frequency dividing ratio of integer frequency divider.
3. a kind of circuit suppressing fractional phase lock loop fractional stray as claimed in claim 2, is characterized in that, described ∑ Delta modulator adopts over-sampling mode to control the frequency dividing ratio of integer frequency divider.
4. one kind is suppressed the method for fractional phase lock loop fractional stray, it is characterized in that, adopt at least two-stage fractional phase lock loop structure, front and back stages fractional phase lock loop is connected by frequency divider, the output signal of prime fractional phase lock loop after frequency divider frequency division as the reference-input signal of rear class fractional phase lock loop; When output signal frequency is constant, by the fractional frequency division ratio of the frequency and front and back stages fractional phase lock loop that arrange rear class fractional phase lock loop reference-input signal, change the frequency-splitting Δ f between reference-input signal harmonic wave and output signal, make frequency-splitting Δ f outside loop filter bandwidth, then carry out filtering by loop filter.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106788423A (en) * | 2017-01-11 | 2017-05-31 | 扬州通信设备有限公司 | A kind of frequency synthesizer module and its spuious filter method |
| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN112636747A (en) * | 2020-12-22 | 2021-04-09 | 成都华微电子科技有限公司 | Phase-locked loop reference stray rapid simulation method |
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| CN1178613A (en) * | 1995-03-16 | 1998-04-08 | 夸尔柯姆股份有限公司 | Direct digital synthesizer driven PLL frequency synthesizer with clean-up PLL |
| US6069524A (en) * | 1998-12-23 | 2000-05-30 | Zenith Electronics Corporation | FPLL with third multiplier in an analog input signal |
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| CN106788423A (en) * | 2017-01-11 | 2017-05-31 | 扬州通信设备有限公司 | A kind of frequency synthesizer module and its spuious filter method |
| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN110190847B (en) * | 2019-04-26 | 2023-06-02 | 西安邮电大学 | Decimal N frequency dividing circuit and method applied to frequency synthesizer |
| CN112636747A (en) * | 2020-12-22 | 2021-04-09 | 成都华微电子科技有限公司 | Phase-locked loop reference stray rapid simulation method |
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