CN104467827A - Spurious suppression method for fractional-n frequency synthesizer - Google Patents
Spurious suppression method for fractional-n frequency synthesizer Download PDFInfo
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Abstract
The invention belongs to the technical field of frequency synthesizer spurious suppression, and particularly relates to a spurious suppression method for a fractional-n frequency synthesizer. The method includes the steps that the frequency interval delta f between the spurious frequency of an output frequency spectrum of the fractional-n frequency synthesizer and the peak value of the output frequency spectrum of the fractional-n frequency synthesizer is acquired; a variable frequency divider is arranged, and output frequency control parameters of the fractional-n frequency synthesizer are determined according to the needed output frequency of the fractional-n frequency synthesizer; if delta f>=mfL, M frequency division is conducted on the reference frequency through the variable frequency divider, wherein m is a set natural number; if 0<delta f<mfL, M+1 frequency division is conducted on the reference frequency through the variable frequency divider; the fractional-n frequency synthesizer outputs the needed frequency according to the output frequency control parameters of the fractional-n frequency synthesizer.
Description
Technical field
The invention belongs to Frequency Synthesizer Spuriousness suppression technology field, particularly a kind of fractional-N frequency synthesizer spurious reduction method.
Background technology
In traditional single integers phase-locked loop (PLL) frequency synthesizer, the frequency interval that phase-locked loop exports is equal with phase demodulation frequency, realize meticulousr frequency interval, program frequency division will increase, what now phase-locked loop exported makes an uproar mutually and can worsen, and frequency resolution is higher, then phase demodulation frequency is lower, and the transient state time that loop enters locking is longer.So traditional single integers PLL frequency synthesizer to realize higher frequency resolution and frequency switching time faster simultaneously.Fractional-N frequency synthesizer well solves the contradiction that traditional single integers phase-locked loop high phase comparison frequency and high frequency resolution can not realize simultaneously, also traditional single integers phase-locked loop phase noise and the contradiction of frequency switching time is solved, therefore fractional-N frequency synthesizer is widely applied in recent years, and fractional-N frequency synthesizer has following three kinds of implementation methods: broken number frequency division synthesizer, DDS (direct digital frequency synthesier)+PLL frequency synthesizer, full digital DDS frequency synthesizer.But, because fraction division is than the average divide ratio of integer frequency ratio being actually different time sections, so all there is a common drawback in these three kinds of fractional-N frequency synthesizers: be exactly because the frequency dividing ratio of Different periods is different, cause in output except cross dominant frequency spectrum except, also exist spuious.
Summary of the invention
The object of the invention is to propose a kind of fractional-N frequency synthesizer spurious reduction method, the present invention is applicable to all frequency synthesizers relevant with fraction division.There is spurious reduction thorough, the simple feature of circuit.
For realizing above-mentioned technical purpose, the present invention adopts following technical scheme to be achieved.
A kind of fractional-N frequency synthesizer spurious reduction method, it is characterized in that having loop filter in described fractional-N frequency synthesizer, the bandwidth of described loop filter is f
l; Described fractional-N frequency synthesizer spurious reduction method comprises the following steps:
Draw the frequency interval Δ f of the spurious frequency of fractional-N frequency synthesizer output spectrum and the peak value of fractional-N frequency synthesizer output spectrum;
At the reference frequency input of described fractional-N frequency synthesizer, a variable frequency divider is set, described variable frequency divider is used for carrying out M frequency division or M+1 frequency division to reference frequency, and for the signal after frequency division is exported in described fractional-N frequency synthesizer, M be greater than 1 natural number; Output frequency needed for fractional-N frequency synthesizer, determines the output frequency controling parameters of the fractional-N frequency synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting; If 0 < Δ f < mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer;
Fractional-N frequency synthesizer, according to the output frequency controling parameters of fractional-N frequency synthesizer, exports required frequency.
Feature of the present invention and further improvement are:
Described fractional-N frequency synthesizer is broken number frequency division synthesizer, the parametric frequency divider that described broken number frequency division synthesizer comprises phase discriminator, decimal frequency divider, divide ratio are integer R, described parametric frequency divider is for receiving reference frequency, and the output of described parametric frequency divider is electrically connected an input of phase discriminator; The output of described phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, and the output of described voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection decimal frequency divider, and described voltage controlled oscillator is for exporting required frequency; The output frequency controling parameters of described fractional-N frequency synthesizer is the divide ratio of described broken number frequency division synthesizer;
After arranging variable frequency divider, the divide ratio of output frequency, parametric frequency divider needed for fractional-N frequency synthesizer, determines the divide ratio of the broken number frequency division synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting, and the span of m is 25 to 35; If 0 < Δ f < mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer.
The parametric frequency divider that described fractional-N frequency synthesizer comprises phase discriminator, Direct Digital Synthesizer, divide ratio are integer R, described parametric frequency divider is for receiving reference frequency, and the output of described parametric frequency divider is electrically connected an input of phase discriminator; The output of described phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, the output of described voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection Direct Digital Synthesizer, and described voltage controlled oscillator is for exporting required frequency; The output frequency controling parameters of described fractional-N frequency synthesizer is the generated frequency of described Direct Digital Synthesizer;
After arranging variable frequency divider, the divide ratio of output frequency, parametric frequency divider needed for fractional-N frequency synthesizer, determines the generated frequency of the Direct Digital Synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting, and the span of m is 8 to 12; If 0 < Δ f < mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer.
The frequency interval Δ f of the spurious frequency of described fractional-N frequency synthesizer output spectrum and the peak value of fractional-N frequency synthesizer output spectrum is:
Δf＝K×(f
Omod f
D)
Wherein, K is positive integer, f
orepresent the output frequency of voltage controlled oscillator, f
drepresent the phase demodulation frequency of phase discriminator, mod represents complementation computing.
Beneficial effect of the present invention is: adopt the method for variable reference frequency to suppress the spuious of fractional-N frequency synthesizer, Frequency spectrum quality good in full frequency band can be realized, circuit realiration is simple, only suitably need adjust clock frequency, add dual-modulus prescaler or the variable frequency divider of one-level monolithic, just can be realized by program control frequency dividing ratio.The present invention has general applicability.
Accompanying drawing explanation
Fig. 1 is the schematic block circuit diagram of broken number frequency division synthesizer;
Fig. 2 is the structural representation after the reference frequency input of broken number frequency division synthesizer arranges variable frequency divider;
Fig. 3 is the schematic flow sheet of the spurious reduction of broken number frequency division synthesizer;
Fig. 4 is the schematic block circuit diagram of Direct Digital Synthesizer;
Fig. 5 is the structural representation of Direct Digital Synthesizer when carrying out spurious reduction;
Fig. 6 is the schematic block circuit diagram of DDS+PLL frequency synthesizer;
Fig. 7 is the structured flowchart of DDS+PLL frequency synthesizer when carrying out spurious reduction;
Fig. 8 is the schematic flow sheet that DDS+PLL frequency synthesizer carries out spurious reduction;
Fig. 9 is the schematic diagram of the specific embodiment of Direct Digital Synthesizer;
The output spectrum schematic diagram of the Direct Digital Synthesizer that Figure 10 a is output frequency when not carrying out spurious reduction when being 87MHz;
Figure 10 b is output frequency carries out the output spectrum schematic diagram of the Direct Digital Synthesizer after spurious reduction when being 87MHz;
The output spectrum schematic diagram of the Direct Digital Synthesizer that Figure 11 is output frequency when not carrying out spurious reduction when being 95.001MHz;
Figure 12 is output frequency carries out the output spectrum schematic diagram of the Direct Digital Synthesizer after spurious reduction when being 95.001MHz.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
In the embodiment of the present invention, fractional-N frequency synthesizer is broken number frequency division synthesizer, DDS (direct digital frequency synthesier)+PLL frequency synthesizer or full digital DDS frequency synthesizer (Direct Digital Synthesizer).Be described for these three kinds of implementations of fractional-N frequency synthesizer respectively below.
With reference to Fig. 1, it is the schematic block circuit diagram of broken number frequency division synthesizer.The parametric frequency divider that broken number frequency division synthesizer comprises phase discriminator, decimal frequency divider, divide ratio are integer R, parametric frequency divider is for receiving reference frequency f
r, an input of the output electrical connection phase discriminator of parametric frequency divider; The output of phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, and the output of voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection decimal frequency divider, and voltage controlled oscillator is for exporting required frequency.
For broken number frequency division synthesizer, it utilizes Different periods to adopt the method for different frequency dividing ratio to realize, its fractional frequency division is than the mean value of different integer frequency ratios being actually different time interval, during loop-locking, decimal frequency divider output frequency and phase demodulation frequency are also unequal, can produce time dependent phase error, the control voltage produced after loop filter is periodically modulated voltage controlled oscillator (VCO), is formed regular spuious.This is spuious with the frequency interval Δ f of the peak value (dominant frequency is composed) of fractional-N frequency synthesizer output spectrum is:
Δf＝K×(f
Omod f
D) (1)
Wherein, K is positive integer, f
orepresent the output frequency of voltage controlled oscillator, f
drepresent the phase demodulation frequency of phase discriminator.F
omodf
dfor getting f
odivided by f
dremainder.As: f
d=5MHz, f
o=50.001MHz, then Δ f
spurfor the integral multiple of 1kHz, namely depart from dominant frequency spectrum 1kHz, 2kHz, 3kHz ... frequency on exist spuious.
When the spuious dominant frequency being distributed in fractional-N frequency synthesizer output spectrum composes far-end, be easy to by loop filter filtering, when spuious gradually when the dominant frequency spectrum of fractional-N frequency synthesizer output spectrum, loop filter filtering is more and more difficult, find after deliberation, as Δ f>=30f
ltime, (f
lfor loop filter bandwidth), spuious can the basic filtering of filtered device, as Δ f < 30f
land it is spuious very difficult by filtering when the dominant frequency spectrum of crossover frequency synthesizer output spectrum gradually.Therefore, in embodiments of the present invention, at the reference frequency input of described fractional-N frequency synthesizer, a variable frequency divider is set, described variable frequency divider is used for carrying out M frequency division or M+1 frequency division to reference frequency, and for the signal after frequency division is exported in described fractional-N frequency synthesizer, M be greater than 1 natural number.
With reference to Fig. 2, for the reference frequency input of broken number frequency division synthesizer arranges the structural representation after variable frequency divider.With reference to Fig. 3, it is the schematic flow sheet of the spurious reduction of broken number frequency division synthesizer.In the embodiment of the present invention, after arranging variable frequency divider, the divide ratio of output frequency and parametric frequency divider needed for fractional-N frequency synthesizer, determines the divide ratio of the decimal frequency divider corresponding with the divide ratio of described variable frequency divider.If Δ f>=30f
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer; If 0 < Δ f < 30f
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to fractional-N frequency synthesizer.Like this, adopt M+1 frequency division when spuious by when appearing in the near-end of fractional-N frequency synthesizer output spectrum peak value, can find out according to formula (1), change f
dfrequency interval that the is spuious and peak value of fractional-N frequency synthesizer output spectrum can be changed, like this, far-end can be transferred to by spuious for the peak value near-end of fractional-N frequency synthesizer output spectrum, by loop filter by its filtering, serve good spurious reduction effect.
With reference to Fig. 4, it is the schematic block circuit diagram of Direct Digital Synthesizer.Direct Digital Synthesizer comprises phase accumulator, wave memorizer, digital to analog converter, low pass filter, and phase accumulator, wave memorizer and digital to analog converter (D/A converter) are respectively used to receive reference frequency f
c, phase accumulator is at reference frequency f
cpromotion under, add up to frequency control word, instantaneous accumulation result, as address addressing in wave memorizer, obtains corresponding amplitude sequence, obtain the stepped-up voltage of simulating after being changed by D/A again, eventually pass low pass filter and obtain level and smooth signal.Full digital DDS frequency synthesizer has the features such as frequency resolution is high, frequency switching time fast, output phase noise is low, spurious reduction is poor.
The spuious of full digital DDS frequency synthesizer causes primarily of Phase Truncation Error, amplitude quantization error, D/A converter nonlinearity erron.Phase Truncation Error is the impact due to waveform holder ROM memory space, and in N bit accumulator, high M' position is used for addressing, and low N-M' position is rejected, and this creates the terminal phase error.The spuious interval delta f that Phase Truncation Error causes
spurphaseerrorfor:
Wherein, D is the decimal number that frequency word is rejected bit.
The producing cause of amplitude quantization error is: the data bits of wave memorizer is limited, and wave-shape amplitude stored therein produces finite word length effect after quantizing, and forms amplitude quantization error.Due to the irrational characteristic of D/A converter, limited during its resolution, output be staircase waveform, non-linear again because of D/A converter, staircase waveform can produce harmonic wave and spurious components at output.
The spuious very difficult formula Unify legislation that DDS exports, but higher spuious coincidence formula (3) is in actual design, and spuious output has certain regularity, and for a certain fixing frequency range, spuious distribution trend is substantially identical.Namely with frequency raise or reduce, spuious gradually near or compose away from dominant frequency.
Δf＝af
c±bf
o(3)
Wherein, a value is 0,1,2 ..., b value is 2,3 ...
For Direct Digital Synthesizer, in the present invention, adopt the method for V-CLK, utilize the regularity of spuious distribution, can well suppress spuious.Reference Fig. 5 is that Direct Digital Synthesizer carries out structural representation during spurious reduction.At the reference frequency input of Direct Digital Synthesizer, increase one-level variable frequency divider, and the frequency dividing ratio of this frequency divider is controlled by a controller, change DDS input clock, change the information such as frequency control word simultaneously, output factors is made to appear at the far-end of dominant frequency spectrum, by bounce frequency filter by its filtering.
With reference to Fig. 6, it is the schematic block circuit diagram of DDS+PLL frequency synthesizer.The parametric frequency divider that DDS+PLL frequency synthesizer comprises phase discriminator, Direct Digital Synthesizer, divide ratio are integer R, parametric frequency divider for receiving reference frequency, an input of the output electrical connection phase discriminator of parametric frequency divider; The output of phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, and the output of voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection Direct Digital Synthesizer, and voltage controlled oscillator is for exporting required frequency; The output frequency controling parameters of fractional-N frequency synthesizer is the generated frequency of Direct Digital Synthesizer.
For DDS+PLL frequency synthesizer, Direct Digital Synthesizer (DDS) wherein, as program divider, can realize fraction division, but intrinsic spuious of DDS still can be incorporated in this application.The spuious distribution of DDS+PLL frequency synthesizer compared with the Frequency point of multizone is:
N×f
d±1/2
k×f
d+Δf (4)
Wherein, f
dfor phase demodulation frequency, N is integer, and Δ f span is 0 < Δ f < 10f
l(f
lfor loop filter bandwidth), k is 1,2,3 ...Test proves, meets the frequency that above formula exports, its spuious integral multiple being spaced apart Δ f composed with DDS+PLL frequency synthesizer output spectrum dominant frequency, and, as k > 3, spuious very little, thus only consider k=1,2, the situation of 3.Meet the output frequency of above-mentioned condition, its spuious being spaced apart apart from dominant frequency spectrum:
Δf＝M×(f
O-(N×f
d±1/2
k×f
d)) (5)
Wherein, Δ f is the frequency interval of the spurious frequency of described fractional-N frequency synthesizer output spectrum and the peak value of fractional-N frequency synthesizer output spectrum, adopts the method for variable phase demodulation frequency, can remain Δ f>=10f
l, thus effectively suppressing spuious, with reference to Fig. 7, is structured flowchart when DDS+PLL frequency synthesizer carries out spurious reduction.With reference to Fig. 8, for DDS+PLL frequency synthesizer carries out the schematic flow sheet of spurious reduction.When carrying out spurious reduction for DDS+PLL frequency synthesizer, at the reference frequency input of described DDS+PLL frequency synthesizer, a variable frequency divider is set, described variable frequency divider is used for carrying out M frequency division or M+1 frequency division to reference frequency, and for the signal after frequency division is exported in described fractional-N frequency synthesizer, M be greater than 1 natural number.As 0 < Δ f < mf
ltime, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer; Like this, just can by spuious be transferred to dominant frequency spectrum far-end, by loop filter filtering.If spuious index request is higher, M+3 frequency division can also be adopted.
Divide three specific embodiments so that broken number frequency division synthesizer, DDS+PLL frequency synthesizer or Direct Digital Synthesizer to be described below.
Embodiment 1, is described the spurious reduction of Direct Digital Synthesizer.
Direct Digital Synthesizer produces the pure local oscillation signal of frequency spectrum.Frequency range is 40MHz ~ 98MHz, and frequency interval is 25kHz.
With reference to Fig. 9, it is the schematic diagram of the specific embodiment of Direct Digital Synthesizer.The reference frequency that temperature compensating crystal oscillator exports produces the clock signal of 1.6GHz by phase-locked loop circuit, phase-locked loop circuit is large-scale integrated phase lock circuitry AD4113, include parametric frequency divider, program divider, phase discriminator and charge and discharge electric pump, this phase-locked loop only produces a point frequently, the clock signal of 1.6GHz carries out frequency division by variable frequency divider AD9513, and the frequency after frequency division is as the reference clock of DDS chip (model is AD9951).DDS chip can realize three road frequency programmable dividings, and frequency dividing ratio scope is 1 to 32.General employing 4 frequency division, maximum output frequency can reach 200MHz.By calculating, dsp chip (model is TMS320VC5416) judges that the spuious distance apart from dominant frequency spectrum controls frequency dividing ratio to suppress spuious, according to the reference clock after change, calculate the frequency word of DDS and preset, ensure that Frequency spectrum quality good in full frequency band.With reference to Figure 10 a, the output spectrum schematic diagram of Direct Digital Synthesizer when not carrying out spurious reduction when be output frequency being 87MHz.With reference to Figure 10 b, when be output frequency being 87MHz, carry out the output spectrum schematic diagram of the Direct Digital Synthesizer after spurious reduction.In Figure 10 a and Figure 10 b, transverse axis represents frequency, and unit is MHz, and the longitudinal axis represents the amplitude output signal of Direct Digital Synthesizer, and unit is that in dBm, Figure 10 a and Figure 10 b, every lattice represent identical band width.Can find out, in Figure 10 a, adopt the fixed reference clock of 400MHz, output factors is very large, and in Figure 10 b, after adopting variable reference clock, Frequency spectrum quality is pure, is spuiously well suppressed.
Embodiment 2, is described the spurious reduction of DDS+PLL frequency synthesizer.
In DDS+PLL frequency synthesizer, parametric frequency divider produces the pure local oscillation signal of frequency spectrum.Frequency range is 72MHz ~ 102MHz, and frequency interval is 10Hz.The DDS device adopted is AD9850BRS, and when input highest frequency is 125MHz, output resolution ratio can reach 0.0291Hz, therefore for phase discriminator, no matter adopt how high phase demodulation frequency, always the frequency interval of 10 Hz can be accomplished, in the present embodiment, adopt higher phase demodulation frequency.
In DDS+PLL frequency synthesizer, reference frequency is exported to variable frequency divider (two film prescalar) by 80 MHz crystal oscillators, two film prescalar model is μ p571 (16 17), its divide ratio is 16 or 17, divide ratio is controlled by CPU, voltage controlled oscillator export after DDS frequency division with the output signal ratio phase of parametric frequency divider, loop filter is made up of current mode charge and discharge electric pump and low pass filter, the effect of current mode charge and discharge electric pump is converted to direct voltage by than the phase error after mutually, low pass filter is to this voltage filter, pressuring controlling oscillator frequency is controlled after filtering, it is made to be locked in required frequency.CPU controls the output frequency of voltage controlled oscillator by the phase step of control DDS.
For DDS+PLL frequency synthesizer, its output spectrum can produce regularity, and other is spuious, and this rule is fundamentally to suppress only by optimization line parameter circuit value, supposes that trivial phase ring output frequency is f
o, phase demodulation frequency is f
r, then main spuious distributed points Δ f (Δ f is the spuious frequency departing from dominant frequency spectrum peak) is:
Δf＝M×(f
O-(N×f
d±1/2
k×f
d))
Work as f
o=75.001MHz, f
dduring=5MHz, Δ f=1kHz, 2kHz, 3kHz, 4kHz; Work as f
o=72.501MHz, f
dduring=5MHz, Δ f=1kHz, 2kHz, 3kHz, 4kHz; With reference to Figure 11, when not carrying out spurious reduction when be output frequency being 95.001MHz, (now, the divide ratio of two film prescalar is 16, phase demodulation frequency f
dfor 5MHz) the output spectrum schematic diagram of Direct Digital Synthesizer.With reference to Figure 12, after carrying out spurious reduction when be output frequency being 95.001MHz, (now, the divide ratio of two film prescalar is 17, phase demodulation frequency f
dfor 4.70588MHz) the output spectrum schematic diagram of Direct Digital Synthesizer.In Figure 11 and Figure 12, transverse axis represents frequency, and unit is MHz, and the longitudinal axis represents the amplitude output signal of Direct Digital Synthesizer, and unit is in dBm, Figure 11 and Figure 12, and every lattice represent identical band width.Find out from the contrast of Figure 11 and Figure 12, after adopting the present invention, the spuious of output frequency of DDS+PLL frequency synthesizer is well suppressed.
Embodiment 3, is described the spurious reduction of broken number frequency division synthesizer.
The reference frequency output of broken number frequency division synthesizer is 72MHz ~ 102MHz, and frequency interval is 1kHz.When utilizing the present invention to carry out spurious reduction to broken number frequency division synthesizer, the divide ratio of the variable frequency divider adopted is 10 or 11, model E8690, during program calculation frequency dividing ratio, variable frequency divider adopts 10 frequency divisions, when spuious by appear in dominant frequency spectrum near-end time, adopt 11 frequency divisions, can find out according to formula (1), change phase demodulation frequency and can change frequency interval that is spuious and output spectrum peak value, like this, dominant frequency can be composed that near-end is spuious is transferred to far-end, then by loop filter by its filtering, serve good inhibitory action.
In sum, the present invention is by studying the variegation of fractional-N frequency synthesizer, sum up its spuious rule, simultaneously by adding variable division link, the phase demodulation frequency of appropriate change PLL or the clock frequency of full digital DDS, change its spuious distribution, add the method for filter by spuious filtering by cycle of phase-locked loop filter or full digital DDS frequency synthesizer output.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (4)
1. a fractional-N frequency synthesizer spurious reduction method, is characterized in that, has loop filter in described fractional-N frequency synthesizer, and the bandwidth of described loop filter is f
l; Described fractional-N frequency synthesizer spurious reduction method comprises the following steps:
Draw the frequency interval Δ f of the spurious frequency of fractional-N frequency synthesizer output spectrum and the peak value of fractional-N frequency synthesizer output spectrum;
At the reference frequency input of described fractional-N frequency synthesizer, a variable frequency divider is set, described variable frequency divider is used for carrying out M frequency division or M+1 frequency division to reference frequency, and for the signal after frequency division is exported in described fractional-N frequency synthesizer, M be greater than 1 natural number; Output frequency needed for fractional-N frequency synthesizer, determines the output frequency controling parameters of the fractional-N frequency synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting; If 0< Δ f<mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer;
Fractional-N frequency synthesizer, according to the output frequency controling parameters of fractional-N frequency synthesizer, exports required frequency.
2. a kind of fractional-N frequency synthesizer spurious reduction method as claimed in claim 1, it is characterized in that, described fractional-N frequency synthesizer is broken number frequency division synthesizer, the parametric frequency divider that described broken number frequency division synthesizer comprises phase discriminator, decimal frequency divider, divide ratio are integer R, described parametric frequency divider is for receiving reference frequency, and the output of described parametric frequency divider is electrically connected an input of phase discriminator; The output of described phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, and the output of described voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection decimal frequency divider, and described voltage controlled oscillator is for exporting required frequency; The output frequency controling parameters of described fractional-N frequency synthesizer is the divide ratio of described broken number frequency division synthesizer;
After arranging variable frequency divider, the divide ratio of output frequency, parametric frequency divider needed for fractional-N frequency synthesizer, determines the divide ratio of the broken number frequency division synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting, and the span of m is 25 to 35; If 0< Δ f<mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer.
3. a kind of fractional-N frequency synthesizer spurious reduction method as claimed in claim 1, it is characterized in that, the parametric frequency divider that described fractional-N frequency synthesizer comprises phase discriminator, Direct Digital Synthesizer, divide ratio are integer R, described parametric frequency divider is for receiving reference frequency, and the output of described parametric frequency divider is electrically connected an input of phase discriminator; The output of described phase discriminator is serially connected with loop filter and voltage controlled oscillator successively, the output of described voltage controlled oscillator is electrically connected another input of described phase discriminator after serial connection Direct Digital Synthesizer, and described voltage controlled oscillator is for exporting required frequency; The output frequency controling parameters of described fractional-N frequency synthesizer is the generated frequency of described Direct Digital Synthesizer;
After arranging variable frequency divider, the divide ratio of output frequency, parametric frequency divider needed for fractional-N frequency synthesizer, determines the generated frequency of the Direct Digital Synthesizer corresponding with the divide ratio of described variable frequency divider; If Δ f>=mf
l, then use variable frequency divider to carry out M frequency division to reference frequency, and utilize variable frequency divider to export the signal after M frequency division to described fractional-N frequency synthesizer, m is the natural number of setting, and the span of m is 8 to 12; If 0< Δ f<mf
l, then use variable frequency divider to carry out M+1 frequency division to reference frequency, and utilize variable frequency divider to export the signal after M+1 frequency division to described fractional-N frequency synthesizer.
4. a kind of fractional-N frequency synthesizer spurious reduction method as claimed in claim 1, is characterized in that, the frequency interval Δ f of the spurious frequency of described fractional-N frequency synthesizer output spectrum and the peak value of fractional-N frequency synthesizer output spectrum is:
Δf＝K×(f
Omodf
D)
Wherein, K is positive integer, f
orepresent the output frequency of voltage controlled oscillator, f
drepresent the phase demodulation frequency of phase discriminator, mod represents complementation computing.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105652660A (en) * | 2016-01-07 | 2016-06-08 | 北京北广科技股份有限公司 | Single-chip microcomputer-based method for acquiring crossover frequency control word |
| CN106383548A (en) * | 2016-11-14 | 2017-02-08 | 成都西蒙电子技术有限公司 | Low-spur DDS (Direct Digital Synthesizer) source and method for reducing spur of DDS source |
| CN109787624A (en) * | 2018-12-24 | 2019-05-21 | 贵州航天计量测试技术研究所 | A kind of broadband low spurious fractional frequency-division phase-locked loop |
| CN113258929A (en) * | 2021-07-15 | 2021-08-13 | 成都威频通讯技术有限公司 | Low phase noise frequency source circuit |
| CN114070308A (en) * | 2022-01-17 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Broadband low-phase noise frequency synthesis circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107891A (en) * | 1999-05-06 | 2000-08-22 | Applied Micro Circuits Corporation | Integrated circuit and method for low noise frequency synthesis |
| US6114987A (en) * | 1999-05-29 | 2000-09-05 | Sensor Technologies & Systems, Inc. | Dual-loop linearizer for FM-CW radar |
| CN102412837A (en) * | 2011-11-18 | 2012-04-11 | 北京航天测控技术有限公司 | Method for realizing low spurious small-step frequency synthesizer |
| CN103490777A (en) * | 2013-09-30 | 2014-01-01 | 四川九洲电器集团有限责任公司 | Low spurious frequency synthesizer |
| CN103501174A (en) * | 2013-09-25 | 2014-01-08 | 中国电子科技集团公司第四十一研究所 | Low-noise reference signal generator and signal generation method |
-
2014
- 2014-12-31 CN CN201410851192.7A patent/CN104467827B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107891A (en) * | 1999-05-06 | 2000-08-22 | Applied Micro Circuits Corporation | Integrated circuit and method for low noise frequency synthesis |
| US6114987A (en) * | 1999-05-29 | 2000-09-05 | Sensor Technologies & Systems, Inc. | Dual-loop linearizer for FM-CW radar |
| CN102412837A (en) * | 2011-11-18 | 2012-04-11 | 北京航天测控技术有限公司 | Method for realizing low spurious small-step frequency synthesizer |
| CN103501174A (en) * | 2013-09-25 | 2014-01-08 | 中国电子科技集团公司第四十一研究所 | Low-noise reference signal generator and signal generation method |
| CN103490777A (en) * | 2013-09-30 | 2014-01-01 | 四川九洲电器集团有限责任公司 | Low spurious frequency synthesizer |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105652660A (en) * | 2016-01-07 | 2016-06-08 | 北京北广科技股份有限公司 | Single-chip microcomputer-based method for acquiring crossover frequency control word |
| CN105652660B (en) * | 2016-01-07 | 2018-11-30 | 北京北广科技股份有限公司 | A kind of SCM Based method for obtaining crossover frequency control word |
| CN106383548A (en) * | 2016-11-14 | 2017-02-08 | 成都西蒙电子技术有限公司 | Low-spur DDS (Direct Digital Synthesizer) source and method for reducing spur of DDS source |
| CN109787624A (en) * | 2018-12-24 | 2019-05-21 | 贵州航天计量测试技术研究所 | A kind of broadband low spurious fractional frequency-division phase-locked loop |
| CN113258929A (en) * | 2021-07-15 | 2021-08-13 | 成都威频通讯技术有限公司 | Low phase noise frequency source circuit |
| CN113258929B (en) * | 2021-07-15 | 2021-09-24 | 成都威频通讯技术有限公司 | Low phase noise frequency source circuit |
| CN114070308A (en) * | 2022-01-17 | 2022-02-18 | 中国电子科技集团公司第二十九研究所 | Broadband low-phase noise frequency synthesis circuit |
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