CN108964660B - High-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation - Google Patents
High-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model discloses a high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation; the frequency-spreading circuit is composed of a decimal frequency-dividing circuit and a triangular wave generator, wherein the triangular wave generator generates a signal with fixed frequency and is overlapped on the decimal part of the frequency divider, so that the whole decimal frequency-dividing frequency is modulated by triangular waves, and further frequency-spreading output is obtained. The fractional frequency divider adopts a phase delay compensation technology, meanwhile, the proportional relation exists between the remainder of the accumulator in the modulator and the phase difference between the feedback signal and the phase-locked loop reference signal, the remainder in the accumulator is taken out, the phase of the feedback signal (programmable delayer) is controlled after decoding, and the fractional frequency division instantaneous phase error is realized.
Description
Technical Field
The utility model relates to a spread spectrum circuit, in particular to a high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation.
Background
At present, the spread spectrum technology modulates the peak clock to change the peak clock from a narrow-band clock to a frequency spectrum with sideband harmonic, so as to disperse peak energy into a plurality of frequency bands in a spread spectrum area, and achieve the effects of reducing the peak energy and inhibiting EMI. Spread spectrum technology is increasingly used in the prior art.
The utility model of CN201010169367.8 discloses a spread spectrum circuit, which comprises an inverter, a current source, a control unit and a shaping circuit. The inverter input receives an original clock signal. The current source is coupled to the current transmission end of the inverter. The control unit comprises a control circuit, and changes the current of the current source according to the original clock signal to control the charge and discharge speed of the output end of the inverter, so that the output end outputs a voltage signal. The shaping circuit shapes the voltage signal to obtain a spread spectrum clock signal.
The utility model of patent number CN201320529544.8 discloses a phase locked loop circuit; in an embodiment, the phase-locked loop circuit comprises: and the switching capacitor circuit generates a modulation waveform which is injected into the phase-locked loop circuit in a current form, so that the output frequency of the phase-locked loop is modulated. Compared with the spread spectrum phase-locked loop in the prior art, the spread spectrum phase-locked loop in the embodiment of the utility model has the advantages of simple structure, low power consumption, low silicon cost and flexibility in both spread spectrum ratio and modulation frequency.
The utility model of CN200510075533.7 discloses a control circuit of a spread spectrum phase-locked loop, which comprises: a reference frequency divider; a phase detector; charging and pumping; a filter circuit; a voltage controlled oscillating circuit; a modulation control circuit; the structure can make the output frequency of the voltage control oscillating circuit be evenly spread in a fixed range, and the energy can be evenly distributed.
However, the analysis shows that the existing spread spectrum control circuit has the following defects, which are mainly reflected in low resolution and high power consumption, so that the spread spectrum precision can not be improved; it is desirable to provide a high resolution low power spread spectrum control circuit based on phase delay compensation to meet the needs.
Disclosure of Invention
Therefore, in order to solve the above-mentioned shortcomings, the present utility model provides a high-resolution low-power spread spectrum control circuit based on phase delay compensation. The method has the characteristics of high resolution and low power consumption, and by controlling the phase of the feedback signal, the phase error of fractional frequency division is eliminated, and the precision of fractional frequency division is improved, so that the precision of frequency spreading is improved.
The utility model is realized in such a way, and constructs a high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation, which is characterized in that: the spread spectrum circuit is provided with a decimal frequency dividing circuit and a triangular wave generator; the triangular wave generator generates a signal with fixed frequency and is overlapped on the decimal part of the frequency divider, so that the whole decimal frequency division number is subjected to triangular wave modulation, and further spread spectrum output is obtained.
As an improvement of the technical scheme, the high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation; the spread spectrum circuit specifically comprises a plurality of frequency-spreading circuits,
the pre-4 frequency dividing circuit is formed by connecting 2 differential input D flip-flops (4 latches) to generate 8-phase output;
the accumulator repeatedly accumulates fractional parts of the small number control words to generate quantized output, and the remainder part is sent to the decoder to adjust feedback signal delay; when the spread spectrum signal is enabled, the fractional part is additionally added with triangular waves generated by the spread spectrum circuit;
and the decoder is used for decoding the residual value (8 bits) in the accumulator, and dividing the residual value into upper 3 bits and lower 5 bits, wherein the upper 3 bits correspond to 8-bit control signals of the phase selector, and the lower 5 bits correspond to 32-bit thermometer codes of the phase interpolator. The corresponding coding table is shown in the figure. The 32-bit thermometer code is controlled by the fraction of the lower 6 bits, and the highest bit in the lower 6 bits controls the direction of the thermometer code, because when the bit is changed, the phase relation of two paths of phase signals input by the phase interpolator can be overturned, so that the monotonicity of the whole 8-bit programmable delay device is ensured.
The phase selector is used for selecting two adjacent phase signals according to the control word, but the input signal has only 8 paths, namely only 7 adjacent phase intervals and cannot cover the whole period, so when the decoding value is 7, cki <0> is delayed by one period, 8 adjacent phase intervals are generated and the whole period is covered.
The phase interpolator is used for carrying out phase interpolation on input signals ck1 and ck2 under the control of thermometer codes, and the key of the phase interpolator is interpolation linearity.
The N/N+1 mode frequency divider is used for performing div_int [4:0] mode frequency division on the integer frequency division preset number mainly through a five-bit counter and outputting a frequency division clock ckp; the integer frequency division clock is sampled by an 8-phase clock ck [7:0] generated by the four frequency dividers, eight-phase frequency division clocks cki [7:0] are generated, and then cki outputs ck1 and ck2 are selected by a phase selection signal sel [8:1], so that the true 8-bit fractional frequency division is realized by matching with a phase interpolation module.
The triangular wave generator mainly generates triangular waves for modulating 8-bit fractional frequency division values.
The output end of the pre-4 frequency dividing circuit is connected with an N/N+1 mode frequency divider, the output end of the triangular wave generator is connected with the input of an accumulator, the output of the accumulator is respectively connected with the N/N+1 mode frequency divider and a decoder, the output of the N/N+1 mode frequency divider is connected with a phase selector, and the output of the phase selector and the output of the decoder are respectively connected with a phase interpolator.
The fractional frequency divider adopts a phase delay compensation technology, meanwhile, the proportional relation exists between the remainder of the accumulator in the modulator and the phase difference between the feedback signal and the phase-locked loop reference signal, the remainder in the accumulator is taken out, and the phase of the feedback signal (programmable delay) is controlled after decoding, so that the phase error caused by fractional frequency division is eliminated, and the fractional frequency division in the true sense is realized.
As an improvement of the technical scheme, the high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation; for a triangular wave generator, the input signals div_num [8:0], ssc_ppm [3:0], and ssc_cnt [9:0] control the slope of the triangular wave: k_triangular=div_num_ssc_ppm 2^9/ssc_cnt; ssc_ppm [3:0] controls spreading depth ssc_depth= - (ssc_ppm 0.000488218).
The utility model has the following advantages: the frequency-spreading circuit is composed of a decimal frequency-dividing circuit and a triangular wave generator, wherein the triangular wave generator generates a signal with fixed frequency and is overlapped on the decimal part of the frequency divider, so that the whole decimal frequency-dividing frequency is modulated by triangular waves, and further frequency-spreading output is obtained. The fractional frequency divider adopts a phase delay compensation technology, meanwhile, the proportional relation exists between the remainder of the accumulator in the modulator and the phase difference between the feedback signal and the phase-locked loop reference signal, the remainder in the accumulator is taken out, and the phase of the feedback signal (programmable delay) is controlled after decoding, so that the phase error caused by fractional frequency division is eliminated, and the fractional frequency division in the true sense is realized. The utility model provides a novel spread spectrum circuit structure aiming at a spread spectrum circuit under the condition of meeting low power consumption. Phase errors caused by fractional frequency division can be eliminated, so that the spread spectrum precision is improved. And the frequency division ratio can be configured and pass simulation verification.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a spread spectrum circuit of the present utility model;
FIG. 2 is a schematic diagram of a divide-by-4 circuit of the present utility model;
FIG. 3 is a schematic diagram of a simulation waveform of a divide-by-4 circuit of the present utility model;
FIG. 4 is a schematic diagram of the accumulator structure of the present utility model;
FIG. 5 is a schematic diagram of an accumulator simulation waveform of the present utility model;
FIG. 6 is a schematic diagram of a phase selector according to the present utility model;
FIG. 7 is a schematic diagram of the overall structure of a phase interpolator of the present utility model;
FIG. 8 is a schematic diagram of the simulation results of the phase interpolator of the present utility model;
FIG. 9 is a schematic diagram of a divide by N/N+1 circuit according to the present utility model;
FIG. 10 is a schematic diagram of simulation results of the N/N+1 frequency dividing circuit of the present utility model;
FIG. 11 is a schematic diagram of the top control word of the triangular wave generator of the present utility model;
FIG. 12 is a schematic diagram of simulation results of a triangular wave generator according to the present utility model;
FIG. 13 is a schematic diagram of an SSC test circuit of the present utility model;
FIG. 14 is a schematic diagram of the SSC output signal of the present utility model.
Detailed Description
The technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to fig. 1 to 14, and it is apparent that the described embodiments are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The utility model provides a high-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation by improving the circuit; the overall structure of the frequency-spreading circuit is shown in fig. 1, and the frequency-spreading circuit is composed of a fractional frequency-dividing circuit and a triangular wave generator, wherein the triangular wave generator generates a signal with fixed frequency and is overlapped on the fractional part of the frequency divider, so that the whole fractional frequency-dividing number is subjected to triangular wave modulation, and further frequency-spreading output is obtained. The fractional frequency divider adopts a phase delay compensation technology, meanwhile, the remainder of the accumulator and the phase difference between the feedback signal and the phase-locked loop reference signal have a proportional relation, the remainder in the accumulator is taken out, and the phase of the feedback signal (programmable delayer) is controlled after decoding, so that the phase error caused by fractional frequency division is eliminated, and the true fractional frequency division is realized.
The spread spectrum control circuit specifically comprises;
1. a divide-by-4 circuit: the pre-4 frequency circuit structure is shown in fig. 2, and is formed by connecting 2 differential input D flip-flops (4 latches) to generate 8-phase output. The simulation results are shown in fig. 3.
2. An accumulator: as shown in fig. 4, the accumulator repeatedly accumulates fractional portions of the fractional control words to produce quantized outputs, and the remainder portions are sent to the decoder to adjust the feedback signal delay. When the spread spectrum signal is enabled, the fractional portion will additionally add the triangular wave generated by the spread spectrum circuit. Fig. 5 is a simulated waveform of the accumulator.
3. And a decoder: the decoder decodes the remaining value (8 bits) in the accumulator into upper 3 bits corresponding to the 8-bit control signal of the phase selector and lower 5 bits corresponding to the 32-bit thermometer code of the phase interpolator. The corresponding coding table is shown in the figure. The 32-bit thermometer code is controlled by the fraction of the lower 6 bits, and the highest bit in the lower 6 bits controls the direction of the thermometer code, because when the bit is changed, the phase relation of two paths of phase signals input by the phase interpolator can be overturned, so that the monotonicity of the whole 8-bit programmable delay device is ensured.
4. A phase selector: as shown in fig. 6, which shows the structure and operation principle of the phase selector, the phase selector is used to select two adjacent phase signals according to the control word, but the input signal has only 8 paths, which means that only 7 adjacent phase intervals cannot cover the whole period, so when the decoding value is 7, cki <0> will be delayed by one period, thus 8 adjacent phase intervals are generated and the whole period is covered.
5. Phase interpolator: the overall structure of the phase interpolator is shown in fig. 7, the function of the phase interpolator is to interpolate the phases of the input signals ck1 and ck2 under the control of the thermometer code, the key of the phase interpolator is interpolation linearity, the simulation result of the phase interpolator is shown in fig. 8, and the linearity of the phase interpolator is good from the simulation result. The simulation result of the whole 8-bit delayer is shown in fig. 8.
N/n+1 mode divider: as shown in fig. 10, the N/n+1-mode frequency divider is configured to divide the integer frequency division preset number by div_int [4:0] mode mainly by a five-bit counter, and output a frequency division clock ckp; the integer frequency division clock is sampled by an 8-phase clock ck [7:0] generated by the four frequency dividers, eight-phase frequency division clocks cki [7:0] are generated, and then cki outputs ck1 and ck2 are selected by a phase selection signal sel [8:1], so that the true 8-bit fractional frequency division is realized by matching with a phase interpolation module. The simulation results are shown in fig. 12.
7. Triangular wave generator: fig. 11ssc_cnt_gen is a triangular wave generator module, which mainly generates a triangular wave for modulating an 8-bit fractional frequency division value. The input signals div_num [8:0], ssc_ppm [3:0], and ssc_cnt [9:0] control the slope of the triangle wave: k_triangular=div_num_ssc_ppm 2^9/ssc_cnt; ssc_ppm [3:0] control spreading depth ssc_depth= - (ssc_ppm 0.000488218); simulation results fig. 12.
For the present utility model, the formula of the spread spectrum circuit is derived as follows:
(1) Spread spectrum depth calculation:
If(the greatest fractional offset, i.e., spread depth, is obtained at this time)
(taking the inverse N value to achieve the upward spread spectrum effect)
(maximum size offset of spread contribution)
(Loop division ratio)
(spread depth 1ssc ppm corresponds to approximately 500 ppm);
(2) Spread spectrum frequency calculation:
If reference clock is 25MHz,
ssc_cnt[9:0]＝01100 01101(397)
25 MHz/(397×2) = 31.48615KHz (spread spectrum frequency)
If reference clock is 30MHz,
ssc_cnt[9:0]＝01110 11100(476)
30 MHz/(476×2) = 31.51261KHz (spread spectrum frequency).
The overall simulation of the spread spectrum circuit is as follows:
we build a spread spectrum test circuit as in fig. 13, configured as: input signals ckp, ckn are 5G, division ratio 20, spread depth ssc_ppm is 1111 (about 15×500 ppm=7500 ppm), and modulation frequency ssc_cnt is configured at 31.5 kHz. The simulation output results are shown in fig. 14 consistent with the configured inputs.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (1)
1. A high-resolution low-power spread spectrum control circuit based on phase delay compensation is characterized in that: the spread spectrum control circuit is provided with a decimal frequency dividing circuit and a triangular wave generator; the decimal frequency dividing circuit is a circuit consisting of a four-frequency dividing circuit, an accumulator, a decoder, a phase selector, a phase interpolator and an N/N+1 mode frequency divider; the output end of the four frequency dividing circuit is connected with an N/N+1 mode frequency divider, the output end of the triangular wave generator is connected with the input of an accumulator, the output of the accumulator is respectively connected with the N/N+1 mode frequency divider and a decoder, the output of the N/N+1 mode frequency divider is connected with a phase selector, the output of the phase selector and the decoder are respectively connected with a phase interpolator, and the output of the decoder is connected with the phase selector;
the triangular wave generator generates triangular waves for modulating the fractional frequency dividing circuit, and the triangular waves are overlapped on the fractional frequency dividing circuit to enable the fractional frequency dividing circuit to be subjected to triangular wave modulation, so that spread spectrum output is obtained;
the spread spectrum control circuit specifically comprises:
the four-frequency dividing circuit structure is formed by inputting 2 differences into 4 latches, and then connecting and outputting the 4 latches to generate an 8-phase output clock cki [7:0] to the N/N+1-mode frequency divider;
for the accumulator, when the spread spectrum control signal enters the triangular wave generator, the triangular wave generator generates triangular waves and transmits the triangular waves to the accumulator, and meanwhile, the accumulator also receives the control of the frequency division control signal and outputs an integer part and a remainder part; the integer part generated by the accumulator is output to the N/N+1 mode frequency divider, and the remainder part generated by the accumulator is sent to the decoder to adjust the delay of the feedback signal;
the decoder decodes a remainder part in the accumulator, the remainder part is divided into a high 3 bit and a low 5 bit, the high 3 bit corresponds to an 8-phase selection signal sel [8:1] of the phase selector, the low 5 bit corresponds to a 32-bit thermometer code of the phase interpolator, the 32-bit thermometer code is controlled by a low 6-bit fraction, the highest bit in the low 6 bits controls the direction of the thermometer code, and when the bit changes, the phase relation of two paths of phase signals input by the phase interpolator can be overturned, so that the monotonicity of the whole 8-bit programmable delay is ensured;
an N/N+1-mode frequency divider, wherein the N/N+1-mode frequency divider samples an integer part generated by the accumulator through an 8-phase output clock cki [7:0] generated by the four-frequency dividing circuit, and generates an 8-phase frequency division output cki [7:0] for the phase selector;
the phase selector is used for selecting two paths of adjacent phase signals from 8-phase frequency division output cki [7:0] generated by the N/N+1-mode frequency divider according to 8-phase selection signals sel [8:1] output by the decoder to output the signals to the phase interpolator, and because the signals input to the phase selector by the N/N+1-mode frequency divider only have 8 paths, the signals mean that only 7 adjacent phase intervals cannot cover the whole period, when the decoding value is 7, the 8-phase frequency division output cki <0> is delayed for one period, so that 8 adjacent phase intervals are generated and the whole period is covered;
for the phase selector, the 8-phase selection signal sel [8:1] sent by the decoder selects cki outputs ck1 and ck2, and the true 8-bit fractional frequency division is realized by matching with the phase interpolator;
the phase interpolator is used for carrying out phase interpolation on input signals ck1 and ck2 of the phase selector under the control of the thermometer code, and the key of the phase interpolator is interpolation linearity;
the fractional frequency dividing circuit adopts a phase delay compensation technology to take out the remainder in the accumulator and controls the phase of the feedback signal after decoding, thereby reducing the phase error brought by the fractional frequency dividing circuit and realizing the fractional frequency division in the true sense.
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| CN109765583B (en) * | 2019-03-04 | 2021-06-15 | 华通信安(北京)科技发展有限公司 | Clock synchronization method based on GNSS receiver second pulse |
| US11949420B2 (en) | 2019-04-23 | 2024-04-02 | Beijing Boe Technology Development Co., Ltd. | Clock spread spectrum circuit, electronic equipment, and clock spread spectrum method |
| US11381229B2 (en) | 2019-04-23 | 2022-07-05 | Beijing Boe Technology Development Co., Ltd. | Clock spread spectrum circuit, electronic equipment, and clock spread spectrum method |
| CN110488911B (en) * | 2019-07-17 | 2023-04-28 | 晶晨半导体(上海)股份有限公司 | Digital frequency generator and state switching method thereof |
| CN113972902B (en) * | 2020-07-23 | 2024-08-02 | 京东方科技集团股份有限公司 | Clock signal generating circuit, clock signal generating method and electronic equipment |
| CN114283857B (en) * | 2021-12-16 | 2024-05-28 | 上海艾为电子技术股份有限公司 | Delay compensation of frequency division signal, frequency division method, system and frequency divider |
| CN115664388B (en) * | 2022-12-26 | 2023-03-28 | 成都信息工程大学 | Triangular wave generating circuit for delta-sigma fractional frequency division phase-locked loop |
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