KR0149126B1 - Mixed type frequency synthesizer - Google Patents

Abstract

The present invention relates to a hybrid frequency synthesizer, in order to solve the problem that the direct digital frequency synthesizer and the phase locked loop frequency synthesizer in the prior art have high power consumption, low transition speed, complicated circuit, and large chip area. It is used as a carrier frequency generator loop which is a high frequency sine wave by connecting the reference frequency generator in series to the front end of the phase synchronization loop frequency synthesizer so as to use the square and the pulse output as the reference frequency. In order to up-convert the frequency of the variable bandwidth at high frequencies, the output of another frequency synthesizer capable of fine tuning by the variable output bandwidth is injected into the feedback circuit.

Description

Hybrid Frequency Synthesizer

1 is a block diagram of a conventional direct digital frequency synthesizer.

2 is a block diagram of a conventional phase locked loop frequency synthesizer.

3 is a block diagram of a hybrid frequency synthesizer of the present invention.

4 is a detailed block diagram of FIG.

5 is an output waveform according to the present invention, where (a) is the most significant bit (MSB) output waveform diagram of a binary input accumulator. (b) shows the spectrum of the final output stage, respectively.

* Explanation of symbols for main parts of the drawings

100: reference frequency generator 200: phase synchronization loop frequency synthesizer

300: direct digital frequency synthesis unit 400: frequency mixing unit

420, 430: first and second frequency mixer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly, to a hybrid frequency synthesizer for obtaining a wideband sine wave at a high frequency by utilizing the advantages of a direct digital synthesizer and a phase locked loop frequency synthesizer in the digital mobile communication field, a digital signal processing system, and a computer peripheral device. will be.

In general, a frequency synthesizer is a circuit that obtains an output signal having a frequency corresponding to an integer multiple of an input signal frequency, and is widely used in the frequency synthesizer of a signal generator, a communication device, and a receiver.

Accordingly, the conventional direct digital frequency synthesizer refers to a digital signal generator that outputs a frequency corresponding to the binary data word value when a frequency adjusted binary data value is input to a frequency input register. The operation is described with reference to FIG.

The phase accumulator 2, which receives the frequency-adjusted binary data value through the frequency input register 1, adds and outputs the data value inputted according to the system clock frequency and its output value. The feedback value is added back to the original value to count the phase value of the output signal.

At this time, the value output from the phase accumulator 2 is an address bit, and the address bit is temporarily stored in the phase register 3 and output according to the system clock frequency.

By inputting the output address bits in the ROM of the sine look-up table 4, a series of data values representing sinusoidal waveforms are generated.

The data value thus generated is input to a digital-to-analog converter (DAC) 5 and output in a desired quantized sinusoid.

The output sinusoidal waveform is output after the high frequency component is removed by the low pass filter 6, so that an accurate sine wave can be obtained.

Since the output sine wave is not necessarily required in a digital synthesizer or a digital system, there is a problem in that an analog-digital converter must be used again to obtain a square wave.

Since mobile communication devices operate at a high speed and broadband at a high speed, the use of the ROM of the sine lookup table 4 and the low pass filter 6 has disadvantages in terms of chip area, power consumption, and speed.

While such direct digital frequency synthesizers have excellent frequency resolution and stability, the maximum frequency that can be output is only about one quarter of the clock frequency.

In addition, in order to synthesize higher operating frequencies, there is a big problem of increasing the clock frequency.

Therefore, it is inefficient to use only direct digital frequency synthesizer in broadband communication system.

Therefore, in the prior art, a phase-locked loop frequency synthesizer (FIG. 2) that can be synthesized with a wide bandwidth is frequently used.

However, the PLL frequency synthesizer alone has a low switching speed and difficulty in adjusting the frequency increasing step.

To solve this problem, a multiple loop PLL was used, but the circuit was complicated and power consumption increased.

In addition, there is a problem in that the frequency combining function is inferior due to the drift between the voltage controlled oscillator 230 and the digital-to-analog converter (reference numeral 5 in FIG. 1).

As shown in FIG. 2, the output of the crystal oscillator 10 composed of passive elements is used as a reference frequency.

Since the crystal oscillator 10 may generate an unstable frequency, a reference frequency generator having excellent stability is required.

It will take longer to lock the phase to an unstable reference frequency.

Therefore, due to the unstable reference frequency, the synthesized output frequency is inevitably bound.

In order to change the reference frequency, there is a problem in that the value of the passive element in the power receiving oscillator 10 must be changed.

The distortion will also be significant as the reference frequency is changed by capacitance, resistance and reactance.

The phase-synchronized loop frequency synthesizer is a frequency synthesizer that outputs a desired frequency by an integral multiple of the reference frequency, and the integer multiple is determined by the N counter 245 and the MN counter 244 of the programmable 1 / N divider 240. , The frequency division ratio is determined by the frequency divider 241.

The output frequency resolution is determined according to the division ratio of the divider 241.

The phase-lock loop frequency synthesizer is configured to combine the phase detector 210 and the region pass filter 220 to set the frequency channel width as the reference frequency.

At this time, if the reference frequency is large, the width of the synthesized frequency also naturally increases, so that the reference frequency can be redistributed by the divider controller 246.

However, by embedding the divider regulator 246, only the chip area is increased, and the frequency resolution is lowered.

On the other hand, although the synthesized frequency can be sufficiently synthesized to the GHz band according to the external device, if the frequency range is widened and the frequency resolution and stability are poor, it is not suitable for the current communication system.

Recently, since the use range of devices driven with low power is being expanded, there are many points to consider, such as integration and power consumption, if the device is divided into functional devices to increase the synthesis frequency.

Since the present invention is used by mixing a conventional direct digital frequency synthesizer and a phase locked loop frequency synthesizer, it is possible to compensate for the advantages and disadvantages of each other.

However, in the related art, a hybrid PLL / DOS frequency synthesizer using a direct digital frequency synthesizer and a phase locked loop frequency synthesizer is required to obtain a desired frequency because an independent device is manufactured on a printed board. The number of elements to make became a complicated circuit.

In addition, the hybrid frequency synthesizer manufactured on the board should consider the transition speed, noise, chip area, and power consumption, and supply the sine wave output from the digital frequency synthesizer directly to the phase-lock loop frequency synthesizer. In order to do this, an additional analog-to-digital converter was needed.

The phase-lock loop frequency synthesizer in the related art has a low transition speed, and the frequency synchronizing function is inferior due to the drift of the voltage controlled oscillator (VCO) and the digital-to-analog converter (DAC) of FIG.

In addition, the direct digital frequency synthesizer has problems such as low operating frequency and spurious noise.

Accordingly, the present invention solves the above problems by using a square wave pulse output of a phase accumulator in which binary data is input to obtain a wideband output frequency at a high frequency, as a reference frequency of a phase-locked loop, thereby allowing high resolution and high performance in a high frequency band. The purpose of the present invention is to provide a hybrid frequency synthesizer for significantly improving power consumption and transition speed by reducing phase complexity and chip area of the circuit.

Technical features of the present invention for achieving the above object, by accumulating a constant data input value corresponding to the frequency control signal in accordance with the system clock frequency to reference the signal of the output waveform having a constant period of the last rounded output value of the most significant bit A reference frequency generating means generated at a frequency and a reference frequency generated from the reference frequency generating means are synthesized by mixing and injecting a high frequency carrier frequency feedback and mixing to up-convert the frequency of the variable bandwidth to a desired output frequency. Phase synchronizing loop frequency synthesizing means, direct digital frequency synthesizing means for accumulating a constant data input value corresponding to a frequency control signal according to a clock frequency, performing quantization and filtering, and then outputting a desired sine wave, and the direct digital frequency synthesizing means. Frequency and local output After mixing the frequency and remixed with the output frequency feedback from the phase synchronizing loop frequency synthesizing means and the frequency mixing means for injecting the phase synchronizing loop frequency synthesizing means, the present invention is used as a carrier frequency generator loop which is a high frequency sine wave And outputting the output of another synthesizer capable of fine tuning of the variable output bandwidth to the feedback circuit so as to up-convert the output of the phase-locked loop frequency synthesizing means to fine-tune the frequency of the variable bandwidth at the desired high frequency. It is characterized by injecting.

As a result, a high frequency synthesizing function having a high speed transition speed and a wide band output of the digital conversion up-converted to a desired output is enabled.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of the present invention, in which a predetermined data input value corresponding to a frequency control signal is accumulated according to a system clock frequency so that the final rounded output value of the most significant bit has a constant period. A frequency of variable bandwidth to a desired output frequency by combining a reference frequency generator 100 generating a reference frequency with a reference frequency generated from the reference frequency generator 100 mixed with the injected high frequency carrier frequency Phase synchronous loop frequency synthesizer 200 for up-converting to fine-adjust the signal, and accumulate a predetermined data input value corresponding to the frequency control signal according to the clock frequency, perform quantization and filtering, and then output a desired sine wave. Frequency synthesizer 300, and the frequency output from the direct digital frequency synthesizer 300 After mixing the local oscillator frequency it is comprised of the phase locked loop frequency synthesizer sub-frequency mixing unit 400 for injecting the combined married with the output frequency from the feedback 200 to the phase locked loop frequency synthesizer 200.

A more detailed configuration of the above configuration is as shown in FIG.

First, the reference frequency generator 100, which is a type of oscillator, includes a first frequency input register 110 in which 24-bit binary data input values are temporarily stored as frequency control signals, and the first phase accumulator. The first output buffer 130 temporarily storing and outputting the coefficient value output through the 120, and the last digit that is the most significant bit (MBS) of the coefficient value output from the first output buffer 130 (Carry). The frequency selector 140 selects a predetermined frequency such that the value is output as an output waveform having a predetermined period (that is, a reference frequency).

In addition, the phase-locked loop frequency synthesizing unit 200 is a phase detector 210 for comparing and detecting the phase of the output signal of the reference frequency generated from the reference frequency generator 100 and the signal divided and feedback at a predetermined ratio; A first low pass filter 220 for removing a high frequency component of the signal detected by the phase detector 210 and outputting a complete sine wave, and a high frequency carrier signal corresponding to an output signal of the first low pass filter 220 The voltage controlled oscillator 230 for outputting and the output frequency fed back from the voltage controlled oscillator 230 by mixing and injecting through the frequency mixing unit 400 to divide the 1 / N program to convert the situation to the desired frequency It is composed of a muble 1 / N division unit 240.

Although the configuration of the programmable 1 / N divider 240 is briefly described with reference to FIG. 2, the present invention is applied to the present invention.

A divider 241 for dividing the oscillation frequency output from the voltage controlled oscillator 230 at a predetermined ratio, a shift register 242 for shifting M-bit data input from the outside according to an input clock, and the shift register A latch 243 latching the shifted M bit at 242 and an MN counter 244 counting data of the MN bit output through the latch 243 according to the frequency divided by the divider 241. ) And an N counter 245 that counts N bits of data output through the latch 243 according to the frequency divided by the frequency divider controller 246 and outputs the counted frequency to the phase detector 210. .

In addition, the direct digital frequency synthesizer 300 includes a second frequency input register 310 for temporarily storing a binary data input value of 24 to 32 bits as a frequency control signal, and according to a system clock frequency (not shown). A second phase accumulator 320 for counting the phase value of the output signal by adding the input binary data value and the feedback output data value, and temporarily storing the coefficient value output through the second phase accumulator 320 A sine ROM 340 of a sine lookup table that outputs a second output buffer 330 and a series of data values representing sinusoidal waveforms in response to an input of a main soot output through the second output buffer 330. And a digital-to-analog converter 350 for converting the data output from the sine ROM 340 into analog data and outputting a sine waveform that is positive, and a sine wave output from the digital-analog converter 350. castle By removing it consisting of the second low-pass filter 360, output of precise sine wave.

In addition, the detailed configuration of the frequency mixer 400 is a local oscillator (LO) 410, the sine wave output from the second low pass filter 360 and the local output from the local oscillator 410 The first frequency mixer 420 mixing the oscillation frequency, the output signal mixed by the first frequency mixer 420 and the output frequency output from the voltage controlled oscillator 230 are mixed again and the programmable 1 The second frequency mixer 430 is injected into the / N division unit 240.

The above-described mixed frequency synthesizer can be one-chip, and in particular, only the digital function unit of the phase-locked-loop frequency synthesizer 200 can be single-chip.

The phase-locked loop frequency synthesizer 200 outputs the output of the direct digital frequency synthesizer 300 to a PLL feedback loop to remove spurious noise of a phase-locked-loop (PLL) output waveform when the output frequency is upconverted. Instead of using a direct connection, it is configured to be first mixed with the oscillation frequency of the local oscillator 410 and then injected into its phase-locked loop frequency synthesizer 200.

In addition, the frequency input register 110 and the first phase accumulator 120 are input as a reference frequency of the phase locked loop frequency synthesizer 200 and used as a reference frequency generator. Digital Frequency Synthesizer).

In addition, the output of the first phase accumulator can be used as a reference frequency of other functional circuit blocks, thereby widening its use range.

Referring to the operation of the present invention configured as described above are as follows.

When the binary data value is input to the first frequency input register 110 and has a binary input of 24 to 32 bits as a frequency control signal, the input value is added according to the clock frequency in the first phase accumulator 120. do.

Accordingly, the added input value is buffered and output through the first output buffer 130.

The signal output as described above is selected by the frequency selector 140 selected in the frequency mode as an input terminal, and a desired reference frequency is output.

In this case, the reference frequency may be input to a constant frequency terminal, which is an input terminal, as shown in FIG.

Such a reference frequency can be input to the phase detector 210 of the phase-locked loop frequency synthesizer 200 to replace the function of a conventional crystal oscillator, and can be used in a variable manner, and is commonly used as a carrier frequency generator loop that is a high frequency sine wave. You can do it.

On the other hand, the reference frequency selected by the frequency selector 140 is a waveform of the final rounding, which is the most significant bit of the phase accumulator, and the waveform is as shown in (a) of FIG.

For example, if data corresponding to 2 ³ of 24 bits is input, the value of the output 24 bits of the first phase accumulator (or the second phase accumulator, reference numeral 320) is 0, 8, 16, 32, 64,- ---, increased to 16777216 (2 ²⁴ ).

Note that, in the end the carry signal is a pulse waveform frequency is ^{(2 3/2 24) *} Fclk obtained.

In addition, when inputted in a multi bit rather than a single bit, that is, when the input data is 2 ²⁰ , 2 ²¹ , the frequency of the output waveform is (2 ²⁰ +2 ^21). ) / 2 ²⁴ * Fclk

Accordingly, the spectrum of the output stage output from the phase-locked loop frequency synthesizer 200 is shown in (b) of FIG. 5, and the final synthesized output frequency is the frequency output from the phase-locked loop frequency synthesizer 200. A variable frequency band up-converted by the frequency f _PLL + f _DDFS obtained by adding the frequency f _DDFS output from the digital frequency synthesizer 300 directly to f _PLL ) is obtained.

On the other hand, the reference frequency generated from the reference frequency generator 100 is input to the phase synchronization loop frequency synthesizer 200.

Accordingly, the phase-locked loop frequency synthesizer 200 is upconverted to fine-tune the frequency of the variable bandwidth at a desired high frequency, and another synthesizer capable of fine tuning by the output bandwidth (eg, fine tuning). : It is operated so that the output of the digital frequency synthesizer 300 is directly injected into the feedback circuit.

Referring to the operation, the output signal of the voltage controlled oscillator 230 is divided into 1 / N by the programmable 1 / N divider 240 (see FIG. 2), and the divided output signal is inputted to the input signal. Since the signal of the reference frequency is detected by the phase detector 210, it is used as a coarse tuning loop for adjusting N to synthesize a desired high frequency carrier signal.

Therefore, the reference frequency can be easily changed and the frequency can be shifted within several nanoseconds (nsec).

The frequency injected into the phase locked loop frequency synthesizer 200 is directly mixed through the digital frequency synthesizer 300 and the frequency mixer 400.

Accordingly, the digital frequency synthesizer 300 and the frequency mixer 400 are mixed.

Accordingly, binary data is input to the second frequency input register 310 in the digital frequency synthesizer 300, and the binary input data is added to its output value through the second phase accumulator 320 to be added to the second frequency input register 310. Output to the output buffer 330.

Accordingly, the second output buffer 330 inputs an address bit, which is a value output from the second phase accumulator 320, to the sine rom 340, and the sine rom indicates a series of sinusoidal waveforms according to the input address bit. Print data values.

The data value thus output is converted into an analog signal by the digital-to-analog converter 350 and output as a quantized visual waveform, and then a high frequency component is removed through the second low pass filter 360 to output an accurate sine wave. .

The output signal of the output sinusoidal wave is mixed with the frequency output from the local oscillator 410 of the frequency mixer 400 through the first frequency mixer 420 and then fed back through the voltage controlled generator 230. A high frequency synthesis function having a high speed transition speed and a wideband output of the digital conversion, which is mixed again through the carrier signal and the second frequency mixer 430 and upconverted to a desired output, is possible.

As described above, the present invention uses the pulse output of the phase accumulator by the binary data input as the reference frequency of the phase-locked-loop frequency synthesizer connected in series to the rear end thereof, so that it is more flexible than the case of using only a crystal oscillator. ) And the transition speed can be increased.

The advantages and disadvantages of the direct digital frequency synthesizer, which has fast transition speed and high resolution frequency characteristics, and the new phase-locked loop frequency synthesizer that combines the advantages of phase-locked-loop frequency synthesizer with low noise and high stability broadband frequency characteristics. This makes up for wideband frequency synthesis at high frequencies.

In addition, in the frequency synthesizer of the present invention, in the conventional digital frequency synthesizer, the sine ROM and the digital-analog converter of the sine lockup table remove the low pass filter, and the spherical and pulse outputs of the phase accumulator are input to the input of the phase locked loop frequency synthesizer. By directly connecting and using, the chip area and power consumption are greatly improved, and the transition speed is also high.

In addition, in the configuration of the present invention, the output of the local oscillator and the direct digital frequency synthesizer are mixed first and then injected into the PLL feedback loop during the redundancy conversion of the output abacus number, thereby directly switching the PLL output waveform by the output of the digital frequency synthesizer. Since the bias noise can be removed, the noise characteristic can be much improved than in the conventional configuration.

The effects of the present invention as described above are as follows.

First, the pulse output of the binary input accumulator is used as the reference frequency of the phase-locked loop frequency synthesizer in the subsequent stage, so that the transition speed, frequency variability, and stability are higher than those of the conventional PLL using a pretuning circuit.

Second, when up-converting the output frequency, the output of the local oscillator and the direct digital frequency synthesizer are first mixed and filtered, and then injected into the PLL feedback loop to remove spurious noise of the PLL output waveform by the output of the direct digital frequency synthesizer. This makes it possible to improve the noise characteristics over the conventional configuration.

Third, it is a new phase-locked frequency synthesizer that combines the advantages of a direct digital frequency synthesizer with fast transition speed and high resolution frequency, and the advantages of a phase-locked loop frequency synthesizer with low noise and high stability in high frequency band. The advantages and disadvantages can be compensated for, enabling wideband frequency synthesis in the high frequency band.

In addition, it is possible to manufacture a single chip, it is possible to manufacture a small portable terminal or a high-performance signal generator of a modern new mobile communication device operating at high speed and low power.

Therefore, the present invention can greatly improve frequency resolution, stability, transition speed, etc., and can reduce the chip size and power consumption by miniaturizing by single-chip, which enables the digital mobile communication field, digital signal processing system, and computer peripheral device. It can be widely used.

Claims (6)

Reference frequency generating means for accumulating a constant data input value corresponding to a frequency control signal according to a system clock frequency to generate an output waveform signal having a constant period as a reference frequency as a reference frequency; A phase synchronizing loop frequency synthesizing means for synthesizing the mixed frequency and the injected high frequency carrier frequencies feedback from the means to up-convert the frequency of the variable bandwidth to a desired output frequency, and a frequency control signal Phase by mixing a constant data input value according to the clock frequency, quantized and filtered, and then outputting the desired sinusoidal wave, and mixing the frequency output from the direct digital frequency synthesizer and the local oscillation frequency. Synchronous Loop Frequency Synthesis And a frequency mixing means for remixing with the output frequency fed back from the stage and injecting the phase synchronizing loop frequency synthesizing means. 2. The apparatus of claim 1, wherein the reference frequency generating means comprises a first frequency input register for temporarily storing binary data input values of a predetermined bit as a frequency control signal, and the inputted binary data values according to a system clock frequency. A first phase accumulator for adding the output data value to count the phase value of the output signal, a first output buffer for temporarily storing and outputting the coefficient value output through the first phase accumulator, and the first output buffer from the first output buffer. And a frequency selector for selecting a predetermined frequency such that a final carry value, which is the most significant bit (MSB) of the output coefficient value, is output as an output waveform having a predetermined period. 2. The apparatus of claim 1, wherein the phase-locked-loop frequency synthesizing means comprises: a phase detector for comparing and detecting a phase of an output signal of a reference frequency generated from the reference frequency generating means and a signal divided and feedback at a predetermined ratio; A first low pass filter for outputting a complete sine wave by removing the high frequency components of the signal detected through the second signal; a voltage controlled oscillator for outputting a high frequency carrier signal corresponding to the output signal of the first low pass filter; And a programmable 1 / N divider for dividing the output frequency fed back from the 1 / N by up-converting to the desired frequency by mixing and injecting the output frequency through the frequency mixing means. 2. The apparatus of claim 1, wherein the direct digital frequency synthesizing means comprises: a second frequency input register in which a binary data input value of a predetermined bit is temporarily stored as a frequency control signal, and the input binary data value and feedback according to a system clock frequency. A second phase accumulator for counting the phase value of the output signal by adding the output data value, a second output buffer for temporarily storing and outputting a coefficient value output through the second phase accumulator, and a second output buffer. A sine ROM of a sine lookup table that outputs a series of data values representing a sinusoidal waveform according to the input of the address bits output through the digital signal, and a digital quantized sinusoidal waveform obtained by converting the data output from the sine ROM into analog data. The analog signal and the sinusoidal waveform output from the digital-analog converter remove high frequency components to obtain accurate sine waves. And a second low pass filter for outputting. The frequency mixing device of claim 1 or 4, wherein the frequency mixing means comprises: a local oscillator (LO), a first frequency for mixing a sine wave output from the second low pass filter and a local oscillation frequency output from the local oscillator; And a second frequency mixer in which the output signal mixed by the first frequency mixer and the output frequency output from the phase locked loop frequency synthesizing means are mixed again and injected into the programmable 1 / N division unit. Mixed frequency synthesizer characterized by. 5. The hybrid type according to claim 1 or 4, wherein the digital frequency synthesizing means replaces the reference frequency generating means and accumulates a predetermined data input value corresponding to the frequency control signal according to the clock frequency to output a desired square wave. Frequency synthesizer.