KR20010083790A - Design Technique of PLL Frequency Synthesizer with High Spectral Purity and Ultra-Fast Switching Speed - Google Patents

Abstract

PURPOSE: A method for designing PLL(Phase Locked Loop) frequency synthesizer having a high-purity frequency spectrum and switching speed is provided, which is useful for a communication system of a commercial bluetooth system and a transform of a very high speed data information and high speed frequency hopping by simultaneously satisfying a high purity frequency spectrum and a very high speed switching speed. CONSTITUTION: A frequency synthesizer of a hybrid structure mixes an open-loop composing method for driving a voltage control oscillator(VCO)(10) by a D/A(digital/analog) convertor output and a closed-loop composing method of a reference PLL(phase locked loop). A high-purity and very high speed frequency synthesizer is designed as using a relationship of a system variable(a loop filter band width and a phase margin) and a capacity parameter(a switching time, a phase noise, and maximum overshoot).

Description

Design Technique of PLL Frequency Synthesizer with High Purity Frequency Spectrum and Ultra Fast Switching Speed {Design Technique of PLL Frequency Synthesizer with High Spectral Purity and Ultra-Fast Switching Speed}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer for generating a sinusoidal signal of a desired frequency over a wide frequency band range according to a digital frequency synthesis command. The present invention relates to a high frequency synthesizer using a hybrid frequency synthesizer structure having a mixed structure of an open loop structure and a closed loop structure. The present invention relates to a frequency synthesizer design technique having a frequency spectrum and an ultrafast switching speed.

Frequency synthesizers have been studied for high speed and high purity. Recent results show an adaptive phase-locked loop that satisfies high purity and high speed simultaneously in April 2000 at Cicero S. Vaucher, IEEE Journ., Solid-State Circuit , Vol. 35, No. 4, pp. 490-502. Implemented the adaptive PLL Tuning System. It does not use an external tuning system and continuously adapts the loop parameters in a parallel double loop structure without switching loop filter components. However, this technology has a double loop applied structure to a conventional PLL system and requires a complicated internal device, and has a disadvantage in that it is not suitable for a frequency synthesizer for high-speed information transmission.

The present invention aims to design a synthesizer that can achieve frequency synthesis at a very high speed and at the same time satisfy the low spurious noise of the generated frequency spectrum, that is, high purity, through a relatively simple circuit. To achieve this goal, an open structure is achieved by controlling the voltage controlled oscillator (VCO) with a mixture of the D / A output signal obtained by applying the digital frequency synthesis command to the D / A converter and the output signal of the loop filter of the phase locked loop. Frequency synthesizer that satisfies high purity and high speed in terms of system parameters (loop filter bandwidth and phase margin) and performance parameters (settling time, spectral purity) by using a hybrid synthesizer with a hybrid structure of Design.

Figure 1a or block diagram of the whole according to the present invention

1b is a loop filter circuit diagram as an internal configuration diagram

2a, 2b, and 2c show the relationship between system variables and performance parameters.

Response speed waveform according to the 3a or frequency switching command

3b or frequency spectrum of the synthesizer output signal

※ Explanation of codes for main parts of drawing

(1) Reference input signal (8) D / A converter

(2) Phase Detectors (9) Analog Adders

(3) Charge Pump (10) Voltage Controlled Oscillator (VCO)

(4) loop filter (11) programmable counter

(5) Frequency Synthesis Command (12) Output Signal

(6) Conversion Table (13) Dividing Signal

(7) D / A converter control command

DETAILED DESCRIPTION OF THE INVENTION The detailed description of the invention is divided into one overall circuit block diagram, a graph of the relationship between performance parameters and design variables, and a waveform resulting from operating the entire circuit.

FIG. 1A is a block diagram showing the circuit configuration of the present invention and is a schematic diagram of a frequency synthesizer of a hybrid structure in which an open loop structure and a closed loop structure are mixed. FIG. 1B is a circuit diagram of the secondary passive loop filter 4 which is part of the overall circuit.

Figure 2a is a diagram showing the relationship between the loop filter bandwidth and phase noise, which is the first design step in the frequency synthesizer presented in the present invention. First, the whole system is simulated by loop filter design considering phase margin and loop filter bandwidth. The frequency spectrum of the synthesizer output signal measured when the loop filter bandwidths are 1 KHz, 5 KHz, 10 KHz, and 15 KHz has an optimal phase noise at a bandwidth of 5 KHz.

2b is a graph showing the relationship between the switching time for the loop filter bandwidth and the maximum overshoot in the second step. The maximum overshoot that occurs during the frequency switching process decreases exponentially with the loop filter bandwidth, and the switching time increases proportionally. Here, the design point with the smallest maximum overshoot and the minimum switching time is near the loop filter bandwidth of 5KHz.

2c is a graph showing the relationship between the switching time for the phase margin and the maximum overshoot in the third step. The maximum overshoot and switching time according to the phase margin have a similar relationship with each other and have an optimum performance near 45 °.

These three design techniques are as follows. In other words, ① find the optimal design point that shows the least phase noise by the system filter loop filter bandwidth. ② Find the optimal design point that meets the fast switching speed with minimum maximum overshoot through the relationship between loop filter bandwidth, switching time, and maximum overshoot. As in the second design technique, find the optimal point for the minimum maximum overshoot and fast switching speed according to the phase margin.

Figure 3a is a diagram of the switching process of the frequency synthesizer structure by the design technique. When the frequency control command 5 is issued to switch from 4 MHz to 5 MHz, the output of the synthesizer has a frequency deviation of up to 0.1% during the switching transition. This means that it becomes an ultra-fast switching characteristic that is an instant response, like a step function, which is an ideal switching process.

3B shows the frequency spectrum of the synthesizer output signal measured in the environment of FIG. 3A. The phase noise according to the offset frequency is expressed as the power difference from the center frequency. At an offset frequency of 10KHz, the phase noise is -128.15dBc.

The present invention uses a hybrid phase locked loop synthesizer that combines an open loop and a closed loop structure to satisfy both high-frequency frequency spectrum and ultra-fast switching speed by three design techniques. It will have a very useful effect on the communication information system of data information transmission and frequency hopping.

Claims (1)

In the technique of designing a phase locked loop (PLL) frequency synthesizer with a digital frequency synthesis command, A) The hybrid frequency synthesizer is a combination of an open-loop configuration that drives a voltage-controlled oscillator (VCO) with the output of a D / A converter and a closed-loop configuration of a conventional PLL. , How to design a high-purity, ultrafast frequency synthesizer using the relationship between system variables (loop filter bandwidth and phase margin) and performance parameters (switching time, phase noise, and maximum overshoot).