KR970055570A - Hybrid Frequency Synthesizer - Google Patents

Hybrid Frequency Synthesizer Download PDF

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Publication number
KR970055570A
KR970055570A KR1019950047064A KR19950047064A KR970055570A KR 970055570 A KR970055570 A KR 970055570A KR 1019950047064 A KR1019950047064 A KR 1019950047064A KR 19950047064 A KR19950047064 A KR 19950047064A KR 970055570 A KR970055570 A KR 970055570A
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South Korea
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frequency
output
phase
value
signal
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KR1019950047064A
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Korean (ko)
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KR0149126B1 (en
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김대용
김수현
한제덕
조경록
임태영
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양승택
한국전자통신연구원
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • G06F1/03Digital function generators working, at least partly, by table look-up
    • G06F1/0321Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

Abstract

본 발명은 혼합형 주파수 합성기에 관한 것으로 종래기술에서의 직접 디지탈 주파수 합성기와 위상동기루프 주파수 합성기가 소비전력이 크고 천이 속도가 낮고 회로가 복잡하며 칩면적이 컸던 문제점을 해결하기 위해 위상동기루프 주파수 합성부의 앞단에 기준주파수 발생부를 직렬로 연결하여 구형과 펄스출력을 기준주파수로 사용할 수 있도록 구성하여 고주파 정현파인 캐리어 주파수 발생기 루프로 사용한 것이고 또한 위상동기루프 주파수 합성부의 출력이 원하는 높은 주파수에서 가변 대역폭의 주파수를 미세조정할 수 있도록 상향변환시키기 위하여 가변 출력대역폭만큼의 미세조정이 가능한 또 다른 주파수 합성기의 출력을 궤환회로에 주입되도록 구성한 것이다.The present invention relates to a hybrid frequency synthesizer, and in order to solve the problems of the direct digital frequency synthesizer and the phase locked loop frequency synthesizer in the related art, which have a high power consumption, a low transition speed, a complex circuit, and a large chip area. It is used as a carrier frequency generator loop, which is a high frequency sine wave, by using the square and the pulse output as the reference frequency by connecting the reference frequency generator in series to the front of the negative part. In order to up-convert the frequency, the output of another frequency synthesizer capable of fine tuning by the variable output bandwidth is injected into the feedback circuit.

Description

혼합형 주파수 합성기Hybrid Frequency Synthesizer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 혼합형 주파수 합성기의 블럭 구성도.3 is a block diagram of a hybrid frequency synthesizer of the present invention.

Claims (6)

주파수 제어신호에 해당한 일정 데이타 입력값을 시스템 클럭주파수에 따라 누산하여 최상위비트인 최종자리올림 출력값이 일정주기를 갖는 출력파형의 신호를 기준 주파수로 발생하는 기준 주파수 발생수단과 상기 기준 주파수 발생수단으로부터 발생된 기준 주파수와 궤환되어 혼합 및 주입된 고주파 캐리어 주파수를 합성하여 원하는 출력 주파수로 가변 대역폭의 주파수를 미세 조정할 수 있도록 상향변환 시키는 위상동기루프 주파수 합성수단과 주파수 제어신호에 해당한 이정 데이타 입력값을 클럭주파수에 따라 누산하여 양자화 및 필터링을 거친후 원하는 정현파를 출력하는 직접 디지찰 주파수 합성수단과 상기 직접 디지탈 주파수 합성수단으로부터 출력된 주파수와 국부잘진 주파수를 혼합한 후 상기 위상동기루프 주파수 합성수단으로부터 궤환된 출력 주파수와 재혼합하여 상기 위상동기루프 주파수 합성수단에 주입하는 주파수 혼합수단으로 구성된 것을 특징으로 하는 혼합형 주파수 합성기.A reference frequency generating means and a reference frequency generating means for accumulating a constant data input value corresponding to a frequency control signal according to a system clock frequency to generate an output waveform signal having a constant period as a reference frequency as a reference frequency; Phase-synchronized loop frequency synthesizing means for synthesizing the mixed and injected high-frequency carrier frequencies, feedback, and frequency-adjusted frequency of variable bandwidth to the desired output frequency, and inputting the binary data corresponding to the frequency control signal. After the value is accumulated according to the clock frequency, quantized and filtered, the direct digital frequency synthesizing means for outputting a desired sinusoidal wave and the local frequency outputted from the direct digital frequency synthesizing means are mixed, and then the phase locked loop frequency synthesis is performed. By means The combined emitter married and the feedback output frequency mixing type frequency synthesizer, characterized in that configured in the frequency mixing means for injecting in the phase locked loop frequency synthesis means. 제1항에 있어서 상기 기준 주파수 발생수단은 주파수 제어신호로 소정 비트의 2진 데이타 입력값이 일시 저장되는 제1주파수 입력 레지스터와, 시스템 클럭 주파수에 따라 상기 입력된 2진 데이타값과 궤환된 출력 데이타값이 가산되어 출력신호의 위상값을 계수하는 제1위상누산기와, 상기 제1위상누산기를 통해 출력된 계수값을 일시 저장하여 출력하는 제1출력버퍼와 상기 제1출력버퍼로부터 출력된 계수값의 최상위비트(MSB)인 최종자리올림(Carry)값이 일정주기를 갖는 출력파형으로 출력되도록 일정 주파수를 선택하는 주파수 선택부로 구성된 것을 특징으로 하는 혼합형 주파수 합성기.2. The apparatus of claim 1, wherein the reference frequency generating means comprises: a first frequency input register for temporarily storing a binary data input value of a predetermined bit as a frequency control signal, and the inputted binary data value and a feedback output according to a system clock frequency; A first phase accumulator for counting phase values of the output signal by adding data values, a first output buffer for temporarily storing and outputting a coefficient value output through the first phase accumulator, and a coefficient output from the first output buffer And a frequency selector configured to select a predetermined frequency such that a final carry value, which is the most significant bit of the value, is output as an output waveform having a predetermined period. 제1항에 있어서 상기 위상동기루프 주파수 합성수단은 상기 기준 주파수 발생수단으로부터 발생된 기준 주파수의 출력신호와 소정 비율로 분주 및 궤환된 신호의 위상을 비교 검출하는 위상 검출기와, 상기 위상 검출기를 통해 검출된 신호의 고주파 성분을 제거하여 완전한 정편하를 출력하는 제1저역통과필터와 상기 제1저역통과필터의 출력신호에 상응한 고주파 캐리어신호를 출력하는 전압제어발진기와 상기 전압제어발진기로부터 궤환된 출력주파를 상기 주파수 혼합수단을 통해 혼합 및 주입하여 원하는 주파수로 상향변환시키도록 1/N 분주하는 프로그램머블 1/N 분주부로 구성된 것을 특징으로 하는 혼합형 주파수 합성기.The phase synchronizing loop frequency synthesizing means comprises: a phase detector for comparing and detecting a phase of an output signal of a reference frequency generated from the reference frequency generating means with a signal divided and fed at a predetermined ratio; A voltage controlled oscillator and a voltage controlled oscillator for outputting a high frequency carrier signal corresponding to the output signal of the first low pass filter and the first low pass filter for removing the high frequency components of the detected signal And a programmable 1 / N divider for dividing the output frequency through the frequency mixing means to up-convert to the desired frequency. 제1항에 있어서 상기 직접 디지탈 주파수 합성수단은 주파수 제어신호로 소정 비트의 2진 데이타 입력값이 일시 저장되는 제2주파수 입력 레지스터와 시스템클럭 주파수에 따라 상기 입력된 2진 데이타값과 궤환된 출력 데이타값이 가산되어 출력신호의 위상값을 계수하는 제2위상누산기와, 상기 제2위상누산기를 통해 출력된 계수값을 일시 저장하여 출력하는 제2출력버퍼와 상기 제2출력버퍼를 통해 출력된 주소비트의 입력에 따라 정형파형을 나타내는 일련의 데이타값을 출력하는 사인 룩 업테이블의 사인롬과 상기 사인 롬에서 출력되는 데이타를 아날로그 데이타로 변환하여 양자화된 사인파형을 출력하는 디지탈-아날로그 변환기와 상기 디지탈 -아날로그 변환기에서 출력되는 사인파형에서 고주파 성분을 제거하여 정확한 정현파를 출력하는 제2저역통과필터로 구성된 것을 특징으로 하는 혼합형 주파수 합성기.2. The direct digital frequency synthesizing means according to claim 1, wherein the direct digital frequency synthesizing means comprises a second frequency input register in which a binary data input value of a predetermined bit is temporarily stored as a frequency control signal and the inputted binary data value according to a system clock frequency. A second phase accumulator for adding the data value to count the phase value of the output signal, a second output buffer for temporarily storing and outputting the coefficient value output through the second phase accumulator, and outputting the second output buffer. A sine ROM of a sine lookup table that outputs a series of data values representing a square waveform according to an input of an address bit; To remove the high frequency components from the sine wave output from the digital-analog converter to output an accurate sine wave Mixed frequency synthesizer according to claim 2 consisting of the low-pass filter. 제1항 또는 제4항에 있어서 상기 주파수 혼합수단은 국부발진기(LO)와 상기 제2저역통과필터로부터 출력된 정현파와 상기 구부 발진기로부터 출력된 국부발진주파수를 혼합하는 제1주파수 혼합기와 상기 제1주파수 혼합기에서 혼합된 출력신호와 상기 위상 동기루프 주파수 합성수단에서 출력되어 궤환된 출력주파수를 다시 혼합하여 상기 프로그램머블 1/N 분주부에 주입하는 제2주파수 혼합기로 구성된 것을 특징으로 하는 혼합형 주파수 합성기.The first frequency mixer and the first frequency mixer of claim 1 or 4, wherein the frequency mixing means mixes a local oscillation frequency output from the local oscillator LO and the second low pass filter and the local oscillation frequency output from the spherical oscillator. A mixed frequency comprising a second frequency mixer in which the output signal mixed by the first frequency mixer and the output frequency output by the phase-locked loop frequency synthesizing means are mixed again and injected into the programmable 1 / N division unit; Synthesizer. 제1항에 있어서 상기 기준 주파수 발생수단은 자신에게서 출력된 기준 주파수를 동시에 상기 직접 디지탈 주파수 합성수단에 입력하는 것을 특징으로 하는 혼합형 주파수 합성기.The mixed frequency synthesizer according to claim 1, wherein the reference frequency generating means inputs the reference frequency output from the same into the direct digital frequency synthesizing means at the same time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047064A 1995-12-06 1995-12-06 Mixed type frequency synthesizer KR0149126B1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010069612A (en) * 2001-04-20 2001-07-25 유흥균 Design Technology of Ultra-fast Digital Hybrid Frequency Synthesizer
KR20010083790A (en) * 2001-06-26 2001-09-03 유흥균 Design Technique of PLL Frequency Synthesizer with High Spectral Purity and Ultra-Fast Switching Speed
US8731126B2 (en) 2009-11-16 2014-05-20 Electronics And Telecommunications Research Institute Phase locked loop and satellite communication terminal using the same
KR101437404B1 (en) * 2013-02-21 2014-09-15 주식회사 한화 Apparatus and Method for frequency synthesizer
CN112087230A (en) * 2020-09-17 2020-12-15 中国科学院空天信息创新研究院 Broadband linear frequency modulation signal generating device and method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100677073B1 (en) * 1999-10-26 2007-02-01 삼성전자주식회사 Apparatus for digital timing recovery
KR20020087024A (en) * 2002-10-09 2002-11-21 유흥균 Apparatus and Design Method of the Ultra-High Speed Fractional-N Type Digital Hybrid Frequency Synthesizer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010069612A (en) * 2001-04-20 2001-07-25 유흥균 Design Technology of Ultra-fast Digital Hybrid Frequency Synthesizer
KR20010083790A (en) * 2001-06-26 2001-09-03 유흥균 Design Technique of PLL Frequency Synthesizer with High Spectral Purity and Ultra-Fast Switching Speed
US8731126B2 (en) 2009-11-16 2014-05-20 Electronics And Telecommunications Research Institute Phase locked loop and satellite communication terminal using the same
KR101437404B1 (en) * 2013-02-21 2014-09-15 주식회사 한화 Apparatus and Method for frequency synthesizer
CN112087230A (en) * 2020-09-17 2020-12-15 中国科学院空天信息创新研究院 Broadband linear frequency modulation signal generating device and method

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