KR20020087024A - Apparatus and Design Method of the Ultra-High Speed Fractional-N Type Digital Hybrid Frequency Synthesizer - Google Patents

Abstract

PURPOSE: A method and an apparatus for designing a high speed fractional-N digital hybrid frequency synthesizer are provided, which can replace a complex digital look-up table(DLT) realized with a ROM(Read Only Memory) with a simple digital circuit. CONSTITUTION: According to the digital hybrid frequency synthesizer method, an open loop where a digital frequency synthesis command is applied directly to a voltage controlled oscillator(VCO)(5) through a ROM and a DAC(Digital Analog Converter)(9) is mixed to a phase locked loop(PLL) circuit, for a high speed frequency synthesis. According to the method, the digital look-up table realized with the ROM having a transfer characteristics of the voltage controlled oscillator is replaced, and thus a difference value between the frequency synthesis command in the previous state and a newly inputted frequency synthesis command is used. A timing synchronization is achieved using an auxiliary signal synchronized to a reference input signal, to be synchronized to the reference frequency at every new frequency synthesis command inputted to a programmable divider of the PLL and the digital look-up table or the circuit replacing the digital look-up table.

Description

Apparatus and Design Method of the Ultra-High Speed Fractional-N Type Digital Hybrid Frequency Synthesizer}

Conventional representative frequency synthesizer is using a phase locked loop (PLL). As a closed loop, it is the most widely used method and has the best price, variety, and flexibility. In addition, spurious noise is relatively low compared to other methods. However, the switching speed is low due to the closed structure.

Closed-type frequency synthesizers generally include integer-type and fractional-N type frequency synthesizers. The integer frequency synthesizer is a structure in which the output frequency is output as an integer multiple of the reference frequency, and the fractional structure is a structure that can be synthesized not only as an integer but also as a fraction multiple. Therefore, compared to the integer structure, the fractional structure can use a higher reference frequency, the comparison time of the phase comparator is shorter, the settling time is shorter, and the division ratio is lowered for the same output frequency, thereby improving the phase noise. do. However, there is a disadvantage in that the settling time is long in proportion to the presence of severe spurious due to the periodic change of the division ratio and the frequency synthesis interval.

On the other hand, high frequency frequency synthesis is performed using a digital hybrid frequency synthesizer method in which an open loop that directly applies a digital frequency synthesis command to a voltage controlled oscillator (VCO) is mixed with an existing closed structure. . The frequency synthesis instruction is applied to the counter and digital look-up table of the existing PLL. When the output of the digital lookup table is applied to a digital-to analog converter (DAC), the voltage corresponding to the synthesis command is added to the voltage of the loop filter to drive the voltage controlled oscillator. The digital lookup table is a ROM structure that stores information on voltage vs. frequency relationship of a voltage controlled oscillator. Thus, the frequency synthesizer command becomes the voltage information according to the digital lookup table, and is outputted to the desired voltage by the DAC. Therefore, switching is possible at high speed whenever a new synthesis command is input. However, this structure alone has a limitation in switching speed, and even though the loop filter parameters are optimized, there is a trade-off between phase noise and settling time, making it difficult to achieve perfect ultrafast switching. In addition, since the digital lookup table is a ROM structure, there are various problems in that hardware complexity increases with the constraint that the initial dispensing instruction must be the same.

According to the present invention, in the aforementioned digital hybrid frequency synthesizer method, 1) overcoming the tradeoff between frequency synthesis speed and phase noise, 2) solving the problem of settling time in proportion to the frequency synthesis interval, and 3) actual digital Design a digital replacement circuit that simplifies the complexity of ROM, a lookup table, and 4) Design a timing synchronization circuit that matches the phase error of the operation occurring during the frequency synthesis command. The present invention relates to a frequency synthesizer design method and apparatus configuration.

First, in order to overcome the limitation of speed, the tradeoff between phase noise and settling time due to the loop filter band should be eliminated. That is, an auxiliary signal synchronized with the reference input signal is used to remove the phase error occurring at the time of change of the frequency synthesis command. In addition, the present invention relates to a simple digital circuit design that calculates a difference between a frequency synthesis instruction of a previous state and a newly input frequency synthesis instruction in place of a digital lookup table implemented in a complex ROM form.

1 is a block diagram of a full digital hybrid frequency synthesizer block

FIG. 2 shows a tertiary sigma-delta-modulator (SDM) structure

FIG. 3 shows a primary sigma-delta-modulator (SDM) structure

4 is an Nf divider configuration diagram

5 is a digital circuit diagram replacing the DLT

6 is a timing synchronization block diagram

7 is a signal waveform that is problematic at the time of frequency change

8 shows the voltage controlled oscillator (VCO) input voltage waveform of the frequency synthesis process.

9 is the frequency spectrum waveform of the output of the frequency synthesis process

※ Explanation of the code about the main part of FIG.

(1) reference frequency (10) DLT replacement block

(2) phase detector (11) checker output

(3) charge pump (12) DAC control signal

(4) loop filter (13) Nf divider

(5) voltage controlled oscillator (VCO) (14) divided signal

(6) Output Frequency (15) 3rd SDM

(7) Timing Synchronization Block (16) 3rd SDM Output

(8) Timing synchronization block output (17) Frequency synthesis instruction (fractional part)

(9) DAC (digital-analog converter) (18) Frequency synthesis instruction (integer part)

※ Explanation of codes for main parts of Figure 2

(16) 3rd SDM Output (20) Carry Output of Primary SDM

(17) Frequency synthesis instruction (fractional part) (21) 4-bit D-flip flop

(19) Primary SDM

※ Explanation of the code about the main part of FIG.

(17) Frequency synthesis command (fractional part) (23) Primary SDM output

(20) Carry Output of Primary SDM (24) k-bit D-Flip-Flop

(22) 1-bit full adder

※ Explanation of codes for main parts of Figure 4

(6) Output frequency (18) Frequency synthesis command (integer part)

(14) Divided Signal (25) Programmable Divider

(16) 3rd SDM Output

※ Explanation of the code about the main part of FIG.

(11) Checker output (18) Frequency synthesis command (integer part)

(12) DAC control signal (26) D-flip flop

(17) Frequency synthesis instruction (fractional part) (27) checker

※ Explanation of the code about the main part of FIG.

(1) Reference frequency (28) 1 bit D-flip flop

(8) Timing synchronization block output (29) Duty ratio converter

(11) checker output (30) 2: 1 multiplexer (MUX)

(14) divided signals

DETAILED DESCRIPTION OF THE INVENTION The detailed description of the present invention is composed of circuit block diagram drawings (first, second, third, fourth, fifth, and sixth) and waveforms (the seventh, eighth, and nineth) resulting from operating the circuit.

1 is an overall system block diagram of the present invention, in which a closed loop structure, a phase locked loop (PLL), and an open structure for directly driving a voltage controlled oscillator (VCO) through a ROM and a DAC are combined. will be. 2 is a block diagram of a third-order sigma-delta modulator (SDM) used in a conventional fractional frequency synthesizer. 3 is an internal block diagram of the primary SDM used in the tertiary SDM. It functions like an accumulator (ACC). Figure 4 is an Nf divider, which is a programmable divider with an average divider fraction. 5 is a block diagram of a digital lookup table. 6 is a synchronization block diagram for removing a phase error occurring when a frequency synthesizing command changes. 7 is a signal waveform when the timing synchronization block of FIG. 6 is not used. 8 is a comparison of the input voltage of the VCO using the same frequency synthesis command and the fractional frequency synthesizer using the existing third-order SDM. FIG. 9 compares the frequency spectrum of the output signal after fixing in FIG.

(1) of FIG. 1 is a reference frequency of the frequency synthesizer generated by the oscillator. (2) is a phase detector, and in the present invention, a '3-state frequency phase detector' was used. (2) calculates the phase difference between two digital input signals and transfers the UP or Down signal to the charge pump (3), and (3) makes the output signal of (2) into one signal. It is composed of Complementary Metal Oxide Semiconductor (CMOS). (4) is a loop filter composed of analog passive elements and is a second low pass filter composed of a resistor (R) and a capacitor (C). (5) is a voltage controlled oscillator whose output frequency is determined by an input voltage value. The two voltage values of the loop filter 4 and the DAC 9 are added by an analog voltage adder using an operational amplifier OP-AMP to control the VCO 5 to produce the final output frequency 6.

The frequency synthesis command is input divided into an integer portion 18 N and a fractional portion 17 K. The final output frequency (6) of the fractional frequency synthesizer is given by equation (1).

In equation (1), f _OUT is the final output frequency (6), f _REF is the reference frequency (1), N is the integer part (18) of the frequency synthesis command, K is the fractional part (17), and k is the K ' The digital word length. First, K, which is the fractional part 17 of the frequency synthesizing instruction, is input to the third-order SDM 15 so that for each rising edge of the Nf divider output 14, {-3, -2,... , 3, 4} randomly outputs a value. In the Nf divider 13, f means K / 2 ^k . The output 16 of the tertiary SDM is input to the Nf divider 13 and added to the integer portion 18 of the frequency synthesis instruction so that {N-3, N-2,... , N + 3, N + 4} is input to the programmable divider 25. In addition, the frequency synthesizing instructions 17 and 18 are inputted to the block 10 replacing the ROM-type DLT to calculate a difference value between the current state and the previous state to obtain a digital value 12 to control the DAC 9. The output 11 of the checker 27 for detecting the change of the frequency synthesizing command is input to the timing synchronization circuit. The timing synchronizing block 7 transmits the signal 14 divided by the Nf divider 13 to the phase comparator 2 in a period where the frequency synthesizing instructions 17 and 18 do not change, and causes the frequency synthesizing instruction to change. When the signal is forcibly synchronized to the reference frequency 1, the signal is transmitted to the phase comparator 2 and the counter register of the Nf divider 13 is initialized. The DLT replacement block 10 and the DAC 9 generate an additional voltage required for the VCO driving voltage in proportion to the change value of the frequency synthesizing instructions 17 and 18. In addition, a faster switching operation characteristic can be obtained by the timing synchronization block 7 forcing the phase of the reference frequency 1 and the divided signal 14 to be forced at the time when the frequency synthesizing command changes.

2 is an internal configuration diagram of the tertiary SDM 15 of FIG. When the fractional part 17 of the frequency synthesizing command is input, the fractional part 17 of the frequency synthesizing command changes randomly while maintaining the average division ratio (.f). The first SDM 19 of FIG. 3 is connected in series to accumulate quantization errors, and the 4-bit D flip-flop 21 is used for one cycle delay. For each rising edge of the input clock, the output 16 randomly outputs a value of {-3 to +4} to maintain an average value.

3 is an internal configuration diagram of the primary SDM 19 used in FIG. A k-bit full adder 22 and a k-bit D flip-flop 24 are provided. The primary SDM performs the same function as the accumulator. When the accumulated value larger than 2 ^K is the overflow occurs carry output 20 is the HIGH state.

4 is an internal configuration diagram of the Nf divider 13 used in FIG. The output signal 6 of the VCO 5 is input to the programmable divider 25, and the division ratio is a value obtained by adding the output 16 of the tertiary SDM and the integer portion 18 of the frequency combining instruction. The divided signal 14 is input to the clock of the tertiary SDM 15 and also to the timing synchronization block.

5 is a diagram illustrating an internal configuration of the DLT replacement block 10 of FIG. It replaces the existing ROM-type digital lookup table and transfers the change detection signal 11 of the frequency synthesizing instructions 17 and 18 to the timing synchronization block 7 by the checker 27 configured as the XOR gate. The preceding D-flip-flop 26 transmits the current frequency synthesis command 17, 18 as a digital subtraction example when the output of the checker 27 is turned on. The digital adder adds the current frequency synthesis command (17, 18) and the value (12) delivered to the current DAC, and another D-flip-flop (26) subtracts the frequency synthesis command of the previous state from the digital adder's output To the DAC (9). When this D-flip-flop is also turned on by the checker 27, the output of the digital subtractor is transmitted to the DAC 9. That is, the block of FIG. 5 accumulates the difference between the frequency synthesis command of the previous state and the current frequency synthesis command. Thus, the DAC 9 outputs a DC voltage corresponding to the accumulated value of the variation amount of the frequency synthesizing command.

6 is an internal configuration diagram of the timing synchronization block 7 of FIG. The reference frequency 1 is changed by the duty ratio converter 29 at the same ratio as the signal actually divided at 50%. When the frequency synthesizing instructions 17 and 18 change, the 'select' terminal of the 2-1 multiplexer 30 becomes HIGH by the 1-bit D flip-flop 28 in which the detection signal 11 is input to the 'preset' terminal. Outputs 'X1'. That is, instead of transmitting the divided signal 14 to the phase detector 2, a signal synchronized with the reference frequency 1 by the duty ratio converter 29 is transmitted to the phase detector 2 to be forcibly synchronized. Also, in the situation where the frequency synthesizing instruction does not change, the output of the D-flip flop 28 becomes LOW, and the Mux 30 outputs the output 14 of the Nf divider 13 of 'X0' to the phase detector 2. To pass.

The frequency synthesizer of the present invention combines the fast switching characteristics of a fractional frequency synthesizer and an open loop synthesizer based on the stability of a conventional phase locked loop (PLL).

When the steady state is reached by the initial frequency synthesis command, the voltage of the loop filter actually increases or decreases slightly, but no longer changes. This is because the voltage required in the process of changing the frequency synthesis command is provided by the auxiliary voltage provided by the DAC. To generate this auxiliary voltage, an appropriate digital word value must be applied to the DAC. In the conventional hybrid frequency synthesizer, there was a constraint that the original frequency synthesis command should always be the same using a ROM-type digital lookup table in which the voltage-to-frequency characteristics of the voltage controlled oscillator (VCO) are stored. A new structure such as 5 degrees is used to calculate the DAC input values. The synchronization block is used to remove the phase error that occurs when the frequency synthesis command changes. This synchronization block is used to get a shorter settling time. That is, the phase error occurs because the internal counter of the programmable divider maintains and counts the value before the change even when the frequency synthesis instruction changes. Therefore, the synchronization block initializes the counter of the programmable divider when the frequency synthesizing instruction changes to suppress the occurrence of phase error. Computer simulations were performed to show the operating characteristics of the frequency synthesizer of the present invention. Experimental conditions include a reference frequency of 500kHz, a voltage-controlled oscillator gain of 5MHz / V, a phase detector gain of 1mA / 2π, a loop filter band of 3kHz, and a third-order SDM with 12 bits of input.

7 shows waveforms of computer simulation results in the absence of a timing synchronization block. 'Vout' in the figure is a digitized signal of the output of the VCO (5), 'Nf' is the instantaneous division ratio input to the programmable divider 25, 'Vfb' is a phase detector (7) in the timing synchronization block (7) The signal input to 2), 'Vref' is the reference frequency (1). The frequency synthesizing command changed from 25.0002441 to 36.0002685. As shown in the figure, the instantaneous frequency division ratio changed from '23' to '34' as the input of the new frequency synthesizing command. Instantaneous frequency division ratio was inputted '34' by frequency synthesizing command, and it additionally counted 22 times. As a result, the phase error occurs out of the synchronization point with the reference frequency. That is, even though the additional voltage required for the new frequency synthesizing command is applied to the VCO input terminal by the DLT replacement circuit, it is out of the normal state and the time to reach the steady state is lengthened. As a result, it can be seen that the timing synchronization block of FIG. 6 is required. Table 1 shows the frequency synthesis process for computer simulation.

8 is a VCO driving voltage waveform obtained by computer simulation. The figure above shows the conventional fractional frequency synthesizer using 3rd-order SDM and it takes time to settle in proportion to the frequency synthesis interval. However, the lower figure shows a fixed settling time regardless of the frequency synthesis interval using the circuit of Figure 1. Table 2 compares the performance of the existing and new structures obtained from the frequency synthesis results of Table 1. The settling time was measured in a range that allowed a voltage ripple within 3 kHz of the VCO driving voltage. The existing structure shows a very large difference in proportion to the frequency synthesis interval, but the proposed structure is almost constant. However, additional DLT replacement blocks, timing synchronization blocks, and DACs have increased circuit complexity.

FIG. 9 is a FFT (fast Fourier transform) result of the output frequency in the settling time interval of FIG. The upper waveform uses the existing structure, and the lower waveform is the new structure. The results of the two structures are identical because the frequency synthesizer of the new structure is a form of adding other functions without changing the existing structure. In a typical PLL, the settling time and phase noise, which are changed by the loop filter band, have a mutually opposite relationship, but the new structure can reduce the settling time without deteriorating the phase noise.

The frequency synthesizer of the present invention can be widely used in communication, electronics, medical, circuits, instruments, and the like, which require high-speed frequency synthesis. In particular, it can be widely used in the field of high speed signal generator and high speed information communication in which frequency hopping is applied in the communication or electronics industry. And it will be very useful as the most important device in the high-speed frequency hopping spreading system typical for military communication to withstand radio interference.

Claims (1)

For ultra-high frequency synthesis, an open loop that applies a digital frequency synthesis command directly to a voltage controlled oscillator (VCO) via ROM and DAC is a conventional closed structure phase acquisition circuit (PLL) In a digital hybrid frequency synthesizer scheme mixed in a locked loop, (A) A circuit design method that replaces a digital look-up table (DLT) implemented as a read-only memory (ROM) that retains the transfer characteristics of a voltage controlled oscillator (VCO). Method and apparatus for designing digital circuit using difference value between frequency synthesis command and newly inputted frequency synthesis command B) Synchronize with the reference frequency whenever a new frequency synthesis command is input to the programmable divider of the phase locked loop (PLL) and the digital look-up table (DLT) circuit, or the digital look-up table replacement circuit. And a timing synchronization by using an auxiliary signal synchronized with a reference input signal.