JPH07170180A - Dds circuit and frequency synthesizer using it - Google Patents

Abstract

PURPOSE:To obtain a synthesizer having an output frequency with a high frequency purity, an excellent frequency generating capability and a frequency switching capability by providing a phase comparator means, a loop filter and a voltage controlled oscillator means to the DDS circuit. CONSTITUTION:An address generating means 7 of a DDS (direct digital synthesizer) circuit 1 generates an address based on a DDS reference frequency EREF from an oscillation means 2 and a read condition outputted from a condition output means 5. Then the means 7 accesses a storage means 6 and read waveform data are outputted via a D/A converter means 8. A phase comparator means 10 receives an output of the means 8 and a DDS output frequency FDDS to provide an output of a phase difference signal and a loop filter 11 outputs a control signal resulting from integrating the phase difference signal. In this case, a floor noise is eliminated by the integration. Thus, an output frequency with high frequency purity is obtained from a VCO 12 and a high frequency generating capability is also obtained by controlling the read condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a DDS which outputs a desired frequency by accessing a memory storing waveform data.
(Direct Digital Synthesizer) circuit and frequency synthesizer using it. In this specification, DDS (Direct Digital Synthesiser)
The circuit is simply referred to as a DDS circuit.

[0002]

2. Description of the Related Art As a conventional general DDS circuit, as disclosed in Japanese Patent Laid-Open No. 143716/1990, waveform data is stored in a memory and a DDS setting which is a condition for accessing this memory is set. In response to the signal, in synchronization with the clock frequency from the clock oscillator, the memory is accessed to read the waveform data, and the waveform data read from the memory is converted into an analog signal by a D / A converter, Further, there is one configured to output through a low pass filter. JP-A-2
JP-A-143716 discloses that the above-mentioned general DDS circuit is provided with a tracking filter that is linked to the output frequency of the DDS circuit to attenuate unnecessary frequency components in the used band and output only the target output frequency. A configuration is disclosed. Further, in Japanese Patent Laid-Open No. 63-296522, the output from the DDS circuit is used as the reference frequency of the PLL circuit, the output from the PLL circuit is guided to a frequency divider connected in multiple stages, and the frequency division of a desired stage is performed by a multiplexer. It is disclosed that the output is configured to be taken out. Further, the applicant has disclosed in Japanese Patent Laid-Open No. 1-151824 that the output from the DDS circuit is used as the reference frequency of the PLL circuit and the waveform data read address in the DDS circuit is changed or the DDS circuit and the PLL are combined.
It was shown that excellent frequency generation ability and frequency switching ability can be obtained by changing the pass frequency of the filter provided between the circuit and the circuit.

[0003]

However, the conventional DD
In the S circuit, there is a problem that an unnecessary wave component other than the desired frequency is generated, and the presence of such an unnecessary frequency component lowers the frequency purity of the generated output frequency.

The main unnecessary frequency components generated in the DDS circuit include a clock frequency component of the DDS circuit, a harmonic component, and the like, and an image component due to these components. These unnecessary frequency components are higher than the cutoff frequency of the low-pass filter of the DDS circuit and can be amplitude-limited.

Besides the unnecessary frequency component higher than the cutoff frequency of the low-pass filter provided in the DDS circuit, there is an unnecessary frequency component called floor noise in the pass band of the low-pass filter. This floor noise is not generated in the entire output frequency band, but is generated at a specific output frequency due to the relationship between the output frequency, the clock frequency, the DDS setting signal, etc., and the waveform data is stored. Whether or not the address is generated depends on how the address to the memory is traced. In addition, the generated frequency may be in a used frequency band that affects the output frequency, or may be outside the used frequency band and may not affect the output frequency.

That is, depending on the DDS setting signal for reading the waveform data from the memory, the same address may be traced at a constant cycle. In this case, an unnecessary frequency component does not occur and the same address is traced at a constant cycle. If there is not, an unnecessary frequency component is generated. And
Even if an unnecessary frequency component is generated, it has an effect if it is within the used frequency band, but has no effect if it is outside the used band.

[0007] Below, by giving concrete numbers, the generation states of various unnecessary frequency components in the DDS circuit will be examined. If the output frequency of the DDS circuit is Fdds, the clock frequency input to the DDS circuit is Fclk, the DDS setting signal is K, and the number of memory addresses is N, then Fdds = K / N × Fclk.

Here, Fdds = 5 MHz, Fclk = 30 M
If HHz, N = 2 ⁴⁰ and the frequency band used is 20 kHz, then from Fdds = K / N × Fclk, 2 ⁴⁰ / K = Fclk / Fdds = 30 MHz / 5 MHz = 6.

In other words, six address data are read out for one cycle of the output frequency Fdds, and the same address is repeatedly traced in the same state for every six data. In this way, high-order frequency components other than the frequency (5 MHz) obtained by repeatedly tracing the six address data are also generated as unnecessary frequency components, but such high-order frequency components can be removed by the low-pass filter, which has an effect. There is no. In such a case (5 MHz), the same address is traced every constant cycle (one cycle) of the output frequency, so that an unnecessary frequency component that affects the target output frequency does not occur.

Next, when the output frequency is changed to Fdds = 4 MHz, 2 ⁴⁰ / K = Fclk / Fdds = 30 MHz / 4 MHz = 7.5, and 7.5 pieces of data are output for one cycle of the output frequency. This means that the same address is not read every cycle.

At this time, since 7.5 pieces of data are read at 30 MHz, the cycle is 7.5 × 1/30 (μS), and the repetition frequency for one cycle is 1 / (7.5 × 1/30) = 4 (MHz). , The desired output frequency, the difference between the repetition frequency that traces the same address at a constant cycle and the cycle that traces the same address is multiplied by | 5-4 | × 1 = 1 (MHz) Points (3MHz and 5MHz)
Then, the first floor noise is generated. However, since the first floor noise is outside the used band of 20 kHz, it does not affect the desired frequency.

At this time, 7.5 pieces of data are read for one cycle of the output frequency, so that the same address is not traced for each cycle, but for every two cycles,
7.5 × 2 = 15 and follow the same address. At this time, the repetition frequency that follows the same address is 1 / (15 × 1/30) = 2 (MHz). In this case, since the same address is followed for two cycles of the DDS output frequency Fdds, this repetition frequency (2 MHz) is generated as the second unnecessary frequency component in the same manner as above. This also does not affect the desired frequency because it is outside the used band of 20 kHz.

Thus, the output frequencies are 5 MHz and 4M.
In the case of Hz, the unnecessary frequency component did not affect the output frequency, but such an example is rare, and in many cases, the same address is not traced and the unnecessary frequency component is output. Occurs at points that affect the frequency. Also, the change pitch of the output frequency is 5MHz and 4M
It is not as wide as 1 MHz like the example of Hz, and it is required to change at a narrow pitch of at least about 1 kHz.

Therefore, by changing the output frequency by 500 Hz,
When set to 4.0005MHz, 30 / 4.0005 ≈ 7.499062617, which is about 7.499062617 for one cycle of output frequency.
This means that individual pieces of data will be read, and the same address will not be traced for each cycle. However, the first floor noise generated thereby does not affect the output frequency because it occurs outside the used frequency band. Therefore, the second floor noise will be described. The repetition frequency for two cycles is 1 / (2 × 7.499062617 / 30) ≈ 2.000250 (MHz), and the same address is traced to the difference between the desired output frequency and the repetition frequency that traces the same address in a fixed cycle. The second floor noise is generated at points vertically separated by | 2-2.000250 | × 2 = 0.000500 (MHz) = 500 (Hz). This second floor noise is
Since it is in the band of kHz, it affects the desired frequency.

Next, when the output frequency is further finely changed by 1 Hz to 4.000001 MHz, 30 / 4.000001≈7.499998125, which is about 7.499998125 for one cycle of the output frequency.
This means that individual pieces of data will be read, and the same address will not be traced for each cycle. However, the first floor noise generated thereby does not affect the output frequency because it occurs outside the used frequency band. Therefore, the second floor noise will be described. The repetition frequency for 2 cycles is 1 / (2 × 7.499998125 / 30) ≒ 2.000005 (MHz), and the same address is traced to the difference between the desired output frequency and the repetition frequency that traces the same address in a fixed cycle. The second floor noise is generated at points vertically separated by | 2-2.000005 | × 2 = 0.000010 (MHz) = 10 (Hz). This second floor noise is in the band of the used frequency band of 20 kHz and therefore affects the output frequency.

As described above, as the output frequency is changed with a fine pitch, the frequency of the floor noise generated becomes closer to the output frequency, so that it cannot be removed by a low-pass filter or the like and affects the output frequency. is there.

When the output frequency is set to 5.0005 MHz, it is natural that the first unnecessary frequency component, which is generated due to the difference from the repetition frequency that follows the same address in one cycle, affects the output frequency. As described above, the unnecessary frequency components generated in the frequency band to be used are
It could not be removed with the S circuit.

Then, in the frequency synthesizer configured to use the output frequency of the conventional DDS circuit as the reference frequency of the PLL circuit, if the frequency division ratio in the PLL circuit is M, the PLL output frequency output from the PLL circuit. Is M times the reference frequency, so by the theorem of multiplication and division,
The floor noise level also increases M times. That is, depending on the value of M, the unnecessary frequency component has a very strong level and affects the PLL output frequency. That is,
The problem arises that the frequency purity of the output frequency decreases. Further, in the output frequency synthesizer having such a configuration, the reference frequency of the PLL circuit output from the DDS circuit is increased to increase the actual switching speed of the output frequency when the condition for designating the output frequency is changed. In other words, if we try to obtain a high frequency switching capability by shortening the time until the PLL system stabilizes,
In some cases, the pitch of the PLL output frequencies that can be generated becomes large and the desired output frequency cannot be obtained. That is, there arises a problem that the frequency generation capability is reduced.

This point will be briefly described below. PLL
The output frequency of the circuit, that is, the PLL output frequency Fout becomes Fout = M × Fdds when the frequency division ratio is M. Therefore, as the reference frequency Fdds increases,
It is clear that the pitch of the PLL output frequency Fout becomes large and the frequency generation capability is reduced.

As a method of reducing the floor noise generated from the DDS circuit, there is a method of increasing the quantization number of the storage means for storing the waveform data and increasing the number of bits of the D / A converter. Such a storage means and a D / A converter are very expensive, and even if the number of bits of the D / A converter is increased, the DD
If the clock frequency supplied to the S circuit cannot be increased,
There was a problem that the conversion speed was very slow. Furthermore,
It was very difficult to completely remove the generated floor noise so as not to affect the PLL output frequency at all. According to Japanese Patent Laid-Open No. 2-143716,
The configuration with the tracking filter linked to the output frequency can attenuate unnecessary frequency components that are far from the target output frequency, but cannot sufficiently attenuate unnecessary frequency components that are close to the target output frequency. At the same time, there is a problem that the circuit configuration becomes complicated. Further, according to the technique disclosed in Japanese Patent Laid-Open No. 63-296522, there is a problem that it is not versatile because it requires a multistage frequency divider and a multistage multiplexer that are guaranteed to operate at a high frequency. Also, Japanese Patent Laid-Open No. 1-15181
According to Japanese Patent Laid-Open No. 24, it is true that excellent frequency generation ability and frequency switching ability can be obtained. However, in recent communication technology, high frequency purity and higher frequency generation ability and frequency switching ability are required. It has come to be required over a wide frequency range. From this point of view, there has been a demand for a technique capable of improving the frequency purity of the frequency synthesizer disclosed in JP-A-1-151824 and obtaining an excellent frequency switching ability even in a relatively low frequency band.

In view of the above problems, the present invention provides
Provided is a DDS circuit having an output frequency with high frequency purity, and by using this DDS circuit, a local part such as a wireless communication device having an output frequency with high frequency purity and excellent frequency generation ability and frequency switching ability. The purpose of the invention is to provide an ideal frequency synthesizer as an oscillator.

[0022]

DISCLOSURE OF THE INVENTION DD according to claim 1 of the present invention
The S circuit outputs a condition output unit that outputs a read condition based on a condition control signal from the outside, a storage unit that stores the waveform data, and a waveform data from the storage unit according to the DDS reference frequency and the read condition. Address generating means for generating an address to be read, D / A converting means for converting the read waveform data into an analog signal and outputting the analog signal, and phase comparing means for receiving the analog signal and a DDS output frequency described later. A loop filter which receives a phase difference signal from the phase comparison means and outputs a control voltage, and a voltage controlled oscillation means which oscillates a DDS output frequency based on the control voltage.

The frequency synthesizer of claim 2 is
A DDS circuit according to claim 1, a phase comparison means to which a DDS output frequency and an output of a frequency division means to be described later are inputted, and a loop filter which receives a phase difference signal from the phase comparison means and outputs a control voltage. , PL based on the control voltage
Voltage controlled oscillator for oscillating L output frequency, and P
The PLL circuit is provided with a frequency dividing means for dividing and outputting the LL output frequency at a frequency division ratio according to the frequency division control signal, and during a predetermined time after an external output frequency switching command is input, Controlling the condition output means to output a condition control signal for increasing the DDS output frequency, and controlling the frequency dividing means to output a frequency division control signal for increasing the frequency division ratio,
After a predetermined time, the frequency initial value control means outputs a condition control signal for lowering the DDS output frequency and a frequency division control signal for reducing the frequency division ratio.

The frequency synthesizer according to claim 3 is
A DDS circuit according to claim 1, a DDS frequency dividing means for dividing a DDS output frequency, a phase comparing means for inputting a frequency division output of the DDS frequency dividing means and a PLL output frequency described later, and the phase comparison. It comprises a loop filter which receives a phase difference signal from the means and outputs a control voltage, and a PLL circuit which includes a voltage controlled oscillation means for oscillating a PLL output frequency based on the control voltage.

[0025]

According to the first aspect of the present invention, in the address generation means, the storage means is accessed by the address generated according to the DDS reference frequency and the read condition output from the condition output means, and a predetermined address is generated. Waveform data is read, and the D / A conversion means converts the read waveform data into an analog signal and outputs it. In addition, an unnecessary frequency component, so-called floor noise, remains in this output frequency. The output frequency thus output is input to the phase comparison means. Then, the control signal obtained by integrating the phase difference signal output from the phase comparison means by the loop filter is input to the voltage controlled oscillation means, so that the output frequency is a different frequency component other than the target frequency. Even if so-called floor noise is included, the DDS output frequency output from the voltage controlled oscillation means includes only a single frequency spectrum component. That is, most floor noise is removed.
Therefore, a desired frequency can be obtained by changing the read condition of the DDS circuit, and floor noise, which is a drawback of the DDS circuit, can be almost removed, and an output frequency with high frequency purity can be obtained. In addition,
The portion composed of the phase comparison means, the loop filter, and the voltage controlled oscillation means functions as a filter for removing floor noise.

According to the second aspect of the invention, the DDS output frequency generated by the DDS circuit of the first aspect is input to the PLL circuit having the frequency dividing means as a reference frequency. The condition output means and the frequency dividing means of the PLL circuit are controlled by the frequency initial value control means.
At this time, the frequency initial value control means controls the condition output means with a condition control signal for a predetermined time after the output frequency switching command from the outside is input to control the DDS.
Since the output frequency is raised and the frequency dividing means is controlled by the frequency dividing control signal to increase the frequency dividing ratio M (dividing to 1 / M), the PLL circuit operates at a high frequency.
Therefore, the PLL system locks in a short time. After the PLL system locks after a predetermined time, the condition output means and the frequency dividing means are simultaneously controlled to output a normal read condition to the DDS circuit to lower the DDS output frequency, and at the same time, the PLL circuit. However, since the frequency division ratio M is reduced to a normal value, the DDS output frequency and the PLL frequency remain in the normal range while the phase is locked. Therefore,
The ability of the DDS circuit to generate a desired frequency can be obtained, floor noise can be removed by the PLL circuit, and the lockup time in the PLL circuit can be shortened.

According to the present invention of claim 3,
The DDS output frequency generated by the DDS circuit having the structure of claim 1 is input to the DDS frequency dividing means. In addition, the D
Most floor noise is removed from the DS output frequency, but it remains. The DDS frequency divided by the DDS frequency dividing means by the predetermined frequency division ratio P is input to the PLL circuit. At this time, the floor noise is reduced by being divided by the DDS dividing means. If the division ratio P = 2 ^Q , the floor noise will be 6 ^Q.
[DB] is reduced. Therefore, in the PLL circuit,
The signal with reduced floor noise is used as the reference frequency,
It is input to the phase comparison means, and as described in claim 1, P
In the LL circuit, an output frequency with higher frequency purity can be obtained.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention of each claim will be described below in detail with reference to the drawings showing the embodiments thereof. 1 is a circuit configuration diagram of a DDS circuit of an embodiment according to claim 1 of the present invention.

In FIG. 1, 1 is a DDS circuit, 2 is a DD
Oscillating means 5 for oscillating and outputting the S reference frequency Fref is a condition outputting means for outputting a reading condition in response to an output frequency switching command from the outside. The DDS circuit 1
Are storage means 6 for storing the waveform data, address generation means 7, for generating an address for accessing the storage means 6 in accordance with the DDS reference frequency Fref and the reading conditions.
D / that converts the read waveform data into an analog signal
A conversion means 8, phase comparison means to which an output from the D / A conversion means 8 and a DDS output frequency Fdds described later are input
10, a loop filter 11 for receiving a phase difference signal from the phase comparison means 10 and outputting a control voltage, and a voltage controlled oscillation means 12 for oscillating a DDS output frequency Fdds based on the control voltage. The part composed of the phase comparison means 10, the loop filter 11, and the voltage controlled oscillation means 12 functions as a filter for removing floor noise when the input frequency and the output frequency match. .

In the DDS circuit 1 shown in FIG. 1, the address generating means 7 has a DDS reference frequency Fref from the oscillating means 2.
Then, an address based on the read condition output from the condition output means 5 is generated to access the storage means 6, and the read waveform data is converted into an analog signal by the D / A conversion means 8 and output. Here, in the state output from the D / A conversion means 8, as shown in FIG. 2, there are many high-order frequency components and unnecessary frequency components including floor noise, so the characteristic line F9 in FIG. The DDS reference frequency Fref and this D
A configuration may be adopted in which high-order frequency components of floor noise are removed together with image components centered on the DS reference frequency Fref. However, even in this case, the floor noise in the pass band of the low pass filter remains.

The phase difference signal between the analog signal output from the D / A conversion means 8 and the DDS output frequency Fdds is output from the phase comparison means 10, and the loop filter 11 outputs the control voltage obtained by integrating the phase difference signal. Is output. At this time, even if the analog signal includes floor noise, it has a certain control voltage in the integrated state. Therefore, at the DDS output frequency Fdds output from the voltage controlled oscillator 12 according to this control voltage, the floor noise is removed to the extent that it does not affect the floor noise. That is, an output frequency with high frequency purity can be obtained.

In this way, high frequency purity can be obtained, and high frequency generating capability can be obtained by controlling the read conditions.

FIG. 3 is a circuit configuration diagram of a frequency synthesizer of an embodiment according to claim 2 of the present invention. In FIG. 3, reference numeral 21 is a frequency synthesizer, an oscillating means 22 for oscillating and outputting the DDS reference frequency Fref, a DDS circuit 23 equivalent to the DDS circuit 1 in FIG. 1, and a PLL circuit 24.
And a condition output means 25 for outputting a read condition for the DDS circuit 23 according to a condition control signal.
The condition control signal corresponds to the output frequency switching command in FIG. The DDS circuit 23 includes a storage means 26 storing waveform data and a DDS reference frequency Fref.
And an address generation means 27 for generating an address for accessing the storage means 26 according to the read condition, a D / A conversion means 28 for converting the waveform data read from the storage means 26 into an analog signal, and a phase. A filter unit 29 including a comparison unit, a loop filter and a voltage controlled oscillation unit for removing floor noise from the analog signal.
Is equipped with. A low pass filter may be provided between the D / A conversion means 28 and the filter unit 29. The DDS circuit 23 in FIG. 3 has the same circuit configuration as that of the DDS circuit 1 in FIG. 1, and the frequency synthesizer in FIG.
21 is the DDS circuit 1 in FIG.
Is a configuration in which is added. Then, the filter unit 29 and the PLL
The circuit 24 forms a two-stage loop.

The PLL circuit 24 includes a phase comparison means 30 to which the DDS output frequency Fdds and an output of a frequency dividing means described later are input, a loop filter 31 to which a phase difference signal is input and which outputs a control voltage, and the control circuit. It is provided with a voltage control oscillating means 32 for oscillating a PLL output frequency Fout based on a voltage, and a frequency dividing means 33 for dividing the PLL output frequency by a frequency dividing ratio M and outputting it to the phase comparing means 30. The phase comparison means 30 outputs an unlock signal until the PLL loop is locked. Reference numeral 34 is a frequency initial value control means for controlling the condition output means 25 and the frequency dividing means 33 based on the output frequency switching command.

The frequency initial value control means 34 is provided with an initial value table 35 and a standard value table 36, which are composed of condition control signal data and frequency division control signal data, for each frequency to be output, and both of these tables are provided. A table switching circuit 37 for selectively switching and outputting any one of the data, and the table switching circuit 37 for a predetermined time after an external output frequency switching command is input.
From the initial value table 35 to the output control circuit 38. The condition control signal data of the initial value table 35 is a standard value table.
It is data that can obtain DDS output frequency higher than 36,
The frequency division control signal data of the initial value table 35 is data having a larger frequency division ratio than the standard value table 36.

In the above configuration, when an output frequency switching command from the outside is input to the frequency initial value control means 34, first, the data of the initial value table 35 is output from the table switching circuit 37, and the DDS circuit. Since the DDS output frequency higher than the normal frequency is output from 23, the PLL circuit 24 locks in a shorter time than usual. Next, the data of the standard value table 36 is output from the table switching circuit 37 after a lapse of a fixed time after the PLL circuit 24 locks and the unlock signal disappears, so that the DDS circuit 23 outputs the data. Lowers its output frequency to the normal DDS output frequency, and at the same time, in the PLL circuit 24, returns the division ratio to the normal value, so that the desired PLL output frequency F
You get out. The table switching circuit 37 may switch to the standard value table 36 side by using a simple timer without using the unlock signal.

In this embodiment, the DDS circuit 23 can obtain a high frequency generation capability, and the PLL circuit 24 can obtain a PLL output frequency having a high frequency purity. Further, by using the PLL circuit 24 having the frequency dividing means 33 and the frequency initial value control means 34, the PLL circuit can be locked in a short time and the PLL frequency Fout can be switched at high speed. .

FIG. 4 is a circuit configuration diagram of a frequency synthesizer of an embodiment according to claim 3 of the present invention. In FIG. 4, reference numeral 41 is a frequency synthesizer, which oscillates 42 for oscillating and outputting the DDS reference frequency Fref, a DDS circuit 43 equivalent to the DDS circuit 1 in FIG. 1, and a DDS output frequency Fdds with a division ratio P. DDS frequency dividing means 44 for frequency division,
A PLL circuit 45 and a condition output means 46 for outputting a read condition for the DDS circuit 43 in response to an output frequency switching command input from the outside are provided. Since the DDS circuit 43 has the same configuration as the DDS circuit of FIG. 1 or 3, the internal description is omitted. In addition, the P
The LL circuit 45 has the same configuration as the PLL circuit of FIG. 1 or FIG. When the PLL circuit 24 of FIG. 3 has the same configuration, it is natural to include the frequency initial value control means 47 similar to the frequency initial value control means 34 of FIG. 3 as shown by the broken line.

According to the frequency synthesizer 41 of FIG. 4, D
The DDS output frequency Fdds output from the DS circuit 43 is
The frequency is divided into 1 / P by the DDS frequency dividing means 44. Here, if the division ratio P = 2 ^Q , the floor noise is 6 ^Q.
[DB] The PLL output frequency Fout with reduced frequency purity is obtained. For example, when the division ratio is 4, floor noise is reduced by 12 [dB]. In this embodiment, the DDS circuit 43 obtains a high frequency generation capability, the DDS divider 44 increases the purity of the reference frequency for the PLL circuit 45, and the PLL circuit 45 obtains the PLL output frequency from which floor noise is removed. Can be done. Further, as indicated by the broken line, the frequency initial value control means has the same configuration as the PLL circuit 24 of FIG.
By providing 47, the PLL circuit can be locked in a short time, and the PLL output frequency Fout can be switched at high speed.

[0040]

According to the first aspect of the present invention, the DD including the phase comparison means, the loop filter and the voltage controlled oscillation means.
The S circuit makes it possible to obtain an output frequency with high frequency purity from which floor noise is removed, and
An excellent frequency generation capability, which is a characteristic of the circuit, is also obtained.

According to a second aspect of the present invention, the DDS output frequency output from the DDS circuit of the first aspect is used as the reference frequency of the PLL circuit having the frequency dividing means, and the same as above. As well as being effective,
By increasing the DDS output frequency and increasing the frequency division ratio in the frequency dividing means for a predetermined time after the output frequency switching command from the outside is input,
The lock-up time of the PLL circuit can be shortened, and excellent frequency switching ability can be obtained for the entire frequency synthesizer.

According to a third aspect of the present invention, the DDS output frequency output from the DDS circuit having the first aspect is frequency-divided and then used as the reference frequency of the PLL circuit to further improve the frequency purity. A high PLL output frequency can be obtained. In addition, by switching the DDS output frequency of the DDS circuit, an excellent frequency generation capability can be obtained for the frequency synthesizer as a whole.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a DDS circuit according to claim 1.

FIG. 2 is a frequency spectrum distribution diagram in a part of the DDS circuit.

FIG. 3 is a configuration diagram of one embodiment of the frequency synthesizer of claim 2;

FIG. 4 is a configuration diagram of an embodiment of the frequency synthesizer of claim 3;

[Explanation of symbols]

 Fref DDS reference frequency Fdds DDS output frequency Fout PLL output frequency 1 DDS circuit (Claim 1) 5 condition output means 6 storage means 7 address generation means 8 D / A conversion means 10 phase comparison means 11 loop filter 12 voltage controlled oscillation means 21 Frequency synthesizer (Claim 2) 23 DDS circuit 24 PLL circuit 25 Condition output means 26 Storage means 27 Address generation means 28 D / A conversion means 29 Filter section 30 Phase comparison means 31 Loop filter 32 Voltage control oscillation means 33 Frequency division means ( Frequency division ratio M) 34 Frequency initial value control means 35 Initial value table 36 Standard value table 37 Table switching circuit 38 Switching control circuit 41 Frequency synthesizer (Claim 3) 43 DDS circuit 44 DDS frequency dividing means (division ratio P) 45 PLL circuit 46 Condition output means 47 Frequency initial value control means

Claims (3)

[Claims] 1. Condition output means for outputting a read condition based on a condition control signal from the outside, storage means for storing waveform data, and waveform data from the storage means according to a DDS reference frequency and the read condition. Address generating means for generating an address for reading out, D / A converting means for converting the read waveform data into an analog signal and outputting the analog signal, and phase comparing means for inputting the analog signal and a DDS output frequency described later. And a loop filter that receives a phase difference signal from the phase comparison means and outputs a control voltage, and a voltage control oscillation means that oscillates a DDS output frequency based on the control voltage. DDS circuit to do. 2. A DDS circuit according to claim 1, a phase comparison means to which a DDS output frequency and an output of a frequency dividing means described later are inputted, and a phase difference signal from the phase comparison means is inputted to the control voltage. A loop filter for outputting the voltage, a voltage control oscillating means for oscillating a PLL output frequency based on the control voltage, and a frequency dividing means for frequency-dividing and outputting the PLL output frequency at a frequency dividing ratio according to a frequency dividing control signal PL equipped
During a predetermined time after the L circuit and an output frequency switching command from the outside are input, the condition output means is controlled to output a condition control signal for increasing the DDS output frequency, and the frequency dividing means is controlled. Then, a frequency division control signal for increasing the frequency division ratio is output, and after a predetermined time, a condition control signal for decreasing the DDS output frequency is output and a frequency division control signal for decreasing the frequency division ratio is output. The DDS according to claim 1, characterized in that the DDS comprises a value control means.
Frequency synthesizer using a circuit. 3. A DDS circuit according to claim 1, a DDS divider for dividing a DDS output frequency, a phase comparison in which a divided output of the DDS divider and a PLL output frequency described later are input. Means, a loop filter for receiving a phase difference signal from the phase comparing means and outputting a control voltage, and a PLL circuit including a voltage control oscillating means for oscillating a PLL output frequency based on the control voltage. A frequency synthesizer using the DDS circuit according to claim 1.