JPH06338793A - Pll frequency synthesizer circuit - Google Patents

Abstract

PURPOSE:To provide a multi-circuit PLL frequency synthesizer circuit without generating the interference of a signal by respective oscillation circuit part and capable of switching a frequency with low power consumption and at high speed. CONSTITUTION:Standby circuits(STBY) 40, 41 are provided for the VCO 38 of a first PLL frequency synthesizer circuit 52 and the VCO 39 of a second PLL frequency synthesizer circuit 53 in a two-circuit PLL frequency synthesizer circuit 30, respectively, and for example, only the VCO 38 is made to be in an operating state by letting the standby circuit(STBY) 40 be on an operating mode when the PLL frequency synthesizer circuit 52 is used, and by letting the VCO 39 be in a standby state by letting the standby circuit(STBY) 41 of the PLL frequency synthesizer circuit 53 on the other side be on a standby mode, thereby, the oscillation of the VCO 39 is stopped, and spurious wave can be prevented from occurring. Also, when the frequency is switched, the VCO 39 in the standby state is made to be in the operating state, and the VCO 38 in the operating state is set in the standby state by the standby circuits(STBY) 40, 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked).
Loop) frequency synthesizer circuit, and more particularly, to a multi-circuit PLL frequency synthesizer circuit for high-speed frequency switching.

[0002]

2. Description of the Related Art A PLL frequency synthesizer circuit is used for a tuning circuit of mobile band communication equipment such as a digital cordless telephone and a mobile telephone.

FIG. 3 is a circuit diagram of a conventional PLL frequency synthesizer circuit. In FIG. 3, the PLL frequency synthesizer circuit 10 includes a reference signal oscillator 11, a frequency divider 12, a phase comparator (PD) 13, a loop filter (LP).
F) 14, VCO (Voltage Controlled Oscillator) 15, comparison frequency divider 16 and CPU 17
It is composed of

The frequency divider 12 and the phase comparator (PD) 13
The comparison frequency divider 16 constitutes a PLL circuit 18 as a whole, and the CPU 17 controls the PLL circuit 18 so as to output a control signal to each section and obtain a predetermined synthesizer output. As the reference signal oscillator 11, the reference frequency f tcx
o A crystal oscillator with high stability is used as the oscillator. When the reference frequency f tcxo is input from the reference signal oscillator 11, the frequency divider 12 causes the reference frequency f t c of the reference signal oscillator 11.
The reference signal f r (= f tcxo /
R) is output to the phase comparator (PD) 13.

The phase comparator (PD) 13 has a reference signal f r (= f tcxo / R) divided by R by the frequency divider 12 and VCO1.
The signal f vco of 5 is frequency-compared with the comparison signal f r ′ (= f vco / N) obtained by dividing the signal f vco of 5 by N by the comparison frequency divider 16, and the error signal is output to the loop filter (LPF) 14. The loop filter (LPF) 14 integrates the input error signal and converts it into an error voltage, and applies this error voltage to the control terminal of the VCO 15. Therefore, the VCO 15 has f r = f
It operates so as to be r ′ and obtains a signal in which the frequency of f vco = fr × N is kept constant.

On the other hand, one of the high-speed frequency switching is a multi-circuit PLL frequency synthesizer circuit as shown in FIG. FIG. 4 shows a PL having two circuits out of multiple circuits.
It is an example of an L frequency synthesizer circuit. In FIG.
The multi-circuit PLL frequency synthesizer circuit 20 includes a reference signal oscillator 21, PLL circuits 22 and 23, and VCOs 24 and 2.
5, an output selection switch (SW) 26, and a CPU 27. The PLL circuits 22 and 23 have the same circuit configuration as the PLL circuit 18 shown in FIG.

The reference signal oscillator 21 and the PLL circuit 2
2, the VCO 24, the output selection switch (SW) 26 and the CPU 27 as a whole include the first PLL frequency synthesizer circuit 28, and the reference signal oscillator 21, the PLL circuit 23, the VCO 25, the output selection switch (SW) 26 and the CPU 27. , The second PLL frequency synthesizer circuit 29 is configured as a whole, and the output of the first PLL frequency synthesizer circuit 28 and the output of the second PLL frequency synthesizer circuit 29 are output selection switches receiving a switching control signal from the CPU 27. It is switched at high speed by the (SW) 26. As a result, the outputs of the two PLL frequency synthesizer circuits 28 and 29 are switched at high speed, and it is possible to obtain a signal having a constant frequency at different frequencies.

[0008]

However, in such a conventional PLL frequency synthesizer circuit having multiple circuits, each PLL has different circuits.
There is a problem in that interference of signals by the oscillation circuit of the frequency synthesizer circuit increases, spurious (interference noise) occurs, and current consumption increases. To prevent signal interference, shield each oscillator circuit, etc.,
Alternatively, it is necessary to take measures such as providing sufficient intervals between individual synthesizers. In order to increase the current consumption due to the increase in the number of circuits, there is a method such as stopping the power supply to the unused VCO. However, if the method such as stopping the power supply to the VCO is taken. There are drawbacks such that it takes time to oscillate at restart and it takes time to stabilize the frequency.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multi-circuit PLL frequency synthesizer circuit capable of high-speed frequency switching with low power consumption without signal interference by each oscillation circuit section.

[0010]

To achieve the above object, a PLL frequency synthesizer circuit according to the present invention divides a reference frequency output from a reference signal oscillator and a signal obtained by dividing a signal frequency output from a voltage controlled oscillator. Phase comparison is performed by a phase comparator, a phase error is converted to a voltage value by a loop filter and is fed back to the voltage controlled oscillator, and two or more PLL frequency synthesizer circuits that make the signal frequency of the output of the voltage controlled oscillator constant are provided. PL above the circuit
A PLL frequency synthesizer circuit comprising selection means for selecting an output of an L frequency synthesizer circuit, wherein the voltage controlled oscillator of the PLL frequency synthesizer circuit selected by the selection means oscillates when the voltage controlled oscillator is restarted. It has a standby circuit that shortens the time.

In the standby circuit, for example, as described in claim 2, by pre-charging the internal capacitor of the voltage controlled oscillator, the charging time of the capacitor is removed to restart oscillation. The time may be shortened.

The standby circuit has, for example, as described in claim 3, an operation mode in which the voltage controlled oscillator is in an operating state and a standby state in which the time for the voltage controlled oscillator to oscillate at restart is shortened. It may have a standby mode to operate.

In a preferred mode, the standby circuit has an operation mode for bringing the voltage-controlled oscillator into an operating state and a time period during which the voltage-controlled oscillator oscillates at restart, as described in claim 4, for example. It is also possible to have a standby mode in which the standby state is shortened to switch between the operation mode and the standby mode in correspondence with the switching of the output frequencies of the two or more PLL frequency synthesizer circuits.

Further, the standby circuit, for example, as described in claim 5, a standby mode for shortening the operation mode in which the voltage controlled oscillator is in an operating state and the time during which the voltage controlled oscillator oscillates at restart. And a second PLL frequency synthesizer having a standby mode in which the first PLL frequency synthesizer circuit is used and the standby circuit of the first PLL frequency synthesizer circuit is set to the operation mode to set the voltage controlled oscillator to the operating state. The standby circuit of the circuit may be placed in a standby mode to stop the oscillation of the voltage controlled oscillator.

[0015]

In the present invention, two or more PLL frequency synthesizer circuits are provided and the outputs of the two or more PLL frequency synthesizer circuits can be selectively switched. Furthermore, a standby circuit is provided to shorten the time during which the voltage controlled oscillator oscillates at restart. In this state, in the steady state, when the first PLL frequency synthesizer circuit is used, the standby circuit of the first PLL frequency synthesizer circuit is set to the operation mode, the voltage controlled oscillator becomes the operation state, and the second PLL frequency synthesizer circuit operates. The standby circuit is placed in the standby mode and the oscillation of the voltage controlled oscillator is stopped. Also, when switching frequencies,
The operation mode and the standby mode are switched according to the switching of the output frequencies of the two or more PLL frequency synthesizer circuits.

Therefore, it is possible to realize a multi-circuit PLL frequency synthesizer circuit capable of high-speed frequency switching with low power consumption without signal interference by the respective oscillation circuit sections.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing an embodiment of a PLL frequency synthesizer circuit according to the present invention, and this embodiment is an example applied to a two-circuit PLL frequency synthesizer circuit. First, the configuration will be described. FIG. 1 is a block diagram of a two-circuit PLL frequency synthesizer circuit. In FIG.
The two-circuit PLL frequency synthesizer circuit 30 includes a reference signal oscillator 31, PLL circuits (PLL frequency synthesizer circuits) 32 and 33, a loop filter 1 (LPF1) 34,
35, loop filter 2 (LPF2) 36, 37, VC
O (voltage controlled oscillator) 38, 39, standby circuit (S
TBY) 40, 41, output selection switch (SW) 42,
It is configured by the CPU 43.

The PLL circuits 32 and 33 include frequency dividers 44 and 45, phase comparators (PD) 46 and 47, switching circuits (switching means) 48 and 49, and comparison frequency dividers 50 and 51.
It is composed of As the reference signal oscillator 31, a crystal oscillator having a high stability is used as the reference frequency f tcxo oscillator.

The frequency dividers 44 and 45 are the reference signal oscillator 31.
The reference frequency f tcxo of R is divided by R, and the reference signal f r (= f tcxo / R) divided by R is phase-comparator (PD) 46, 4
Output to 7. The phase comparators (PD) 46 and 47 divide the reference signal fr (= f tcxo /
R) and the signal f vco of the VCO 38, 39 are compared and frequency divider 5
The comparison signal f r ′ (= f vco /
N) and the error signal is compared with the switching circuits 48, 4
Output to 9. The comparison frequency dividers 50 and 51 are the VCO 38,
The output signal f vco from 39 is divided by N, and the comparison signal f r '
(= F vco / N) as a phase comparator (PD) 46, 47
To return to. The frequency of the synthesizer is selected by changing the frequency division ratio N. The switching circuits 48 and 49 are
The error signals from the comparison frequency dividers 50 and 51 are switched to the loop filters 1 (LPF1) 34 and 35 for removing spurious or the loop filters 2 (LPF2) 36 and 37 for output.

Loop filter 1 (LPF1) 34, 35
Is a filter that is provided for spurious removal separately from the original loop filters 2 (LPF2) 36 and 37, and sets the time constant of the filter to be long to prevent the occurrence of spurious due to interference. However, since the response characteristic deteriorates, the switching circuit 48, 49 causes the loop filter 1 (L
PF1) 34, 35 or loop filter 2 (LPF)
2) Switch between 36 and 37 for use. The loop filters 2 (LPF2) 36 and 37 are composed of low-pass filters, integrate the error signals from the phase comparators (PD) 46 and 47 to remove high frequency components and convert them into error voltages. Is added to the control terminals of VCOs 38 and 39.

The VCOs 38 and 39 are loop filters 2
F r = f due to the error voltage from (LPF2) 36 and 37
It operates so as to be r ′ and outputs a frequency signal in which the frequency of f vco = fr / N is kept constant. Standby circuit (S
TBY) 40 and 41 are circuits that enable the VCOs 38 and 39 to start up at high speed, and are controlled by control signals from the CPU 27. It will be described later with reference to FIG.

The output selection switch (SW) 42 is a CPU
It is possible to switch the outputs of the VCOs 38 and 39 at high speed by a switching control signal from 27 and obtain signals with different frequencies kept constant. The CPU 43 outputs a control signal to each unit to obtain a predetermined synthesizer output, the PLL circuits 32 and 33, and a standby circuit (STBY).
40, 41 and the output selection switch (SW) 42 are controlled.

The reference signal oscillator 31, the PLL circuit 3
2, the loop filter 1 (LPF1) 34, the loop filter 2 (LPF2) 36, the VCO 38, the standby circuit (STBY) 40, the output selection switch (SW) 42, and the CPU 43 constitute a first PLL frequency synthesizer circuit 52 as a whole. In addition, the reference signal oscillator 31,
PLL circuit 33, loop filter 1 (LPF1) 35,
Loop filter 2 (LPF2) 37, VCO 39, standby circuit (STBY) 41, output selection switch (S
W) 42 and the CPU 43 are the second PLL as a whole.
The frequency synthesizer circuit 53 is configured.

FIG. 2 shows the standby circuit (STBY).
It is a figure for demonstrating the function of 40,41. As described above, there is a method of stopping the power supply to the VCO that is not in use to increase the current consumption due to the increase in the number of circuits, but if this method is adopted, oscillation at restart will occur. There is a drawback that it takes time to stabilize the frequency. The reason is that there is a noise removing capacitor inside the VCO, and it is necessary to charge this capacitor when oscillation occurs at restart after stopping the power supply to the VCO. Therefore, it takes time until the oscillation at the time of restart due to the charging time of the capacitor.

Therefore, in this embodiment, the VCOs 38 and 3 are used.
9. Standby circuits (STBY) 40 and 41 for pre-charging the noise removal capacitors inside 9 are provided, and the standby circuits (STBY) 40 and 41 are controlled by a control signal from the CPU 27, so that the VCOs 38 and 39 stand up at high speed. Enables raising. In this case, the standby circuits (STBY) 40 and 41 have an operation mode in which the VCOs 38 and 39 are in an operating state and a standby mode in which the VCOs 38 and 39 are in a standby state in which the oscillation time at restart is shortened. The mode and the standby mode are switched according to the switching of the output frequencies of the PLL frequency synthesizer circuits 52 and 53.

Next, the operation will be described. The two-circuit PLL frequency synthesizer circuit 30 of the present embodiment repeatedly operates in the following (1) steady state and (2) frequency switching state. (1) Steady state When one PLL frequency synthesizer circuit (for example, the first PLL frequency synthesizer circuit 52) is operating, the standby circuit (STBY) 40 of the first PLL frequency synthesizer circuit 52 is in the operation mode, VCO38
Is operating, the output of the VCO 38 is locked to a predetermined frequency by the PLL circuit 32, and the output selection switch (S
W) 42 is operative to output the frequency signal from VCO 38.

The state in which the PLL is applied will be specifically described. The frequency divider 44 frequency-divides the reference frequency f tcxo of the reference signal oscillator 31 by R, and the frequency-divided reference signal f r (= f tc
xo / R) is output to the phase comparator (PD) 46. The phase comparator (PD) 46 divides the reference signal f r (= f tcxo / R) divided by R by the divider 44 and the signal f vco of the VCO 38 into N by the comparison divider 50 and compares them by a comparison signal f r. '(= F v
Co / N) is compared in phase and the error signal is output to the loop filter 2 (LPF2) 36. Loop filter 2
The (LPF2) 36 integrates the input error signal to convert it into an error voltage, and applies this error voltage to the control terminal of the VCO 38. As a result, the VCO 38 operates so that f r = f r ′ and obtains a signal in which the frequency of f vco = fr × N is kept constant.

At this time, the standby circuit (STBY) 41 of the other PLL frequency synthesizer circuit (in this case, the second PLL frequency synthesizer circuit 53) is in the standby mode, and the VCO 39 is in the standby state. Since VCO 39 is in the standby state, VCO 3
Oscillation based on 9 does not occur, and spurious due to signal interference by the respective oscillation circuit units does not occur.

(2) At the time of frequency switching The PLL frequency synthesizer circuit in the standby state (in this case, the second PLL frequency synthesizer circuit 5)
The value of the counter corresponding to the frequency for switching to the PLL operation of 3) is set. In addition, the VCO 39 in the standby state
Is in the operating state, and the operating VCO 38 is in the standby state to switch the output selection switch (SW) 42.
At this time, the standby circuit (S
Since the noise removal capacitor inside the VCO 39 is charged in advance by the TBY) 41, the VCO 39 starts up at a high speed, and the switching circuit 49 causes the loop filter 1 (LPF1) 35 to switch the loop filter 2 to the loop filter 2 at the initial stage of response.
By switching to (LPF2) 37, the time constant of the loop filter is lowered and the oscillation frequency is adjusted at high speed. Spurious is likely to occur by lowering the time constant of the loop filter in the initial stage of response, but spurious emission is ignored in the initial stage of response, and response characteristics are emphasized.

As described above, when the first PLL frequency synthesizer circuit 52 is operating and the standby circuit (STBY) 41 of the second PLL frequency synthesizer circuit 53 is in the standby mode, the frequency switching is performed. , But the opposite is exactly the same.

As described above, in this embodiment, in the two-circuit PLL frequency synthesizer circuit 30, the VCO 38 and the second PL of the first PLL frequency synthesizer circuit 52 are connected.
The VCO 39 of the L frequency synthesizer circuit 53 is provided with standby circuits (STBY) 40 and 41, respectively. For example, when the PLL frequency synthesizer circuit 52 is used, the standby circuit (STBY) 40 is set to an operation mode.
Only the 38 is in the operating state, the standby circuit (STBY) 41 of the other PLL frequency synthesizer circuit 53 is set in the standby mode, and the VCO 39 is set in the standby state to stop the oscillation of the VCO 39 and prevent the spurious emission due to the signal interference. . When the frequency is switched, the standby circuits (STBY) 40 and 41 bring the VCO 39 in the standby state into the operating state and the VCO 38 in the operating state into the standby state. As a result, the VCO 39 can be activated at high speed, and high-speed frequency switching can be realized.

Further, the loop filters 1 (LPF1) 34, 35 for removing spurious are switched by the switching circuits 48, 49.
By switching between the loop filter 2 and the loop filter 2 (LPF2) 36 and 37, it is possible to prevent spurious noise from occurring and achieve a response characteristic at the same time.

In the present embodiment, the multi-circuit PLL frequency synthesizer circuit is applied to a two-circuit PLL frequency synthesizer circuit, but any configuration is possible as long as the PLL frequency synthesizer circuit is multi-circuit. The type and number of each member, control method, etc.
It goes without saying that anything can be used.

[0034]

According to the present invention, in a multi-circuit PLL frequency synthesizer circuit for the purpose of high-speed frequency switching, spurious due to the interference of signals of respective oscillating parts does not occur and current consumption can be reduced. The individual shields can be eliminated or simplified, and high-density mounting can be achieved. Further, the increase in current consumption due to the increase in the number of circuits is small, and it becomes possible to positively increase the number of circuits.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 2 is a configuration diagram of a standby circuit of the PLL frequency synthesizer circuit of the same embodiment.

FIG. 3 is a circuit configuration diagram of a conventional PLL frequency synthesizer circuit.

FIG. 4 is a circuit configuration diagram of a conventional two-circuit PLL frequency synthesizer circuit.

[Explanation of symbols]

30 2 Circuits PLL Frequency Synthesizer Circuit 31 Reference Signal Oscillator 32, 33 PLL Circuit (PLL Frequency Synthesizer Circuit) 34, 35 Loop Filter 1 (LPF1) 36, 37 Loop Filter 2 (LPF2) 38, 39 VCO (Voltage Controlled Oscillator) 40 , 41 Standby circuit (STBY) 42 Output selection switch (SW) 43 CPU 44, 45 frequency divider 46, 47 Phase comparator (PD) 48, 49 Switching circuit (switching means) 50, 51 Comparative frequency divider 52 First PLL frequency synthesizer circuit 53. Second PLL frequency synthesizer circuit

Claims (5)

[Claims] 1. A reference frequency output from a reference signal oscillator and a signal obtained by dividing a signal frequency output from a voltage controlled oscillator are phase-compared by a phase comparator, and a phase error is converted into a voltage value by a loop filter. P to make the signal frequency of the output of the voltage controlled oscillator constant by feeding back to the controlled oscillator
A PLL frequency synthesizer circuit comprising two or more LL frequency synthesizer circuits and selecting means for selecting an output of the two or more PLL frequency synthesizer circuits, wherein the PLL frequency synthesizer circuit selected by the selecting means 2. The PLL frequency synthesizer circuit according to claim 1, further comprising a standby circuit for shortening the time for the voltage controlled oscillator to oscillate when restarted. 2. The standby circuit eliminates the charging time of the capacitor by pre-charging the internal capacitor of the voltage controlled oscillator to shorten the time until the oscillation at restart. The PLL frequency synthesizer circuit according to claim 1, wherein the PLL frequency synthesizer circuit is a PLL frequency synthesizer circuit. 3. The standby circuit has an operation mode in which the voltage controlled oscillator is in an operating state, and a standby mode in which the voltage controlled oscillator is in a standby state in which the oscillation time at restart is shortened. The PLL frequency synthesizer circuit according to claim 1. 4. The standby circuit has an operation mode in which the voltage controlled oscillator is in an operating state, and a standby mode in which the standby state is shortened in which the time for the voltage controlled oscillator to oscillate at restart is shortened. 2. The PLL frequency synthesizer circuit according to claim 1, wherein the standby frequency and the standby mode are switched in correspondence with switching of output frequencies of the two or more PLL frequency synthesizer circuits. 5. The standby circuit has an operation mode in which the voltage controlled oscillator is in an operating state, and a standby mode in which the standby state is shortened in which the oscillation time of the voltage controlled oscillator when restarted is shortened. When the PLL frequency synthesizer circuit is used, the standby circuit of the first PLL frequency synthesizer circuit is set to the operating mode to set the voltage controlled oscillator in the operating state, and the standby circuit of the second PLL frequency synthesizer circuit is set to the standby mode to set the voltage controlled oscillator. 3. The PLL frequency synthesizer circuit according to claim 1, wherein the oscillation of the PLL is stopped.