JP3270586B2 - Phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit for matching an output frequency to a target frequency, and more particularly to a method for stably locking a frequency within a predetermined time even when an operating voltage is changed. It is configured to be able to.

[0002]

2. Description of the Related Art A crystal oscillator circuit has been used as a signal source in a communication device or a cellular phone for some time. However, in recent years, a signal of a plurality of frequencies has been generated by the same device with the increase in communication channels. Alternatively, a frequency synthesizer using a phase locked loop circuit (PLL circuit) that can be synthesized is generally used. This PLL
Circuits are also widely used as means for keeping the rotation speed of the medium of various optical and magnetic disk storage devices constant.

As shown in FIG. 3, a frequency synthesizer which is an application example of this PLL circuit has a low-pass filter (LPF) 1 having a gain K _{F (S)} and a voltage-controlled oscillator circuit having a gain K _V / S. VCO) 2, a variable frequency dividing circuit (programmable divider: PD) 3 for dividing the output of the VCO to an arbitrary number 1 / N, and comparing the output Kφ of the PD with the input θ _{i (S) of the} frequency synthesizer. Phase comparison circuit (phase
Comparator: PC) 4 and outputs θ _{O (S)} as an output signal.

The system shown in FIG. 3 can be represented in the form of a block diagram in FIG. 4 as a general closed-loop control system.
Where G (S) is the forward loop transfer function, H (S) is the transfer function of the feedback loop, θ _{i (S)} and θ
_{O (S)} is the input and output of this system, respectively.

The transfer function Y (S) of this closed loop control system can be expressed as follows: Y (S) = G (S) / {1 + G (S) .H (S)} (1)

The transfer function of the system shown in FIG. 3 is expressed as G (S) and H (S) in equation (1), where G (S) = K _F · (K _V / S) · Kφ H (S) = 1 / by substituting N, it is determined as Y (S) = {Kφ · K F · K V} / {S + (Kφ · K F · K V / N)} (2).

When a lag filter as shown in FIG. 5 is used as the LPF of this system, K _{F (S)} = 1 / (T · S + 1) (3) (where T is a time constant of the filter and T = C · R), and when this is substituted into equation (2), Y (S) = ｛(Kφ · K _V ) / T｝ / ｛S ² + (1 / T) S + (Kφ · K _V ) / N · T｝ (4).

When equation (4) is compared with Y (S) = ω _n ² / 形 S ² + 2ξω _n S + ω _n ² ｝ (5) which is a standard form of the transfer function of the secondary form, natural frequency ω _n Is: ω _n = {(Kφ · K _V ) / (N · T) ( ^1/2 (6) The damping factor is: ξ = １ ／ {N / (Kφ · K _V · T)} ^{1 / 2} (7).

The form of the step response of this system depends on the damping factor ξ, and the damping factor ξ
It is widely known that when the value approaches 0, the vibration does not converge, and the vibration is attenuated when 0 <ξ <1 and monotonically attenuated when ξ> 1. In a frequency synthesizer, it is required that the output converge as quickly as possible, and therefore, the damping factor ξ is usually selected to be about 0.6 to 0.8.

[0010]

However, the conventional PLL
In a circuit, the value of the damping factor 大 き く greatly depends on the power supply voltage of the circuit. For example, when the power supply voltage is changed depending on the operation mode to save power, such as in a mobile phone, the operation characteristics of the PLL circuit Had a problem that it changed greatly.

This is due to the fact that the gain K _V / S of the VCO in the PLL circuit changes under the influence of the supply voltage to the VCO. If lowered, the gain K of the VCO
_V / S also decreases, and the convergence time of the PLL circuit increases. As a result, the lock-up time of the frequency synthesizer becomes longer, which hinders the operation.

The present invention solves such a conventional problem, and a phase locked loop capable of stably locking the frequency of an input signal within a fixed time even when the operating voltage is changed. It is intended to provide a circuit.

[0013]

Therefore, according to the present invention, there is provided a phase locked loop circuit comprising at least a phase comparing means, a low-pass filter, and a voltage controlled oscillating means on a closed loop and operating at a plurality of operating voltages. Switching means for switching the time constant of the low-pass filter in accordance with a change in the operating voltage.

The switching means changes the connection of the capacitor, which is a component of the low-pass filter, for switching the time constant.

Alternatively, the connection of the resistor, which is a component of the low-pass filter, is changed by the switching means in order to switch the time constant.

[0016]

Therefore, even if the gain of the VCO changes due to a change in the operating voltage, the damping factor ξ is maintained at an optimum value by switching the time constant T of the LPF, and the phase of the input signal is changed within a predetermined time. Locked.

[0017]

FIG. 1 shows an embodiment of a frequency synthesizer circuit using a PLL circuit according to the present invention. This frequency synthesizer circuit includes a lag filter 1 as an LPF.
, A VCO 2, a PD 3, a PC 4, a reference frequency generation circuit 5, a crystal oscillator 6 for generating a signal serving as a reference frequency of the PLL circuit, and a power supply 7 for supplying power to each circuit.
1, 72 are provided.

The lag filter 1 includes a resistor R, a plurality of capacitors C1 and C2, and a switch SW2 for selecting connection of these capacitors. Further, the power supply circuit includes a changeover switch SW1 for selecting whether to add the power supply 72 or not.
The operating voltage applied to each circuit is changed. The switching operation of SW1 and the switching operation of SW2 in the lag filter 1 are linked.

In this frequency synthesizer circuit, the crystal oscillator 6 generates a signal having a frequency n times the reference frequency, and divides the signal by n in the reference frequency generation circuit 5 to form a signal having the reference frequency. It is provided to one of the inputs of PC4.

At the same time, a part of the output of VCO 2 is frequency-divided by PD 3 and applied to the other input of PC 4. PC4 is
The phase comparison between the reference frequency and the divided output of the VCO 2 is performed, and an error signal corresponding to the phase difference is output.

This error signal is input to the VCO 2 as a control signal after unnecessary high frequency components are removed by the LPF 1,
The output frequency of the VCO 2 is corrected to a target frequency. VCO
When the output frequency of No. 2 becomes the same as the target frequency, this frequency synthesizer is locked.

When the operating voltage of the frequency synthesizer is high, that is, when SW1 is at the position a, L
Similarly, SW2 of PF1 is located at a, and capacitor C1 is selected. As a result, the damping factor ξ in this PLL system is set to an optimum value.

Next, when the equipment using this frequency synthesizer lowers the power supply voltage for the purpose of power consumption reduction, that is, when SW1 is located at b, SW2 is also moved to b, and LPF1 is turned on. C2 is selected as the capacitor of the above. As a result, the damping factor の of the PLL system takes an optimum value under the condition that the power supply voltage is gradually reduced.

As described above, in the PLL circuit according to the embodiment, the time constant T of the LPF is changed by changing the connection of the capacitor in the LPF according to the operating voltage of the circuit, whereby the damping factor 常 に is always optimal. Set to value. For this reason, it is possible to lock the frequency within a stable time.

FIG. 2 shows an embodiment of a frequency synthesizer constructed using a generally known IC. Q1
Is a P / P with a built-in PD, PC and reference frequency generation circuit
The MB87001A is an LL IC, and the capacitors C5 and C6 connected to Q1 and the crystal oscillator X1 constitute a part of a reference frequency generation circuit. Q3 is VCO
Is a prescaler MB501 that divides the frequency of the output signal of FIG.

This circuit further comprises a VCO (Q2),
A lag filter as an LPF, batteries B1 and B2 serving as power supplies for the PLL circuit, a changeover switch SW1 for changing an operation voltage of the PLL circuit, a changeover switch SW2 linked to SW1, and a resistor R4 are provided. .

The LPF includes R1, C3, C4 and a diode D1, which, together with the resistor R4, serves to change the time constant of the LPF according to the operating voltage.

In this frequency synthesizer circuit, a signal having a frequency n times the reference frequency is generated by the crystal oscillator X1, and is divided by n inside Q1 to form a reference frequency.
At the same time, Q3 divides a portion of the output of Q2 to such a frequency that PDs and PCs inside Q1 are operable. Next, the PC inside Q1 compares the phase of the reference frequency with the frequency-divided output of Q2, outputs an error signal corresponding to the phase difference from Q1, passes through the LPF, and becomes the control signal of Q2. Thus, the output frequency of Q2 is corrected to the target frequency.

Now, when the operating voltage of this frequency synthesizer is high, that is, when SW1 is at the position a, SW
2 is also at the position a, so that D1 is turned ON and L
Both the capacitors C3 and C4 are used as the capacitors of the PF.

On the other hand, the state where the power supply voltage is gradually reduced, that is, S
When W1 is located at b, SW2 also moves to b, D1 is turned off, and only C3 is used as the LPF capacitor.

The capacitance values of capacitors C3 and C4 are set so that the damping factor の of the PLL system can take an optimum value under any of these conditions.

As described above, in the PLL circuit according to the embodiment of the present invention, the time constant T of the LPF is changed in accordance with the operating voltage of the circuit. As a result, the damping factor 常 に always takes the optimum value, The phase will always be locked within a certain time.

In order to change the time constant T of the LPF, a plurality of resistors R in the LPF are provided in place of the switching of the capacitor, and the connection of the resistors is switched in conjunction with the change of the operating voltage. May be.

When the operating voltage of the device can be switched among three or more stages, it can be dealt with by configuring the time constant of the LPF so that it can be switched in multiple stages.

[0035]

As is clear from the above description of the embodiment, in the PLL circuit of the present invention, even when the equipment using the circuit lowers the power supply voltage for the purpose of reduction of power consumption, etc. Since the factor ξ can be set to an optimum value, it is possible to lock the phase of the input signal within a constant time that is always stable.

Therefore, even when used in a frequency synthesizer circuit of a portable telephone for switching an operating voltage to reduce power consumption or a medium rotation control circuit of a portable compact disk (CD) device, a stable frequency lock can be achieved. Operation and stable rotation speed control can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer circuit configured using a PLL circuit of the present invention;

FIG. 2 is a circuit diagram of a frequency synthesizer of an embodiment configured using an IC;

FIG. 3 is a block diagram showing a general configuration of a frequency synthesizer to which a PLL circuit is applied;

FIG. 4 is a block diagram generally showing a closed-loop control system,

FIG. 5 is a circuit diagram showing a configuration of a lag filter used in the LPF.

[Explanation of symbols]

 B1, B2, 71, 72 Battery C1, C2, C3, C4, C5, C6 Capacitor D1 Diode Q1 MB87001A Q2, 2 Voltage controlled oscillator (VCO) Q3 MB501 SW1, SW2 Selector switch X1, 6 Crystal oscillator 1 LPF 3 Variable frequency divider (PD) 4 Phase comparator (PC) 5 Reference frequency generator 6 Crystal oscillator

Claims (3)

(57) [Claims] 1. A phase locked loop circuit comprising at least a phase comparison means, a low-pass filter, and a voltage controlled oscillation means on a closed loop and operating at a plurality of operation voltages, wherein A phase locked loop circuit comprising switching means for switching a time constant of a low-pass filter. 2. The phase-locked loop according to claim 1, wherein said switching means changes a connection of a capacitor which is a component of said low-pass filter for switching said time constant. circuit. 3. The phase locked loop according to claim 1, wherein said switching means changes a connection of a resistor which is a component of said low-pass filter for switching said time constant. circuit.