JPH05327490A - Pll circuit - Google Patents

Abstract

PURPOSE:To speed up the lockup time required until the phase vibration of the oscillation output is setted within a certain range when remarkably changing the oscillation frequency of the voltage control oscillator is largely changed by minimizing the charge and discharge of the time constant capacity of the loop filter of the PLL circuit concerning to the PLL circuit to be used in selection, etc., of the channel frequency of a radio equipment. CONSTITUTION:Fixed control voltages V1 and V2# to decide self-running frequencies f1 and f2# of a voltage control oscillator VCO are beforehand stored in the voltage control oscillator VCO of the PLL circuit, apart from the variable control voltage V0 of the loop filter LPF output controlling the phase vibration epsilonwithin a certain range of the oscillation frequency (f). The PLL circuit is provided with a VCO self-running frequency control voltage supply means 1 switching the respective voltages V1 and V2# to supply to the VCO at the time of largely changing the self-running frequency (f) of the voltage control oscillator VCO from a certain frequency f1 to another frequency f2#.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit which is a loop circuit for synchronizing the phase of the oscillation frequency of a voltage controlled oscillator VCO used for selecting a channel frequency of a radio device with the phase of a reference frequency signal. In the PLL circuit, generally, the characteristic after the output frequency of the voltage controlled oscillator VCO is in the steady state (steady characteristic) and the pull-in characteristic until the phase is synchronized with the reference frequency signal (synchronous characteristic) are in a mutually contradictory relationship. Therefore, for example, if the frequency pull-in range of the synchronization characteristic is widened and the synchronization speed is increased, the noise band of the loop is widened and the characteristics in the steady state are deteriorated. Also, the voltage controlled oscillator VCO
If the synchronization speed is increased when frequency modulation FM is applied to, it becomes difficult to obtain the required FM modulation degree. Enough FM
In order to secure the degree of modulation, the natural frequency ω _{n of the} loop determined by the loop system must be sufficiently lower than the lower limit of the modulation frequency. For the PLL circuit, it is desired that the lock-up time until the oscillation frequency of the voltage controlled oscillator VCO is pulled into the reference frequency signal and the phase is synchronized is shortened and the FM modulation degree is sufficient.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional PLL circuit of a radio device, which shows a characteristic of a loop when the oscillation frequency f of a voltage controlled oscillator VCO is not phase-synchronized with a reference frequency signal F and when it is phase-synchronized. The circuit system was operated by switching the frequency ω _n with a switch or the like. And when switching the channel frequency of the radio, switch the time constant CR of the loop filter LPF with a switch etc. to increase the natural frequency ω _n and speed up the lockup time.
By reducing the natural frequency ω _n , the voltage controlled oscillator VCO is FM-modulated with a sufficient degree of modulation. The operation of a switch or the like for changing the natural frequency ω _n by switching the time constant CR of the loop filter LPF is PL
Lock that indicates when the phase error ε of the output of the phase comparator PC that compares the output f of the voltage controlled oscillator VCO of the L circuit and the output F of the reference signal oscillator falls within a certain range (or deviates). It was done automatically by the signal.

[0003]

The synchronization time of the PLL is
The process can be divided into two, the frequency pulling process and the phase synchronizing process. When there is a difference from the frequency of the reference signal, first, so-called cycle slipping is performed in the frequency pulling process to reduce the frequency difference and shift to the phase synchronization process, whereby the PLL is completely synchronized. The present invention shortens the time required for the PLL frequency pulling process to speed up the lock-up time. In the conventional PLL circuit, as shown in the characteristic diagram of FIG. 5, the oscillation frequency f of the voltage-controlled oscillator VCO on the horizontal axis is, for example,
If the frequency is changed significantly from f ₁ to frequency f ₂ , the VCO on the vertical axis
The control voltage V applied to the output voltage V of the loop filter LPF that integrates the phase error ε of the output of the phase comparator PC of the PLL increases from the voltage V ₁ to the voltage V ₂ and the oscillation frequency f of the VCO f Is locked to the phase of the reference frequency signal F after changing from frequency f ₁ to frequency f ₂ . To change the oscillation frequency f of the voltage controlled oscillator VCO from frequency f ₂ to frequency f ₁ ,
The control voltage V applied to CO is reduced from voltage V ₂ to voltage V ₁ . Therefore, the capacitance C of the time constant CR of the loop filter LPF of the PLL circuit is set to the oscillation frequency of the voltage controlled oscillator VCO.
Charge and discharge are performed each time f is changed. The charge and discharge of the capacitance C of the time constant CR of this loop filter LPF is
There is a problem that when the VCO oscillation frequency f is changed, the phase is pulled into the phase of the reference signal and is fixed, that is, the lockup time is delayed. The object of the present invention is to shorten the lock-up time until the new free-running frequency is phase-locked when the oscillation frequency of the voltage-controlled oscillator VCO of the PLL is changed, and to obtain a sufficient degree of modulation when FM modulation is applied. To do so.

[0004]

The basic configuration of the present invention for achieving this object is generally a voltage controlled oscillator of a PLL circuit.
To quickly lock the phase when the VCO oscillation frequency f is changed from frequency f ₁ to frequency f ₂ , use the loop filter.
The charge / discharge of the capacity C of the time constant CR of the LPF must be minimized.For that reason, a variable control voltage for suppressing the phase fluctuation ε within a certain range applied to the VCO through the loop filter LPF is required. Paying attention to the fact that it may be constant regardless of the frequency f ₁ before switching and the frequency f ₂ after switching, and as shown in the principle diagram of FIG. 1, the voltage controlled oscillator VCO of the PLL circuit is self-running. A loop filter that integrates the variable control voltage v ₀ that controls the phase fluctuation within a certain range of the frequency f, that is, the comparison error ε of the output of the phase comparator PC that obtains the phase difference with the reference frequency signal F with the time constant circuit CR. Separately from the output voltage v _{0 of} LPF,
A fixed control voltage V _1, for determining the free-running frequency f ₁ f _{2 of}
When V ₂ ─ is stored in memory and the free-running frequency f of the VCO is changed from the frequency f ₁ to the frequency f ₂ ─, those voltages V _{1 and} V ₂ ─ are read out and switched, and the VCO self The running frequency control voltage supply means 1 is provided.

[0005]

In the present invention, the voltage controlled oscillator VCO of the PLL circuit is
Is synchronized (locked) with the control voltage (error voltage) v ₀ for phase synchronization
The control voltage for phase synchronization (error voltage)
v ₀ Apart from the control voltage V for controlling when a voltage is applied v ₀ to the phase synchronization control terminal of the VCO, the free-running oscillation frequency f of the VCO
Is stored in advance, and the free-running oscillation frequency control voltages V _{1 and} V ₂ corresponding to the frequency to be synchronized (locked) are supplied to the VCO by the free-running frequency control voltage supply means 1. Phase synchronization control voltage (error voltage) v ₀ and free-running oscillation frequency control voltage V ₁
And the VCO phase-locked (locked) at frequency f ₁ ,
When changing to the frequency f ₂ and synchronizing the phase, the newly provided free-running frequency control voltage supply means 1 changes the free-running oscillation frequency control voltage V ₂ corresponding to the frequency f ₂ stored in advance to the frequency
Change to f ₂ and apply to VCO at the same time. During this time, the control voltage (error voltage) for phase synchronization applied to the VCO through the loop filter LPF is a substantially constant voltage v ₀ regardless of the frequency f ₁ before the change and the frequency f ₂ after the change ( (Refer to the characteristic diagram of Fig. 3), so there is almost no charge / discharge of the capacitance C of the time constant CR of the loop filter LPF. Therefore, when the frequency (set frequency) of the PLL circuit is changed, at the same time when the frequency (set frequency) is changed, the free-running oscillation frequency f of the VCO oscillates at a frequency very close to the target frequency f ₁ f ₂ . Therefore, the free-running oscillation frequency f of the VCO after changing the frequency (set frequency) is pulled within a certain range by the reference frequency signal, and the time until lockup for phase synchronization becomes faster, and
When performing FM modulation, the natural frequency ω _{n of the} loop can be set low enough to obtain a sufficient degree of modulation.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the channel frequency of a radio device according to an embodiment of the present invention.
FIG. 3 is a configuration diagram of a PLL circuit for selecting a wave number, and FIG.
FIG. 7 is a characteristic diagram for explaining the operation of the PLL circuit of the example.
It Voltage control in the PLL circuit of the embodiment of FIG.
The free-running frequency control voltage supply means 1 for the oscillator VCO is
Free-running frequency f_1,f₂─ f_nFixed control voltage V that determines₁, V₂
─ to the digital data D_1,D₂─ D_nWrite as
ROM 11 to be placed and the digital data D_1,D₂─ D_n, CP
With U 10, a fixed voltage V of analog quantity₁And voltage V₂─ V_n
D / A converter that converts the voltage to VCO and supplies it to the voltage-controlled oscillator VCO 12
Composed of and. In addition, the voltage controlled oscillator VCO
Maximum value V that suppresses the phase fluctuation of frequency f within a certain range_Eof
Variable control voltage v₀Variable capacitance diode VC₁
And its free-running frequency f₁Fixed control set to
Voltage V₁And frequency f₂─ f_nFixed control voltage V set to₂─
V_nVariable-capacitance diode VC applied by switching between and
₂It is configured as a self-excited oscillator having and. Now P
The voltage controlled oscillator VCO of the LL circuit has a certain oscillation frequency f₁so
If the phase difference is locked to a certain range, the VCO
Running frequency f₁Is a fixed voltage V₁And that
The control voltage that suppresses the phase fluctuation within a certain range of_E
Variable voltage v₀Is. Oscillation frequency f in this state₁And then
Frequency f₂When changing to, switch the external frequency selection switch
Command data of frequency change to CPU 10 of PLL
Then, CPU 10 has frequency f ₁The frequency f₂To change to
Sending the ratio data to the frequency divider and free-running the VCO
Frequency f₁To f₂Voltage V to change to₂Corresponding to
Digital data D₂Read from ROM 11 to D / A converter 12
give. At this time, the frequency f₂When is set and D
Output of A / A converter 12 V₂Occur at the same time
It And the output V of D / A converter 12₂Is the VCO oscillator circuit
Variable capacitance VC₂Applied to. At this time, the PLL
Phase comparator PC produces a phase comparison with reference frequency signal F.
The loop filter LPF that integrates the phase error ε within the constant range
Output, VCO oscillator varactor diode VC
₁Variable control voltage v applied to₀Is the frequency before the change
Number f₁Since the value is almost the same as that of, the PLL circuit is
New oscillation frequency f₂Immediately into the PLL loop
I will Also, the time constant of the loop filter LPF must be changed automatically.
The frequency becomes large and the natural frequency of the loop ω_nSet low
VCO varactor diode VC₃FM modulation with
In this case, a sufficient degree of modulation can be obtained.

[0007]

As described above, according to the present invention, P
When the VCO oscillation frequency of the LL circuit is changed, a new oscillation frequency f ₂ is immediately pulled into the PLL loop and locked, so the synchronization characteristics are improved, and at the same time, a sufficient degree of modulation is obtained when FM modulation is performed in the steady state after locking. As a result, the steady-state characteristic is improved.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a PLL circuit of the present invention.

FIG. 2 is a configuration diagram of a PLL circuit for selecting a channel frequency of a wireless device according to an embodiment of the present invention.

FIG. 3 is a characteristic diagram for explaining the operation of the PLL circuit according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional PLL circuit.

FIG. 5: Characteristic diagram of conventional voltage-controlled oscillator VCO for PLL circuit

[Explanation of symbols]

1 is a VCO free-running frequency control voltage supply means, 10 is a CPU, 11
Is a ROM and 12 is a D / A converter.

Claims (1)

[Claims] 1. An oscillating frequency (f) at a control DC voltage (V)
The phase of the output frequency (f) of the voltage controlled oscillator (VCO) that is controlled is compared with the phase of the reference frequency signal (F) (PC),
Loop filter (LP) obtained by integrating the comparison error (ε)
DC voltage (V) at the output of F) is the voltage controlled oscillator (VCO)
To the reference frequency signal by controlling the output frequency (f)
In the PLL circuit that synchronizes the phase with (F), the output of the loop filter (LPF) that controls the phase fluctuation (ε) within a certain range of the oscillation frequency (f) of the voltage controlled oscillator (VCO) In addition to the control voltage (v ₀ ) of the
A fixed control voltage for determining the free running frequency (f ₁ f ₂ ─) of (O)
(V _1, V _2- ) is stored in advance and the voltage controlled oscillator (VC
When the free-running frequency (f) of (O) is changed from _one frequency (f ₁ ) to another frequency (f ₂ ─), the voltage control is performed by switching those voltages (V _1, V ₂ ─). A PLL circuit characterized by being provided with a VCO free-running frequency control voltage supply means (1) for supplying to an oscillator (VCO).