JP2005236482A - Lc oscillator - Google Patents

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JP2005236482A
JP2005236482A JP2004040943A JP2004040943A JP2005236482A JP 2005236482 A JP2005236482 A JP 2005236482A JP 2004040943 A JP2004040943 A JP 2004040943A JP 2004040943 A JP2004040943 A JP 2004040943A JP 2005236482 A JP2005236482 A JP 2005236482A
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inductor
circuit
value
amplifier
embodiment
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Hiroto Matsuda
宏人 松田
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Fujitsu Ltd
富士通株式会社
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Abstract

An LC oscillator formed on a semiconductor substrate is designed to have a low jitter characteristic even when the inductor Q value is increased by means of a circuit and is produced by an existing standard CMOS process.
A negative resistance circuit 1 and an LC resonance circuit 2 are provided. In the LC resonance circuit 2, between the resonance circuit connection nodes 21 and 22 of the negative resistance circuit 1, a capacitor circuit including the inductor 13, capacitors 17 and 18, and a Q value control circuit for increasing the Q value of the inductor 13 are arranged in parallel. Connect and configure. The Q value control circuit includes a current mirror amplifier 15 whose input terminal is connected to the resonance circuit connection node 21, a current mirror amplifier 16 whose input terminal is connected to the resonance circuit connection node 22, and the output terminals of the current mirror amplifiers 15 and 16. And an inductor 14 that is electromagnetically coupled to the inductor 13.
[Selection] Figure 1

Description

  The present invention relates to an LC oscillator formed on a semiconductor substrate.

  In recent years, in order to reduce the cost of high-frequency circuits, development of high-frequency circuits using CMOS (complementary metal oxide semiconductor) has been advanced. In a high-frequency circuit, a voltage controlled oscillator required for a PLL (phase locked loop) circuit or the like is required to have low jitter (phase fluctuation) of an output waveform.

  Conventionally, when creating an oscillator with a CMOS, a ring oscillator in which inverters are connected in a ring shape is often used. However, noise generated from a transistor increases jitter, so in a frequency band of GHz or higher, a ring oscillator is used. Instead, an LC oscillator including an LC resonance circuit composed of an inductor and a capacitor is often used.

  In the LC oscillator, the larger the Q value of the inductor and the capacitance of the LC resonance circuit, the smaller the jitter. However, when the LC oscillator is fabricated on an existing standard CMOS process on a semiconductor substrate, the wiring resistance of the inductor is large. If the wiring width is increased in order to reduce this, the wiring-to-substrate capacitance increases and the Q value decreases. There was a problem of becoming.

  Therefore, when an LC oscillator is produced by an existing standard CMOS process, some circuit device is required to increase the Q value of the inductor. However, conventionally, an LC oscillator having a low jitter characteristic has not been proposed even in the case where the Q value of the inductor is increased by a device ingenuity and the inductor is produced by an existing standard CMOS process.

Conventionally, a technique for increasing the Q value of the inductor of the filter circuit by a device on the circuit has been proposed (for example, Patent Document 1 and Non-Patent Document 1). However, these documents do not disclose an LC oscillator that has a low jitter characteristic even when the Q value of the inductor is increased by circuit improvements and is produced by an existing standard CMOS process. .
JP-A 61-280103 IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE p.275-278

  An object of the present invention is to provide an LC oscillator that has a low jitter characteristic even when the Q value of an inductor is increased by means of a circuit and is produced by an existing standard CMOS process.

  In the present invention, the LC oscillator of the first invention has a resonance circuit and a negative resistance circuit, and the resonance circuit is connected between the first and second nodes of the negative resistance circuit. And a capacitor and a Q value control circuit for increasing the Q value of the first inductor are connected in parallel, and the Q value control circuit includes a first amplifier having an input terminal connected to the first node. A phase shifter, a second amplifier / phase shifter having an input terminal connected to the second node, and an output terminal of the first and second amplifier / phase shifters; A second inductor electromagnetically coupled to the other inductor.

  In the present invention, the LC oscillator of the second invention has a resonance circuit and a negative resistance circuit, and the resonance circuit includes a predetermined node of the negative resistance circuit and a wiring that is grounded in an alternating current manner. Between the first inductor, the capacitor, and a Q value control circuit that increases the Q value of the first inductor in parallel. The Q value control circuit has an input terminal connected to the predetermined node. And a second inductor connected between the output terminal of the amplifier / phase shifter and the AC grounded wiring and electromagnetically coupled to the first inductor It is to have.

  According to the LC oscillator of the present invention, the phase difference between the input voltage and the input current of the first inductor can be set to 90 degrees by the action of the mutual inductance generated between the first and second inductors. The effective Q value of the inductor can theoretically be infinite. Therefore, even in the case where the standard CMOS process is used, in the case of the first invention, complementary jitter signals with low jitter can be obtained at the first and second nodes. In some cases, an oscillation signal with low jitter can be obtained at a predetermined node.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, 1 is a negative resistance circuit, 2 is an LC resonance circuit, and 3 and 4 are oscillation signal output terminals to which complementary oscillation signals SOUT and / SOUT are output.

  In the negative resistance circuit 1, 5 is a power supply line, 6 is a ground line, 7 and 8 are CMOS inverters, 9 and 10 are pMOS transistors, and 11 and 12 are nMOS transistors. That is, the negative resistance circuit 1 has a differential amplifier configuration in which CMOS inverters 7 and 8 are cross-connected.

  In the LC resonance circuit 2, reference numerals 13 and 14 denote inductors spirally formed on a semiconductor substrate so as to be electromagnetically coupled, and reference numerals 15 and 16 denote amplifiers and phase shifters that function as amplifiers and phase shifters. The current mirror amplifiers 17 and 18 are fixed capacitors having the same configuration and the same capacitance value. The inductor 14 and the current mirror amplifiers 15 and 16 constitute a Q value control circuit that increases the Q value of the inductor 13.

  In other words, the LC resonance circuit 2 includes an inductor 13 and a Q value control circuit in which an inductor 14 electromagnetically coupled to the inductor 13 is sandwiched between current mirror amplifiers 15 and 16 having the same circuit configuration, and a fixed capacitance having the same configuration and the same capacitance value. 17 and 18 are connected in parallel, and end portions 19 and 20 are connected to resonance circuit connection nodes 21 and 22 of the negative resistance circuit 1.

  FIG. 2 is a schematic configuration diagram of the inductors 13 and 14. In the first embodiment of the present invention, the inductors 13 and 14 are formed so as to overlap different layers above a semiconductor substrate (not shown) via an insulating layer (not shown). In this way, an increase in chip area can be suppressed. In FIG. 2, the inductors 13 and 14 have a single structure, but can have a structure of a double structure or more.

  FIG. 3 is a circuit diagram showing the configuration of the current mirror amplifiers 15 and 16. In the current mirror amplifier 15, reference numeral 23 denotes a power line, 24 denotes a ground line, 25 denotes an nMOS transistor serving as a driving element, and 26 and 27 denote pMOS transistors constituting a current mirror circuit.

  In the current mirror amplifier 16, 28 is a power supply line, 29 is a ground line, 30 is an nMOS transistor that forms a drive element, and 31 and 32 are pMOS transistors that form a current mirror circuit.

  The nMOS transistors 25 and 30 have the same size, the pMOS transistors 26 and 31 have the same size, the pMOS transistors 27 and 32 have the same size, and the current mirror amplifiers 15 and 16 have the same amplification factor and the same phase shift amount. It is supposed to have.

FIG. 4 is an equivalent circuit diagram of a portion on one side of the midpoint between the inductors 13 and 14. However, the resistance value and self-inductance of the half part of the inductor 13 are R 1 and L 1 , respectively, and the resistance value and self-inductance of the half part of the inductor 14 are R 2 and L 2 , respectively, and the half part of the inductor 13 and the inductor The mutual inductance of the half of 14 is represented by M.

Here, considering only the AC component, if the voltage at the end of the inductor 13 (input voltage) is v 1 , the current flowing through the inductor 13 (input current) is i 1 , and the current flowing through the inductor 14 (input current) is i 2. ,

It becomes. If the amplification factor from i 1 to i 2 is m 0 and the phase difference between i 1 and i 2 is θ,

Therefore, if formula (2) is substituted into formula (1),

It becomes. Therefore, from the equation (3), the input impedance Z in = v 1 / i 1 viewed from the end of the inductor 13 is

It becomes.

On the other hand, considering only the AC component of the current mirror amplifier 15, since the input terminal IN is connected to the inductor 13, the voltage at the input terminal IN is v 1 , and the output terminal OUT is connected to the inductor 14. The current flowing through the pMOS transistor 27 is i 2 .

Here, assuming that the transconductance of the nMOS transistor 25 is gm 1 and the transconductances of the pMOS transistors 26 and 27 are gm 2 and gm 3 , respectively, the current flowing through the nMOS transistor 25 is gm 1 · v 1 . Therefore, the current i 2 flowing through the pMOS transistor 27 is

It becomes. Substituting equation (2) into equation (5),

It becomes. When comparing the real part and the imaginary part on the right side of Expression (4) and Expression (6),

It becomes. From the equations (7A) and (7B), m 0 · sin θ is obtained.

It becomes. In a transistor fabricated by a CMOS process, g m2 / g m1 g m3 is on the order of 10 3 , and ωM is on the order of 10 1 , so the second term in the denominator and the first term in the numerator are Since it can be ignored, approximately

Holds. The Q value becomes maximum (theoretically infinite) when the real part becomes zero in Equation (4).

It becomes. From Equation (9) and Equation (10),

It becomes. That is, by adjusting the size (g m1 , g m2 , g m3 ) of the nMOS transistor 25 and the pMOS transistors 26 and 27 so that m 0 · sin θ satisfies the equation (10), the half portion of the inductor 13 is lost. It is an ideal inductor without any. This is also true for the current mirror amplifier 16.

  As described above, according to the first embodiment of the present invention, the phase difference between the input voltage and the input current of the inductor 13 is set to 90 degrees by the action of the mutual inductance M generated between the inductors 13 and 14, and effective. The Q value of the inductor 13 can theoretically be infinite. Therefore, even when the conventional standard CMOS process is used, low jitter complementary oscillation signals SOUT and / SOUT can be obtained.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a second embodiment of the present invention. The second embodiment of the present invention is provided with an LC resonance circuit 33 having a circuit configuration different from that of the LC resonance circuit 2 shown in FIG. 1, and the other configurations are the same as those of the first embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 33 is configured by connecting the intermediate points 13C and 14C of the inductors 13 and 14 with a conductive layer 34, and the others are configured similarly to the LC resonance circuit 2 shown in FIG. FIG. 6 is a schematic configuration diagram of the inductors 13 and 14.

  According to the second embodiment of the present invention, the same effects as those of the first embodiment of the present invention shown in FIG. 1 can be obtained, and the intermediate points 13C and 14C of the inductors 13 and 14 are connected to each other by the conductive layer 34. Since they are connected, the voltage amplitude at the inductor 14 does not exceed the power supply voltage VDD, the destruction of the pMOS transistors 27 and 32 constituting the current mirror amplifiers 15 and 16 can be prevented, and the reliability can be improved. .

(Third embodiment)
FIG. 7 is a circuit diagram showing a third embodiment of the present invention. The third embodiment of the present invention is provided with an LC resonance circuit 35 having a circuit configuration different from that of the LC resonance circuit 2 shown in FIG. 1, and the other configurations are the same as those of the first embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 35 is grounded at the intermediate point 14C of the inductor 14, and is otherwise configured in the same manner as the LC resonance circuit 2 shown in FIG.

  According to the third embodiment of the present invention, the same effect as that of the first embodiment of the present invention shown in FIG. 1 can be obtained, and the intermediate point 14C of the inductor 14 is grounded. The voltage amplitude does not exceed the power supply voltage VDD, the destruction of the pMOS transistors 27 and 32 constituting the current mirror amplifiers 15 and 16 can be prevented, and the reliability can be improved.

(Fourth embodiment)
FIG. 8 is a circuit diagram showing a fourth embodiment of the present invention. The fourth embodiment of the present invention is provided with an LC resonance circuit 36 having a circuit configuration different from that of the LC resonance circuit 2 shown in FIG. 1, and the others are configured in the same manner as the first embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 36 is provided with two symmetrical inductors 37 and 38 having the same self-inductance connected in series instead of the inductor 13, and has a self-inductance connected in series instead of the inductor 14. The same two symmetrical symmetrical inductors 39 and 40 are provided, and the others are configured similarly to the LC resonance circuit 2 shown in FIG.

  In the fourth embodiment of the present invention, the inductors 37 and 39 are electromagnetically coupled, and the inductors 37 and 39 constitute a first mutual induction circuit, and the inductors 38 and 40 are electromagnetically coupled. A second mutual induction circuit having the same mutual inductance as that of the first mutual induction circuit is configured.

  According to the fourth embodiment of the present invention, the same effect as that of the first embodiment of the present invention shown in FIG. 1 can be obtained, and the inductors 13 and 14 are divided into two inductors 37 to 40, respectively. Therefore, even if each of the inductors 37 to 40 is an asymmetric inductor, the entire circuit can be easily made symmetrical, and the duty characteristics of the complementary oscillation signals SOUT and / SOUT can be improved. .

  Note that the connection midpoint 41 of the inductors 37 and 38 and the connection midpoint 42 of the inductors 39 and 40 may be connected, or the connection midpoint 42 of the inductors 39 and 40 may be grounded.

(Fifth embodiment)
FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention. The fifth embodiment of the present invention is provided with an LC resonance circuit 43 having a circuit configuration different from that of the LC resonance circuit 2 shown in FIG. 1, and the other configurations are the same as those of the first embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 43 is provided with variable capacitors 44 and 45 that can change the capacitance value by the oscillation frequency control voltage VC instead of the fixed capacitors 17 and 18 and have the same capacitance value. 1 is configured in the same manner as the LC resonance circuit 2 shown in FIG.

  For example, the variable capacitors 44 and 45 connect the source and drain of an nMOS transistor, use the gate as the first electrode, the source and drain as the second electrode, and apply the oscillation frequency control voltage VC to the second electrode. Can be configured.

  According to the fifth embodiment of the present invention, the same operational effects as the first embodiment of the present invention shown in FIG. 1 can be obtained, and the variable capacitors 44 and 45 are provided. It can be used in a PLL circuit or the like.

  As in the second embodiment of the present invention, the midpoints 13C and 14C of the inductors 13 and 14 are connected to each other, or the midpoint 14C of the inductor 14 is grounded as in the third embodiment of the present invention. You may make it do.

(Sixth embodiment)
FIG. 10 is a circuit diagram showing a sixth embodiment of the present invention. In the sixth embodiment of the present invention, an LC resonance circuit 46 having a circuit configuration different from that of the LC resonance circuit 36 shown in FIG. 8 is provided, and the others are configured similarly to the fourth embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 46 is provided with variable capacitors 44 and 45 that can change the capacitance value by the oscillation frequency control voltage VC instead of the fixed capacitors 17 and 18 and have the same capacitance value. The configuration is the same as that of the LC resonance circuit 36 shown in FIG.

  For example, the variable capacitors 44 and 45 connect the source and drain of an nMOS transistor, use the gate as the first electrode, the source and drain as the second electrode, and apply the oscillation frequency control voltage VC to the second electrode. Can be configured.

  According to the sixth embodiment of the present invention, the same effect as that of the fourth embodiment of the present invention can be obtained, and the variable capacitors 44 and 45 are provided. Can be used.

  Note that the connection midpoint 41 of the inductors 37 and 38 and the connection midpoint 42 of the inductors 39 and 40 may be connected, or the connection midpoint 42 of the inductors 39 and 40 may be grounded.

(Seventh embodiment)
FIG. 11 is a circuit diagram showing a seventh embodiment of the present invention. In the seventh embodiment of the present invention, an LC resonance circuit 47 having a circuit configuration different from that of the LC resonance circuit 43 shown in FIG. 9 is provided, and the others are configured similarly to the fifth embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 47 is provided with variable capacitors 48 and 49 whose capacitance values are variable by the oscillation frequency band control voltage VB and having the same capacitance value. The other components are the same as those of the LC resonance circuit 43 shown in FIG. It is constituted similarly.

  For example, the variable capacitors 48 and 49 connect the source and drain of an nMOS transistor, use the gate as the first electrode, the source and drain as the second electrode, and apply the oscillation frequency band control voltage VB to the second electrode. It can be constituted as follows.

  According to the seventh embodiment of the present invention, the same effect as the fifth embodiment of the present invention shown in FIG. 9 can be obtained, and the oscillation frequency band can be switched by the oscillation frequency band control voltage VB. It can be highly convenient.

  As in the second embodiment of the present invention, the midpoints 13C and 14C of the inductors 13 and 14 are connected to each other, or the midpoint 14C of the inductor 14 is grounded as in the third embodiment of the present invention. You may make it do.

(Eighth embodiment)
FIG. 12 is a circuit diagram showing an eighth embodiment of the present invention. In the eighth embodiment of the present invention, an LC resonance circuit 50 having a circuit configuration different from that of the LC resonance circuit 46 shown in FIG. 10 is provided, and the others are configured similarly to the sixth embodiment of the present invention shown in FIG. It is.

  The LC resonance circuit 50 is provided with variable capacitors 48 and 49 whose capacitance values are variable by the oscillation frequency band control voltage VB and having the same capacitance value. The other components are the same as those of the LC resonance circuit 46 shown in FIG. It is constituted similarly.

  For example, the variable capacitors 48 and 49 connect the source and drain of an nMOS transistor, use the gate as the first electrode, the source and drain as the second electrode, and apply the oscillation frequency band control voltage VB to the second electrode. It can be constituted as follows.

  According to the eighth embodiment of the present invention, it is possible to obtain the same effect as that of the sixth embodiment of the present invention shown in FIG. 10, and the frequency band can be switched by the oscillation frequency band control voltage VB. It can be made highly.

  Note that the connection midpoint 41 of the inductors 37 and 38 and the connection midpoint 42 of the inductors 39 and 40 may be connected, or the connection midpoint 42 of the inductors 39 and 40 may be grounded.

  In the first to eighth embodiments of the present invention, the current mirror amplifiers 15 and 16 are provided as amplifiers / phase shifters, but instead of the current mirror amplifier 15 as shown in FIG. The amplifier 51 and the phase shifter 52 are connected in cascade to form a first amplifier / phase shifter, and instead of the current mirror amplifier 16, the amplifier 53 and the phase shifter 54 are connected in cascade to form a second amplifier. -You may make it comprise a phase shifter.

(Ninth embodiment)
FIG. 14 is a circuit diagram showing a ninth embodiment of the present invention. The ninth embodiment of the present invention is provided with an LC resonance circuit 55 having a circuit configuration different from that of the LC resonance circuit 2 shown in FIG. 1, and the other configurations are the same as those of the first embodiment of the present invention.

  The LC resonance circuit 55 is provided with current mirror amplifiers 56 and 57 having a circuit configuration different from that of the current mirror amplifiers 15 and 16 shown in FIG. 1, and the other configurations are the same as those of the LC resonance circuit 2 shown in FIG. .

  FIG. 15 is a circuit diagram showing the configuration of the current mirror amplifiers 56 and 57. The current mirror amplifier 56 includes pMOS transistors 58 and 59, and the others are configured in the same manner as the current mirror amplifier 15 shown in FIG.

  The pMOS transistor 58 constitutes a current mirror circuit together with the pMOS transistors 26 and 27, and the pMOS transistor 59 functions as a switching element whose on / off is controlled by the control signal VD.

  The current mirror amplifier 57 includes pMOS transistors 60 and 61, and the others are configured in the same manner as the current mirror amplifier 16 shown in FIG. The pMOS transistor 60 constitutes a current mirror circuit together with the pMOS transistors 31 and 32 and has the same size as the pMOS transistor 58. The pMOS transistor 61 functions as a switch element that is controlled to be turned on / off by the control signal VD.

  According to the ninth embodiment of the present invention, the same effect as that of the first embodiment of the present invention can be obtained, and the on / off of the pMOS transistors 59 and 61 is controlled by the control voltage VD, whereby the current The characteristics of the mirror amplifiers 56 and 57 can be changed, that is, the amplitude and phase of the current flowing through the inductor 14 can be changed, and the jitter characteristics can be optimized by the control voltage VD.

  As in the second embodiment of the present invention, the midpoints 13C and 14C of the inductors 13 and 14 are connected to each other, or the midpoint 14C of the inductor 14 is grounded as in the third embodiment of the present invention. You may make it do.

  Moreover, you may make it comprise the inductors 13 and 14 by the two inductors 37-40 similarly to 4th Embodiment of this invention. In this case, the connection midpoint 41 of the inductors 37 and 38 and the connection midpoint 42 of the inductors 39 and 40 may be connected, or the connection midpoint 42 of the inductors 39 and 40 may be grounded.

  Further, instead of the fixed capacitors 17 and 18, the capacitance value can be changed by the oscillation frequency control voltage VC, and the variable capacitors 44 and 45 having the same capacitance value may be provided. Similarly to the seventh and eighth embodiments of the present invention, variable capacitors 48 and 49 having MOS structures of the same size whose capacitance value is variable by the oscillation frequency band control voltage VB may be provided.

  Further, instead of the current mirror amplifier, an amplifier / phase shifter may be configured by cascading an amplifier and a phase shifter. In this case, the amplifier may be a variable amplifier whose gain can be varied by a control signal, and the phase shifter may be a variable shifter whose phase shift amount can be varied by a control signal.

(10th Embodiment)
FIG. 16 is a circuit diagram showing a tenth embodiment of the present invention. In FIG. 16, 62 is a negative resistance circuit, 63 is an LC resonance circuit, and 64 is an oscillation signal output terminal from which an oscillation signal SOUT is output.

  In the negative resistance circuit 62, 65 is a power supply line, 66 is a ground line, 67 and 68 are CMOS inverters, 69 and 70 are pMOS transistors, and 71 and 72 are nMOS transistors.

  73 and 74 are inductors formed in a spiral shape on the semiconductor substrate so as to be electromagnetically coupled, 75 is an amplifier, 76 is a phase shifter, 77 is a fixed capacitor, and 78 is a ground line. The inductor 74, the amplifier 75, and the phase shifter 76 constitute a Q value control circuit that increases the Q value of the inductor 73.

  In the LC resonance circuit 63, 79 and 80 are spirally formed inductors on the semiconductor substrate so as to be electromagnetically coupled, 81 is an amplifier, 82 is a phase shifter, 83 is a fixed capacitor, and 84 is a ground line. The inductor 80, the amplifier 81, and the phase shifter 82 constitute a Q value control circuit that increases the Q value of the inductor 79.

  According to the tenth embodiment of the present invention, the phase difference between the input voltage and the input current of the inductors 73 and 79 is set to 90 degrees by the action of the mutual inductance generated between the inductors 73 and 74 and between the inductors 79 and 80. , 79 can be theoretically infinite. Therefore, the low jitter oscillation signal SOUT can be obtained even when an existing standard CMOS process is used and a non-symmetrical inductor is used.

(Eleventh embodiment)
FIG. 17 is a circuit diagram showing an eleventh embodiment of the present invention. In FIG. 17, 85 is a negative resistance circuit, 86 is an LC resonance circuit, and 87 is an oscillation signal output terminal from which an oscillation signal SOUT is output.

  In the negative resistance circuit 85, 88 is a power supply line, 89 is a ground line, 90 and 91 are CMOS inverters, 92 and 93 are pMOS transistors, and 94 and 95 are nMOS transistors.

  Reference numerals 96 and 97 denote inductors spirally formed on the semiconductor substrate so as to be electromagnetically coupled, 98 an amplifier, 99 a phase shifter, 100 a fixed capacitor, and 101 a power line. The inductor 97, the amplifier 98, and the phase shifter 99 constitute a Q value control circuit that increases the Q value of the inductor 96.

  In the LC resonance circuit 86, reference numerals 102 and 103 denote inductors spirally formed on a semiconductor substrate so as to be electromagnetically coupled, reference numeral 104 denotes an amplifier, reference numeral 105 denotes a phase shifter, and reference numeral 106 denotes a fixed capacitor. The inductor 103, the amplifier 104, and the phase shifter 105 constitute a Q value control circuit that increases the Q value of the inductor 102.

  According to the eleventh embodiment of the present invention, the phase difference between the input voltage and the input current of the inductors 96 and 102 is set to 90 degrees by the action of the mutual inductance generated between the inductors 96 and 97 and between the inductors 102 and 103. , 102 can be theoretically infinite. Therefore, even if the current standard CMOS process is used, and even if the inductors 96, 97, 102, and 103 are not symmetrical inductors, the low jitter oscillation signal SOUT can be obtained.

  In the tenth and eleventh embodiments of the present invention, an amplifier and a phase shifter are provided as an amplifier / phase shifter. Instead, a current mirror as shown in FIG. 3 or FIG. An amplifier may be provided.

  Here, when the LC oscillator of the present invention is arranged, the LC oscillator of the present invention includes the following LC oscillators.

(Additional remark 1) It has a resonance circuit and a negative resistance circuit, The said resonance circuit has a 1st inductor, a capacity | capacitance, and said 1st between the 1st, 2nd nodes of the said negative resistance circuit. A Q value control circuit for increasing the Q value of the inductor is connected in parallel. The Q value control circuit includes a first amplifier / phase shifter having an input terminal connected to the first node, and an input terminal. A second amplifier / phase shifter connected to the second node and a second amplifier coupled between the output terminals of the first and second amplifier / phase shifters and electromagnetically coupled to the first inductor. Having an inductor.

(Supplementary note 2) The LC oscillator according to supplementary note 1, wherein intermediate points of the first and second inductors are connected to each other.

(Supplementary note 3) The LC oscillator according to supplementary note 1, wherein an intermediate point of the second inductor is grounded.

(Supplementary note 4) The LC oscillator according to supplementary note 1, wherein the first and second inductors are configured to overlap with each other via an insulating layer.

(Supplementary note 5) The LC oscillator according to supplementary note 1, wherein each of the first and second inductors includes a plurality of inductors.

(Supplementary note 6) The LC oscillator according to supplementary note 1, wherein the capacitance is a variable capacitance whose capacitance value can be varied by an oscillation frequency control voltage.

(Supplementary note 7) The LC oscillator according to supplementary note 1, wherein the resonance circuit is further connected in parallel with a variable capacitor whose capacitance value is variable by an oscillation frequency band control voltage.

(Supplementary note 8) The LC according to supplementary note 1, wherein the first and second amplifier / phase shifters are capable of controlling an amplitude or a phase of a current flowing through the second inductor by an external signal. Oscillator.

(Supplementary note 9) The LC oscillator according to supplementary note 1, wherein the first inductor, the Q value control circuit, and the capacitor have symmetrical structures.

(Supplementary Note 10) A resonance circuit and a negative resistance circuit, wherein the resonance circuit includes a first inductor between a predetermined node of the negative resistance circuit and a wiring grounded in an alternating current manner. A capacitor and a Q value control circuit for increasing the Q value of the first inductor are connected in parallel, and the Q value control circuit includes an amplifier / phase shifter having an input terminal connected to the predetermined node; An LC oscillator connected between the output terminal of the amplifier / phase shifter and the AC grounded wiring and having a second inductor electromagnetically coupled to the first inductor .

1 is a circuit diagram showing a first embodiment of the present invention. It is a schematic block diagram of the 1st, 2nd inductor with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the 1st, 2nd current mirror amplifier with which 1st Embodiment of this invention is provided. FIG. 3 is an equivalent circuit diagram of a portion on one side of an intermediate point between the first and second inductors included in the first embodiment of the present invention. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a schematic block diagram of the 1st, 2nd inductor with which 2nd Embodiment of this invention is provided. It is a circuit diagram which shows 3rd Embodiment of this invention. It is a circuit diagram which shows 4th Embodiment of this invention. It is a circuit diagram which shows 5th Embodiment of this invention. It is a circuit diagram which shows 6th Embodiment of this invention. It is a circuit diagram which shows 7th Embodiment of this invention. It is a circuit diagram which shows 8th Embodiment of this invention. It is a circuit diagram which shows the other structural example of the 1st, 2nd amplifier and phase shifter with which this invention is provided. It is a circuit diagram which shows 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the 1st, 2nd current mirror amplifier with which 9th Embodiment of this invention is provided. It is a circuit diagram which shows 10th Embodiment of this invention. It is a circuit diagram which shows 11th Embodiment of this invention.

Explanation of symbols

3, 4 ... Oscillation output terminals 13, 14 ... Inductors 17, 18 ... Fixed capacitors 37-40 ... Inductors 44, 45 ... Variable capacitors 48, 49 ... Variable capacitors 64 ... Oscillation signal output terminals 73, 74 ... Inductors 77 ... Fixed capacitors 79, 80 ... Inductor 83 ... Fixed capacity 87 ... Oscillation signal output terminal 96, 97 ... Inductor 100 ... Fixed capacity 102, 103 ... Inductor 106 ... Fixed capacity

Claims (5)

  1. It has a resonance circuit and a negative resistance circuit,
    In the resonant circuit, a first inductor, a capacitor, and a Q value control circuit for increasing the Q value of the first inductor are connected in parallel between the first and second nodes of the negative resistance circuit. Configured,
    The Q value control circuit includes a first amplifier / phase shifter having an input terminal connected to the first node, a second amplifier / phase shifter having an input terminal connected to the second node, An LC oscillator comprising a second inductor connected between output terminals of the first and second amplifier / phase shifters and electromagnetically coupled to the first inductor.
  2.   2. The LC oscillator according to claim 1, wherein the capacitor is a variable capacitor whose capacitance value can be varied by an oscillation frequency control voltage.
  3.   2. The LC oscillator according to claim 1, wherein the resonance circuit further includes a variable capacitor whose capacitance value is variable by an oscillation frequency band control voltage.
  4.   2. The LC oscillator according to claim 1, wherein the first and second amplifying / phase shifting devices are capable of controlling an amplitude or a phase of a current flowing through the second inductor by a control signal.
  5. It has a resonance circuit and a negative resistance circuit,
    The resonant circuit has a first inductor, a capacitance, and a Q value that increases a Q value of the first inductor between a predetermined node of the negative resistance circuit and a wiring that is AC-grounded. Consists of value control circuits connected in parallel,
    The Q value control circuit is connected between an amplifier / phase shifter having an input terminal connected to the predetermined node, and an output terminal of the amplifier / phase shifter and the AC grounded wiring, An LC oscillator comprising a second inductor electromagnetically coupled to the first inductor.
JP2004040943A 2004-02-18 2004-02-18 Lc oscillator Pending JP2005236482A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100760196B1 (en) 2005-12-08 2007-09-20 한국전자통신연구원 LC Resonance Voltage-Controlled Oscillator with Adjustable Negative Resistance Cell for Multi-band
JP2008042275A (en) * 2006-08-01 2008-02-21 Univ Chuo Lc oscillation circuit
JP2014506102A (en) * 2011-02-18 2014-03-06 クアルコム,インコーポレイテッド Varactorless Tunable Oscillator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0377360A (en) * 1989-08-18 1991-04-02 Mitsubishi Electric Corp Semiconductor device
JPH05327490A (en) * 1992-05-25 1993-12-10 Fujitsu Ltd Pll circuit
JPH11330366A (en) * 1998-03-06 1999-11-30 Internatl Business Mach Corp <Ibm> Method and apparatus for formation of improved inductor for electronic oscillator
JP2001352218A (en) * 2000-06-09 2001-12-21 Nippon Telegr & Teleph Corp <Ntt> Voltage-controlled oscillator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0377360A (en) * 1989-08-18 1991-04-02 Mitsubishi Electric Corp Semiconductor device
JPH05327490A (en) * 1992-05-25 1993-12-10 Fujitsu Ltd Pll circuit
JPH11330366A (en) * 1998-03-06 1999-11-30 Internatl Business Mach Corp <Ibm> Method and apparatus for formation of improved inductor for electronic oscillator
JP2001352218A (en) * 2000-06-09 2001-12-21 Nippon Telegr & Teleph Corp <Ntt> Voltage-controlled oscillator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100760196B1 (en) 2005-12-08 2007-09-20 한국전자통신연구원 LC Resonance Voltage-Controlled Oscillator with Adjustable Negative Resistance Cell for Multi-band
US7554416B2 (en) 2005-12-08 2009-06-30 Electronics And Telecommunications Research Institute Multi-band LC resonance voltage-controlled oscillator with adjustable negative resistance cell
JP2008042275A (en) * 2006-08-01 2008-02-21 Univ Chuo Lc oscillation circuit
JP2014506102A (en) * 2011-02-18 2014-03-06 クアルコム,インコーポレイテッド Varactorless Tunable Oscillator

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