JP2842847B2 - PLL synthesizer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a PLL (Phas).
e-Locked Loop) circuit, especially PLL
The frequency characteristics of a synthesizer circuit are wide
For example, a television having a wide reception frequency range (hereinafter referred to as TV)
The present invention relates to a PLL synthesizer circuit for a receiver tuner.

[0001]

2. Description of the Related Art A PLL circuit has one oscillator.
This circuit detects the phase difference and controls the oscillator by feedback so that the frequency and phase of the oscillator match the frequency and phase of an external input signal.

Recently, a PLL synthesizer type tuner is often used as a tuner of a TV receiver. this is,
This is because the PLL synthesizer does not require a mechanical contact that causes a failure, and is small in size and easy in remote control.

An example of a conventional PLL synthesizer circuit used in a tuner for a TV receiver of this type is shown in FIG. 7 as a first conventional example.

A first prior art example of the PLL synthesizer circuit shown in FIG. 7 is a crystal oscillator 1 which is a reference oscillator for generating a reference signal S having a reference frequency fs, a reference signal S and a divided signal D (described later). Phase comparison circuit (PD) 2 that compares the phases of the signals and outputs positive and negative phase difference signals PDU and PDD.
And a charge pump circuit (CP) 3 that outputs a charge pump signal P in response to the supply of each of the phase difference signals PDU and PDD, and removes high-frequency components of the charge pump signal P, that is, smoothes the charge pump signal P. Low-pass filter (LPF) 4 that outputs the oscillated oscillation control signal CC
And the oscillation frequency f0 in response to the supply of the oscillation control signal CC.
Controlled oscillator (V) for generating an oscillation signal VO for controlling
CO) 5, a programmable frequency divider 6 that divides the oscillation signal VO by the frequency division ratio N set by the frequency division ratio setting data DF to generate a frequency divided signal D having a frequency f0 / N, and an external An input interface 7 for generating frequency division ratio setting data DF in response to supply of frequency setting data MF from a microcomputer or the like.

Next, the operation of the PLL synthesizer circuit shown in FIG. 7 will be described. This PLL synthesizer circuit is a circuit that sets a desired frequency f0 to be output with frequency setting data MF and controls an oscillation signal VO of the voltage controlled oscillator 5 so that the phases of the reference signal S and the frequency-divided signal D match. is there.

The phase comparison circuit 2 compares the phase of the reference signal S with the phase of the frequency-divided signal D. If the phase of the frequency-divided signal D is behind the phase of the reference signal S, a positive phase difference signal PDU is output. If it has advanced, a negative phase difference signal PDD is generated and supplied to the charge pump circuit 3. The charge pump circuit 3
Positive if the supplied phase difference signal is a PDU, PDD
In this case, a charge pump signal P, which is a negative DC signal, is generated and supplied to the low-pass filter 4. The low-pass filter 4 smoothes the charge pump signal P, outputs an oscillation control signal CC, and supplies the oscillation control signal CC to the voltage-controlled oscillator 5. The voltage control oscillator 5 generates an oscillation signal VO that controls the oscillation frequency f0 in accordance with the voltage level of the oscillation control signal CC, outputs the oscillation signal VO to the outside, and supplies the oscillation signal VO to the programmable frequency divider 6. In this case, when the voltage of the oscillation control signal CC is high, the frequency is high, and when the voltage is low, the frequency is low.
In the programmable frequency divider 6, the frequency division ratio N is set by the frequency division ratio data DF from the input interface 7, and in response to the supply of the oscillation signal VO, the frequency division of the frequency f0 / N substantially equal to the reference frequency fs. Generate signal D. In this way, control is performed so that the phase difference between the frequency fs and the frequency f0 / N becomes zero. After the frequency is locked,
Neither of the phase difference signals PDU and PDD is output, and the output of the charge pump circuit 3 is in a high impedance state.

Important factors that determine the operating characteristics of this type of PLL synthesizer circuit include frequency stabilization time (lock time) at the time of channel switching (frequency switching) and carrier noise (C / N) indicating the signal purity of the voltage controlled oscillator. ).

In order to improve both the lock time and carrier noise characteristics at the same time, a method disclosed in
No. 13726 (hereinafter referred to as a second conventional example) has been proposed, and is described with reference to FIG.

In a second conventional example, in a charge pump circuit of a PLL circuit, external resistors R1 and R2 having different resistance values are connected to a constant current type charge pump circuit 9 and charge is performed by selecting these external resistors. It has a configuration for controlling the magnitude of the pump signal P. Then, in order to switch the external resistance, the phase difference signals PDU and PDD output from the phase comparison circuit 2 are input to a lock detection circuit (LD) 11, which locks the two phase difference signals PDU and P.
DD detects whether or not the frequency is locked, and selects one of the external resistors according to the state. The resistance value of the external resistor satisfies R2> R1.
1 is selected, and R2 is selected after lock-up. When R1 is selected, the current of the charge pump signal P increases to speed up lockup, and when R2 is selected, the current decreases to increase stability (that is, a slight error signal is generated in the phase comparison circuit). However, since the output fluctuation of the low-pass filter is small, the fluctuation of the lock frequency is also small.)

[0010]

However, for example, a PLL synthesizer circuit of a tuner for a TV receiver has a T
Since the V channel needs to cover the VHF band to the UHF band, the corresponding frequency band is wider than the frequency range used in a general communication PLL synthesizer circuit.
It ranges from about 80-930 MHz. Therefore, the first
Using a PLL synthesizer circuit as in the conventional example of
High frequency band (UHF band) and low frequency band (VHF band)
Are large, and the lock time and the C / N characteristic are different. More specifically, since the frequency is higher in the UHF band than in the VHF band, it is necessary to increase the frequency division ratio. As a result, the loop gain decreases, and the voltage of the varactor diode itself, which is the tuning element of the voltage controlled oscillator, is reduced. The nonlinear effect of the capacitance characteristic occurs, and the value of the lock time or the like changes between the UHF and VHF bands. As is well known, both the lock time and the C / N characteristics are determined by the damping factor of the PLL circuit.

Further, even if the second conventional example in which high-speed switching is performed before lock-up and noise characteristics are improved after lock-up is used, since there is no characteristic compensation capability corresponding to the frequency, the loop gain is not affected. Can't respond.

[0012]

The main structure of a PLL synthesizer circuit according to the present invention is that a frequency setting data for setting an output frequency is input, a voltage controlled oscillator for generating the output frequency, and an oscillation frequency of the voltage controlled oscillator. In a PLL synthesizer circuit including at least a charge pump circuit that generates a charge pump current for controlling the charge pump current, a current value of the charge pump current of the charge pump circuit is adjusted based on frequency setting data.
To adjust the charge pump current, control data is generated by selecting a plurality of bits from the input frequency setting data, and the current values of the charge pump currents corresponding to the number of bits of the control data are adjusted. A charge pump current control circuit is used.

The PLL synthesizer circuit according to the present invention comprises:
Specifically, an input section to which frequency setting data for setting an output frequency is input, a reference oscillator for generating a reference frequency, a voltage controlled oscillator for generating an oscillation signal for controlling the output frequency, an oscillation signal, A frequency divider that receives frequency setting data and generates a frequency-divided signal by dividing the oscillation signal to the value of the reference frequency, and a phase comparison that generates a phase difference signal by comparing the phase of the frequency-divided signal with the reference frequency A PLL synthesizer circuit comprising a circuit and a charge pump circuit for generating a charge pump current for controlling an output frequency of a voltage controlled oscillator by a phase difference signal, wherein control data is generated from frequency setting data, and a charge pump is generated based on the control data. A charge pump current control circuit for generating a charge pump current control signal for controlling a current is further provided. The input unit generates frequency division ratio setting data for setting the frequency division ratio of the frequency divider from the frequency setting data, outputs the data to the frequency divider, and further selects a plurality of bits from the frequency division ratio setting data. It is output to the charge pump current control circuit as control data. The charge pump current control signal is generated by a number of current sources corresponding to the number of bits of the control data.

[0014]

Embodiments of the present invention will be described below.

FIG. 1A shows an embodiment of a PLL synthesizer circuit according to the present invention. The same components as those of the conventional example shown in FIG.

The embodiment shown in FIG. 1A includes a crystal oscillator 1, a phase comparison circuit 2, a low-pass filter LPF 4, a voltage controlled oscillator 5, and a programmable frequency divider 6, as in the conventional example shown in FIG. However, the charge pump circuit 3A, the input interface 7A, and the charge pump current control circuit 8 have a configuration unique to the present embodiment. First, these three circuits will be briefly described. The input interface 7A receives the input frequency setting data MF
Are selected as control bits and output to the charge pump current control circuit 8 as control data EF. The charge pump current control circuit 8 outputs a charge pump control current PF of a predetermined magnitude in accordance with the input control data EF, and the charge pump circuit 3A compares the phase with the charge pump control current PF. Charge pump signal P based on phase difference signals PDU and PDD from circuit 2
To control the current level. That is, in the present embodiment,
The charge pump signal P is controlled by the frequency setting data MF.

FIG. 1B is a block diagram of a TV receiver according to the present embodiment. In the PLL synthesizer circuit 100 of the present embodiment, the portion excluding the crystal oscillator 1 in FIG. 1A is arranged on one chip. This PLL synthesizer circuit 100 receives a reference frequency from an external crystal oscillator 1 via a reference input terminal Ir, and outputs a PLL signal from a controller 101 such as an external microprocessor.
Frequency setting data MF is input via the L input terminal. The transmission frequency f0 is output from the PLL output terminal OUT to the tuner 102 to which the antenna 104 is connected. Further, the controller 101 controls the PLL synthesizer circuit 100 and also controls the video control unit (VCU) 103, and outputs a video signal to the CRT 105. FIG.
A, a detailed block diagram of the input interface 7A and the charge pump current control circuit 8 is shown. In the present embodiment, for simplicity of description, a case is shown in which the upper two bits of frequency division ratio setting data DF are selected as control bits.

The input interface 7A inputs the frequency setting data MF supplied from the outside at an arbitrary timing to generate the frequency division ratio setting data DF.
And a data latch unit that latches the frequency division ratio setting data DF from the input unit 71, outputs the latched data to the programmable frequency divider 6, and outputs a control bit to the charge pump current control circuit 8 as control data EF. 72.

FIG. 3 is a time chart showing the data format of the frequency setting data MF. The frequency setting data MF includes serial data SD including n-bit data M1 to Mn representing a frequency value in a binary number,
A clock CLK for bit synchronization and serial data SD
And an enable signal EN for designating an effective part of. Since the serial data SD is represented by binarizing the frequency, for example, when the frequency of the VHF band which is a low frequency band is specified, “0” is increased in the upper bits, and the UHF band which is a high frequency band is specified. Then, the upper bit becomes "1".

The operation of the input interface 7A will be described with reference to FIGS. The input unit 71 receives the serial data SD of the frequency setting data MF, the clock CLK, and the enable signal EN. The serial data transfer control circuit 71A outputs a signal (EN) to the shift register only when the input enable signal EN becomes high level. And the shift register 7
1B is the clock C only when the signal (EN) is input.
The serial data SD is input based on the LK, and the serial data SD is serial-to-parallel converted to generate parallel frequency division ratio setting data DF. However, when the output of the signal (EN) stops, the clock CLK becomes invalid. Also, the enable signal E
When N goes low, the frequency division ratio setting data DF is latched by the data latch unit 72 in response to a latch signal LATCH generated from the serial data transfer control circuit 7A. The latched frequency division ratio setting data DF is output to the programmable frequency divider 6 and, at the same time, its upper two bits (Mn, Mn-1) are output to the charge pump current control circuit 8 as control data EF.

Next, the charge pump current control circuit 8 and the charge pump circuit 3A will be described with reference to FIGS.

The charge pump current control circuit 8 includes current control units 81 and 82 having different current values corresponding to each control bit of the control data EF. Current control units 81, 82
Are respectively connected to the switches S81 and S82 and the current source I8.
1, I82. In the present embodiment,
The current value of each current source is set as I82> I81. The switch S of each current control unit is connected to the first control bit.
Is turned on or off according to the logic level (for example, “1”) or the second logic level (for example, “0”). Table 1 shows combinations of possible states of the switch S based on the control data EF.

[0023]

[Table 1]

That is, the charge pump control current PF is controlled in four stages, and the control bits Mn and Mn-1 are set to "0,
"0" (state 1) is the minimum level (0) and "1,
1 "(state 4) is at the maximum level.

Next, charge pump circuit 3A includes a current source I31 connected to power supply level Vcc and a ground level G.
A current source I32 connected to the ND, and switches S31 and S32 connected between the output node out and the current sources I31 and I32, respectively, are provided. When the positive phase difference signal PDU is supplied, the charge pump circuit 3A performs S31.
Is turned on and the current of the current source I31 is output as the charge pump signal P. Similarly, when the negative phase difference signal PDD is supplied, the current of the current source I32 is used as the charge pump signal P. In the embodiment, the magnitude of the charge pump signal P is controlled by the charge pump control current PF. That is, as shown in FIG.
The charge pump control current PF depends on the values of n and Mn-1.
Increases, the current level of the charge pump signal P also increases.

Here, the detailed circuits of the charge pump current control circuit 8 and the charge pump circuit 3A are configured as shown in FIG. The output current value of the charge pump signal P is controlled by the resistors R2 and R3 of the charge pump current control circuit 8. The resistance of these resistors is R
3> R2, and the charge pump current control circuit 8
The control bits Mn and Mn-1 input to the resistor R
2, R3 are selected to determine the charge pump control current PF. Therefore, the charge pump control current PF by the resistors R2 and R3 is added to the charge pump signal P by the resistor R1 of the charge pump circuit 3. Note that the size of the resistor R1 of the charge pump circuit 3A is appropriately set.

FIG. 6 shows an example of the damping factor corrected for the current value of the charge pump signal P set in the states 1 to 4 of the charge pump current control circuit 8 described above. The damping factor mentioned here particularly means the amplitude of the transient characteristic. The conventional damping factor increases in proportion to the frequency as shown by the broken line,
In the present embodiment, the current value of the charge pump signal P increases as the state advances from state 1 to state 4 as shown by the solid line. This has the effect of accelerating the charging and discharging of the low-pass filter, and thus suppresses an increase in the damping factor.

The embodiment of the present invention has been described above.
The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, not only the upper two bits of the frequency division ratio setting data but also more bits are used as control data, and the number of current control units is increased in accordance with the increase in the number of bits. It can be controlled and adjusted precisely. Therefore, it is possible to set an optimal damping factor for a wider frequency band.

[0029]

As described above, the PLL synthesizer circuit according to the present invention provides the charge pump signal P in response to the supply of the frequency setting data, that is, the charge pump current control data generated from the data for controlling the frequency division ratio. Since the current value is controlled, the fluctuation range of the damping factor is suppressed by changing the charge pump signal in accordance with the change of the frequency division ratio, and the lock time between each channel of the UHF band and the VHF band is reduced. Fluctuations in noise characteristics can also be greatly improved.

[Brief description of the drawings]

FIG. 1A is a block diagram showing a first embodiment of a PLL synthesizer circuit of the present invention. FIG. 1B is a block diagram showing a TV receiver using the PLL synthesizer circuit of the present invention.

2A is a block diagram of an input input interface, a charge pump current control circuit, and a charge pump circuit of the present invention. FIG. 2B is a detailed block diagram of an input input interface of the present invention.

FIG. 3 is a time chart showing a format of frequency setting data and a latch signal.

FIG. 4 is a detailed circuit diagram of the charge pump current control circuit and the charge pump circuit of the present invention.

FIG. 5 shows characteristics of a charge pump signal according to the present invention.

FIG. 6 shows characteristics of a damping factor according to the present invention.

FIG. 7 is a block diagram showing a first conventional example.

FIG. 8 is a block diagram showing a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2 Phase comparison circuit 3A Charge pump circuit 4 Low-pass filter 5 Voltage controlled oscillator 6 Programmable frequency divider 7A Input interface 8 Charge pump current control circuit 71 Input section 71A Serial data transfer control circuit 71B Shift register 72 Data latch section 81 82 Current control unit S31, S32, S81, S82 Switch I31, I32, I81, I82 Current source 100 PLL synthesizer circuit 101 Controller 102 Tuner 103 Video control unit 104 Antenna 105 CRT

Claims (6)

(57) [Claims] 1. A voltage-controlled oscillator that receives frequency setting data for setting an output frequency and generates the output frequency, and at least a charge pump circuit that generates a charge pump current that controls the oscillation frequency of the voltage-controlled oscillator. Wherein the current value of the charge pump current of the charge pump circuit is adjusted based on the frequency setting data.
LL synthesizer circuit. 2. The method according to claim 1, wherein the adjusting of the current value of the charge pump current includes selecting a plurality of bits from the input frequency setting data to generate control data, and adjusting the number of the charge data corresponding to the number of bits of the control data. 2. The PLL synthesizer circuit according to claim 1, wherein the control is performed by a charge pump current control circuit that adjusts a current value of the pump current. 3. An input section to which frequency setting data for setting an output frequency is input, a reference oscillator for generating a reference frequency, a voltage controlled oscillator for generating an oscillation signal for controlling the output frequency, and A frequency divider that receives the signal and the frequency setting data and generates a frequency-divided signal obtained by dividing the oscillation signal to the value of the reference frequency, and compares the phase of the frequency-divided signal with the reference frequency to obtain a phase difference. In a PLL synthesizer circuit including a phase comparison circuit that generates a signal and a charge pump circuit that generates a charge pump current that controls the output frequency of the voltage controlled oscillator based on the phase difference signal, control data is generated from the frequency setting data. And a charge generating a charge pump current control signal for controlling the charge pump current based on the control data. PLL synthesizer circuit further comprising a pump current control circuit. 4. The input unit generates frequency division ratio setting data for setting a frequency division ratio of the frequency divider from the frequency setting data and outputs the frequency division ratio setting data to the frequency divider. 4. The PLL synthesizer circuit according to claim 3, wherein a plurality of bits are selected from the control signal and output to the charge pump current control circuit as the control data. 5. The PLL synthesizer circuit according to claim 3, wherein said charge pump current control signal is generated by a number of current sources corresponding to the number of bits of said control data. 6. The control data, wherein upper two bits of the frequency setting data are selected.
Or a PLL synthesizer circuit according to claim 4.