JPH11308101A - Tuner device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the fluctuation of a phase noise characteristic by the deviation of a received frequency with respect to a PLL(phased locked loop) synthesizer tuner with a wide received frequency band. SOLUTION: The control voltage signal V of a local oscillator 6 constituted of a voltage control oscillator is converted into a digital signal by an analog digital converter 23 and charge pump current control data C0, C0...Cn are generated. Charge pump current P derived from a charge pump circuit 180 is optimized based on the output of the phase comparator 17 of a PLL circuit with control data and optimized charge pump current P is smoothed by a loop filter 19. A tuner is provided with the PLL circuit obtaining the control voltage signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phas).
The present invention relates to a tuner device using a (e Locked Loop) synthesizer circuit, and more particularly to a tuner device for a digital CATV.

[0002]

2. Description of the Related Art The structure of a conventional tuner device is shown in FIGS. FIG. 8 shows an entire configuration of a conventional double conversion tuner. High frequency RF received
(Radio Frequency) signal is converted to an intermediate frequency IF (Interm
output signal of the same frequency.

In FIG. 8, 1 is an RF input terminal, 2 is a band-pass filter that allows only an RF signal in a reception band to pass, and 3 is an AGC (Automatic Gain Co).
ntrol), 4 is an RF amplifier circuit, 5 is a first frequency converter, 6 is a first local oscillator, 7 is a PLL circuit, 8 is a band-pass filter, 9 is a first IF amplifier circuit, 10 is A band pass filter, 11 is a second frequency converter, 12 is a second local oscillator, 13 is a band pass filter, 14 is a second IF amplifier circuit, and 15 is an IF signal output terminal of this tuner.

An RF signal input from an RF input terminal 1 is subjected to a filtering process corresponding to a reception frequency band by a band pass filter 2, and the AGC amplifier circuit 3
After being limited to a predetermined level range by an AGC voltage corresponding to the RF signal level, the signal is amplified by the RF amplifier circuit 4 and supplied to the first frequency converter 5. The first frequency converter 5 converts the frequency of the input RF signal into a first IF signal based on the first local oscillation signal output from the first local oscillator 6. In this case, the oscillation frequency of the first local oscillator 6 is controlled by the PLL circuit 7 in accordance with the reception channel, and the frequency is stabilized.

Here, the first IF signal output from the first frequency converter 5 is subjected to band filtering corresponding to a first intermediate frequency band by a band-pass filter 8, and the first IF signal is output. After being amplified by the amplifier circuit 9, the bandpass filter 10 again performs band filtering processing corresponding to the first intermediate frequency band, and is supplied to the second frequency converter 11. Second frequency converter 11
Converts the frequency of the input first IF signal into a second IF signal based on the second local oscillation signal output from the second local oscillator 12.

[0006] The second IF signal output from the second frequency converter 11 is applied to a band-pass filter 13.
As a result, a band filtering process corresponding to the second intermediate frequency band is performed, amplified by the second IF amplifier circuit 14, and then output from the IF signal output terminal 15.

FIG. 9 is a detailed diagram of the PLL circuit 7 in FIG. In FIG. 9, the same parts as those in FIG. 8 are denoted by the same reference numerals. Reference numeral 5 denotes a first frequency converter, 6 denotes a first local oscillator, and 7 denotes a PLL circuit. This PLL circuit 7
, 16 is a crystal oscillator, 17 is a phase comparator, 18
Is a charge pump circuit, 19 is a loop filter including resistors R1 and R2, a capacitor C and an amplifier 21, and 20 is a programmable frequency divider.

The phase comparator 17 calculates the reference frequency fr from the crystal oscillator 16 and the oscillation frequency fv of the first local oscillator 6.
The phase is compared with a frequency fvco / N obtained by dividing the frequency of N by N (described later), and a phase comparison signal Q corresponding to the phase advance / delay is obtained.
1 and Q2 are output to the charge pump circuit 18. The charge pump circuit 18 generates a positive or negative DC current signal P based on the phase comparison signals Q1 and Q2,
The voltage is supplied to a loop filter 19 including resistors R1 and R2 and a capacitor C.

The loop filter 19 filters (integrates) the charge pump signal P, outputs a smoothed control voltage signal V, and supplies it to the first local oscillator 6. The first local oscillator 6 oscillates at an oscillation frequency fvco based on the control voltage signal V, outputs an output signal to the first frequency converter 5, and
Output to 0. The programmable frequency divider 20 divides the output signal from the first local oscillator 6 by N, and outputs the frequency fvco
/ N is supplied to the phase comparator 17.

Such a circuit constitutes a PLL which is N times in phase synchronization with the output frequency fr of the reference oscillator comprising the crystal oscillator 16, and the frequency division ratio output from the programmable frequency divider 20 is determined by the user. The value is changed according to the selected channel. Thus, the output frequency fvco of the first local oscillator 6 is sent to the first frequency converter 5 and converts the received RF signal into an IF frequency.

Here, the time constant and gain of the PLL loop filter (low-pass filter) determined by the resistors R1 and R2 and the capacitor C shown in FIG. 9 are fixed values for the selected channel. In the PLL circuit 7 shown in FIG. 9, the output frequency fvco of the first local oscillator 6 is represented by fvco = N · fr (1), and the tuning is performed by a programmable frequency divider constituted by a microcomputer or the like. This is done by changing the frequency division ratio N of 20.

In such a conventional tuner device, P
The phase transfer function H (s) that determines the phase noise characteristic of the LL synthesizer is given by the following equation.

[0013]

(Equation 1)

In the above equation, the filter time constants τ ₁ and τ ₂ are
τ ₁ = R1 · C, τ ₂ = R2 · C, and the natural frequency ω _n and the damping factor ζ are respectively ω _n = (K /
tau ₁₎ ^1/2, is given by _{ζ = τ 2/2 · (} K / τ 1) 1/2,
The loop gain K is K = Kφ · Kvco / N.
Here, Kφ is the sensitivity of the phase comparator 17, and Kvco is the first
, And S is a Laplace operator.

Here, in the channel selection, the above equation (1)
When the frequency division ratio N changes, the loop gain K changes as is apparent from the above relationship, and the natural frequency ω _n
And the damping factor 変 化 changes, and the phase transfer function H
The frequency response characteristic of (S) changes. Since the phase noise characteristic of the PLL synthesizer is approximately proportional to the frequency response characteristic of the phase transfer function H (S), if the receiving channel changes and the dividing ratio N changes, the phase noise characteristic changes. . As described above, the natural frequency ω _n affects the phase noise characteristic of the PLL circuit after lock-up, and the damping factor ζ affects the lock-up time of the PLL circuit.

To solve such a problem, Japanese Patent Laid-Open No.
In the PLL synthesizer circuit of No. 93125, the output current value of the charge pump circuit is variably controlled based on the division ratio setting data at the time of channel selection, so that the PLL synthesizer circuit having a wide frequency range has a high frequency band and a low frequency band. A technique for controlling a lock-up time between each frequency and a variation in noise characteristics is disclosed.

[0017]

When the above-mentioned conventional double-conversion tuner is used as a tuner for receiving a terrestrial digital television broadcast having a wide receiving band, there are the following problems. In a terrestrial digital television broadcast receiving tuner, the receiving band is 50 MHz.
Since the band is very wide, z to 806 MHz (used in the United States), the inter-channel deviation of the phase noise characteristic is large depending on the reception frequency, and the phase noise characteristic fluctuates greatly, greatly affecting the performance of the tuner.

In the PLL synthesizer circuit disclosed in JP-A-9-93125, the charge pump current of the charge pump circuit is controlled by the PLL frequency division ratio data which is a digital signal. In such a case, there is a problem that a boundary value between the zones cannot be analogously selected to an arbitrary optimum value. The present invention has been made in view of the above problems, and has as its object to provide a tuner that has a simple configuration and suppresses deviation in phase noise characteristics due to a channel selected when receiving a wideband frequency.

[0019]

In order to achieve the above object, according to the present invention, there is provided a tuner apparatus comprising: a local oscillator comprising a voltage-controlled oscillator for changing an output frequency in accordance with an input voltage; A frequency divider that can vary the frequency division ratio in response to an external command and derives a frequency-divided signal obtained by dividing the output of the local oscillator according to the frequency division ratio; and generates a reference frequency signal. A reference frequency oscillator; a phase comparator for comparing a phase between the reference frequency signal and the frequency-divided signal; and a charge pump current for controlling an oscillation frequency of the local oscillator based on an output of the phase comparator. A charge pump circuit; a loop filter for smoothing the charge pump current to derive a control voltage for controlling an oscillation frequency of the local oscillator; And a charge pump current control means for setting the current value of the charge pump current derived from the charge pump circuit to a predetermined optimum value that reduces the change in the time constant of the loop filter. And

According to a second aspect of the present invention, in the tuner device according to the first aspect, a control voltage of an analog signal for controlling an oscillation frequency of the local oscillator is converted into a digital control signal for controlling a charge pump current of the charge pump circuit. It is characterized by comprising analog-to-digital conversion means for converting.

According to a third aspect of the present invention, in the tuner device according to the second aspect, the analog-to-digital converter is constituted by a plurality of arbitrary comparator circuits.

[0022]

The programmable frequency divider sets the oscillation frequency fvco from the first local oscillator to 1 / N according to the selected channel.
The phase of the divided frequency fvco / N is compared with a reference frequency fr from a crystal oscillator by a phase comparator, and phase comparison signals Q1 and Q2 corresponding to the phase advance / delay are output to the charge pump circuit. . The charge pump circuit generates a positive or negative DC current signal P based on the above-mentioned phase comparison signals Q1 and Q2, smoothes it with a loop fill, and makes the first local oscillator control voltage signal V corresponding to the selected channel. Supply.

On the other hand, the control voltage signal V output from the loop filter is an A / D converter, and charge pump current control data Cn, Cn-1,... C of the charge pump circuit.
Converted to o. This charge pump current control data C
n, Cn-1,... Co are digital signals corresponding to the frequency of the selected channel, and are positive or negative DC current signals P from the charge pump circuit for suppressing the time constant of the loop filter from shifting with frequency. Is set in advance so that can be derived.

The charge pump current control data Cn, Cn-1,... Co derived from the A / D converter are supplied to the charge pump circuit via the charge pump current control circuit. P is made and supplied to the loop filter. Therefore, the loop filter suppresses the deviation of the time constant even when the tuning frequency greatly changes, and prevents the phase noise characteristic of the PLL synthesizer circuit from deteriorating. The output frequency fvco of the first local oscillation circuit derived as described above is mixed with the input RF signal by the first frequency converter and converted into an IF signal.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. Since the entire configuration of the tuner device of the present invention is exactly the same as that of FIG. 8 described in the related art except for the PLL circuit, the description is omitted. FIG. 1 is a block diagram showing a configuration of a PLL circuit 70 used in the present invention corresponding to the conventional PLL circuit 7 shown in FIGS.

In FIG. 1, portions corresponding to those of the prior art shown in FIG. 9 are denoted by the same reference numerals, 5 indicates a first frequency converter, 6 indicates a first local oscillator, and 70 indicates a PL used in the present invention.
This is an L circuit. In this PLL circuit 70, 16 is a crystal oscillator, 17 is a phase comparator, 180 is a charge pump circuit, 19 is a loop filter, 20 is a programmable frequency divider, 22 is a charge pump current control circuit, and 23 is an analog-to-digital converter. is there. The difference from the prior art shown in FIG. 9 is that a charge pump current control circuit 22 and an analog-to-digital converter 23 are added.

The phase comparator 17 calculates the reference frequency fr from the crystal oscillator 16 and the oscillation frequency fv of the first local oscillator 6.
The phase is compared with a frequency fvco / N obtained by dividing the frequency of N by N (described later), and a phase comparison signal Q corresponding to the phase advance / delay is obtained.
1 and Q2 are output to the charge pump circuit 180. The charge pump circuit 180 generates a positive or negative DC current signal P based on the phase comparison signals Q1 and Q2, and supplies it to the loop filter 19.

The loop filter 19 filters (integrates) the charge pump signal P and outputs a control voltage signal V. The first local oscillator 6 oscillates at an oscillation frequency fvco based on the control voltage signal V, and outputs an output signal to the first frequency converter 5 and to the programmable frequency divider 20. Programmable frequency divider 2
0 divides the output signal from the first local oscillator 6 by N,
The frequency fvco / N is supplied to the phase comparator 17.

The relationship between the reference frequency fr from the crystal oscillator 16 and the oscillation frequency fvco of the first local oscillator 6 is given by fvco = N · fr (1). This is performed by changing the circumferential ratio N.

The control voltage signal V is supplied to an analog-to-digital converter 23 separately from the first local oscillator 6. The analog-to-digital converter 23 outputs the control voltage signal V
(Analog signal) is converted into charge pump current control data Cn, Cn-1,... Co (parallel data of digital signal) of the charge pump circuit 180. The charge pump current control circuit 22 controls the charge pump current of the charge pump circuit 180 based on the charge pump current control data Cn, Cn-1,... Co. Here, the charge pump current control data (Cn, Cn-1,... Co)
Can be set arbitrarily.

FIG. 2 is a detailed diagram of the charge pump circuit 180, the loop filter 19, and the charge pump current control circuit 22 in FIG. In FIG. 2, the same parts as those of FIG.
180 is a charge pump circuit, 19 is a loop filter,
22, a charge pump current control circuit; and 23, an analog-to-digital converter.

The charge pump circuit 180 comprises PNP bipolar transistors Q20, Q24, Q26, NPN bipolar transistors Q23, Q25, a PMOS transistor Q21, and an NMOS transistor Q22. Bipolar transistors Q20, Q24, Q26
Are connected in common to a power supply (+ B), the bipolar transistors Q20 and Q24 are current mirror-connected to the bipolar transistor Q26, and the collector of the bipolar transistor Q20 is connected to the source of the PMOS transistor Q21. Therefore, the supply current Ia, which is the collector current of the bipolar transistor Q20, has a current amount proportional to the control current Ic flowing through the collector of the bipolar transistor Q26.

The bipolar transistors Q23 and Q25 have their emitters grounded and are connected in current mirror. And the bipolar transistor Q2
5 is a bipolar transistor Q
24, connected to the collector of a bipolar transistor Q
23 is connected to the source of the NMOS transistor Q22. Therefore, the bipolar transistor Q23
Is also proportional to the control current Ic flowing through the collector of the bipolar transistor Q26.

The charge pump current control circuit 22 is composed of constant current sources RIn. One of the constant current sources RIn... RIo is commonly connected to the collector of the bipolar transistor Q26 of the charge pump circuit 180, and the other is commonly grounded. The amount of supply current of the constant current sources RIn ... Rio is Icn ...
Ico. The constant current sources RIn ... RIo are on / off controlled by charge pump current control data Cn ... Co output from the analog-to-digital converter 23. That is, the control current Ic output from the charge pump current control circuit 22 is a constant current source RIn.
Since the current amount is proportional to the sum of the currents Icn ... Ico of Io, the control current Ic can be controlled by the charge pump current control data Cn ... Co.

In the above description, the number of data bits of the charge pump current control data Cn... Co can be set arbitrarily. Accordingly, the number of constant current sources RIn... RIo with a switching function of the charge pump current control circuit 15 can be set arbitrarily.

In such a configuration, the charge pump circuit 180 controls the phase comparison signal Q from the phase comparator 17.
1 and Q2 are PMOS transistors Q21 and NM, respectively.
The signal is input to the gate of the OS transistor Q22. When the phase comparison signal Q1 is "L", the PMOS transistor Q21
Is turned on, the supply current Ia is sourced, and the phase comparison signal Q
2 is "H", the NMOS transistor Q22 turns on,
The supply current Ib is sinked.

Then, a charge pump signal (current) P is obtained from between the drain of the PMOS transistor Q21 and the drain of the NMOS transistor Q22, and the charge pump signal P is supplied to the loop filter 19. The loop filter 19 includes an amplifier 21 and a resistor R1,
R2 and a capacitor C. By changing the charge pump signal P (source current Ia, sink current Ib) supplied to the loop filter 19, the time constant of the loop filter 19 is changed.

FIG. 3 is a detailed diagram of the analog-to-digital converter 23 in FIG. Analog-to-digital converter 23
Are n + 1 comparators Ao to An and a resistance RAo,
RBo, RCo, RDo to RAn, RBn, RCn, R
Dn. Reference voltage Vr of comparator An
n is set by the resistors RAn and RBn. When the charge pump current control voltage signal V is higher than the reference voltage Vrn of the comparator An, the output of the comparator An is at “H” level, and when the current control voltage signal V is lower than the reference voltage Vrn of the comparator An. The output of the comparator An is at the “L” level.

When the current control voltage signal V slightly fluctuates near the reference voltage Vrn of the comparator An,
Since the output of the comparator An repeats the “H” level and the “L” level, the resistor RC is used to prevent this.
n and RDn give the comparator An a hysteresis characteristic. Note that the input impedance of the comparator An is so high that it does not affect the PLL loop.

Next, in the above description, the first local oscillator 6
Control voltage signal (= charge pump current control voltage signal)
V, Z01, Z12, Z23, Z
The case of dividing into 34 zones will be described in more detail. Here, the zone is divided into four zones. However, the present invention is not limited to this, and an arbitrary division is possible.

FIG. 4 shows the relationship between the control voltage signal (= charge pump current control voltage signal) V of the first local oscillator 6.
3 shows the relationship between the oscillation frequency fvco of the first local oscillator 6. The control voltage signal (= charge pump current control voltage signal) V of the first local oscillator 6 is set to Z
01, Z12, Z23, Z34
The boundary value of each zone is V0, V
Assuming that 1, V2, V3, and V4, the oscillation frequency fvco of the first local oscillator 6 increases in proportion to the control voltage signal (= charge pump current control voltage signal) V. When the control voltage signal (= charge pump current control voltage signal) V increases to V0, V1, V2, V3, and V4 in ascending order, the oscillation frequency fvco becomes f0 and f in descending order.
1, f2, f3, and f4.

FIG. 5 shows that the control voltage signal (= charge pump current control voltage signal) V is V0, V1,
V2, V3, V4 and increase (oscillation frequency fvco increases f0, f1, f2, f3, f4 in descending order), ie, when the reception channel frequency changes from low to high, the natural frequency V for changes in ωn54
CO control voltage input level 50, A / D converter output 51,
Charge pump current 52, loop filter time constant (τ1
= R1 · C) 53.

Next, the VCO control voltage input level 50 and A
The relationship between the / D converter output 51 will be described. In the analog-to-digital converter shown in FIG. 3, n = 2. The control voltage signal (charge pump current control voltage signal) V and the reference voltage Vrn of the comparator An are calculated as follows: V1 = Vr0, V2 = V
r1, V3 = Vr2.

1) When the control voltage signal (charge pump current control voltage signal) V is in the zone Z01 The control voltage signal (= charge pump current control voltage signal) V is V1 = V
Since it is lower than r0, C2 = L, C1 = L, and C0 = H.

2) When the control voltage signal (= charge pump current control voltage signal) V is in the zone Z12 The control voltage signal (= charge pump current control voltage signal) V is V1 =
Since it is higher than Vr0 and lower than V2 = Vr1, C2 =
L, C1 = L, C0 = H.

3) When the control voltage signal (= charge pump current control voltage signal) V is in the zone Z23, the control voltage signal (= charge pump current control voltage signal) V is V2 =
Since it is higher than Vr1 and lower than V3 = Vr2, C2 =
L, C1 = H, and C0 = H.

4) When the control voltage signal (= charge pump current control voltage signal) V is in the zone Z34, the control voltage signal (= charge pump current control voltage signal) V is V3
= Vr2, C2 = H, C1 = H, C0 = H
Becomes

Next, the relationship between the A / D converter output 51 and the charge pump current 52 will be described. As described in FIG. 2 for the charge pump circuit 180 and the charge pump current control circuit 22, if n = 2 in the charge pump current control circuit 22, 1) the control voltage signal (= charge pump current control voltage signal) V When in Z01, C2 = L, C1 = L,
C0 = L, and the charge pump control current becomes zero. 2) When the control voltage signal (= charge pump current control voltage signal) V is in the zone Z12, C2 = L, C1 = L,
C0 = H, and the charge pump control current becomes Ic0. 3) When the control voltage signal (= charge pump current control voltage signal) V is in zone Z23, C2 = L, C1 = H,
C0 = H, and the charge pump control current is Ic0 + I
c1. 4) When the control voltage signal (= charge pump current control voltage signal) V is in the zone Z34, C2 = H, C1 =
H, C0 = H, and the charge pump control current is Ic0
+ Ic1 + Ic2.

FIG. 6 is a graph showing the above description. When the oscillation frequency fvco of the first local oscillator 6 increases, the charge pump control current Ic increases in proportion. Since the charge pump current P is proportional to the charge pump control current Ic, the charge pump current P increases in proportion to the oscillation frequency of the first local oscillator 6.

Next, the relationship between the charge pump current 52 and the loop filter time constant 53 will be described. In the charge pump circuit 180 and the loop filter 19 of FIG. 2, the time constant of the loop filter 13 is changed by changing the charge pump signal P (source current Ia, sink current Ib) supplied to the loop filter 19. That is, when the charge pump signal P (source current Ia, sink current Ib) increases, the time constant τ1 of the loop filter 19 = R1 ·
C becomes smaller. That is, as the oscillation frequency fvco of the first local oscillator 6 increases, the loop filter 19
Τ1 = R1 · C becomes smaller.

Next, the relationship between the loop filter time constant 53 and the natural frequency ωn54 will be described. As described in detail in the section of the prior art, the relationship between the natural frequency ωn and the reep filter time constant τ1 = R1 · C is expressed as follows: ωn = (K / τ1) ^1/2 (2) Becomes

From equation (2), as the oscillation frequency fvco of the first local oscillator 6 increases, the time constant τ1 = R1 · C of the loop filter 19 decreases, and the natural frequency ωn increases.

As described above, according to the present invention, the reception frequency becomes higher (the oscillation frequency f of the first local oscillator 6).
As vco increases, the natural frequency ωn is controlled to increase.

FIG. 7 shows the reception frequency (the first local oscillator 6).
The relationship between the oscillation frequency fvco) and the natural frequency ωn is compared between the conventional example and the present invention. Dotted line (a)
The present invention is shown by a solid line (b). The natural frequency ωn becomes ωn = (K / τ1) ^{1/2 as} shown in the above equation (2), and the respective values are as follows: ωn: natural frequency, K: loop gain, τ1: filter time Constant K = Kφ · Kvco / N (3) Expression: K: loop gain, Kφ: sensitivity of phase comparator, Kvc
o: VCO sensitivity, N: frequency division ratio (N = fvco / fr)

Further, τ1 changes by changing the charge pump current. Here, considering the relationship between ωn and fvco, Kφ, Kvco, and fr do not depend on fvco, so that if τ1 is a constant value, the relationship is as shown in FIG.
Here, τ1 is changed according to the value of fvco. For example, τ1 is switched to four values depending on the value of fvco as in the following example. f0 to f1: τ1 1 f1 to f2: τ1 2 f2 to f3: τ1 3 f3-f4: τ1 4 Here, f0 <f1 <f2 <f3 τ1 1> τ1 2> τ1 3> τ1 4, the relationship between ωn and fvco is as shown in FIG.
FIG. 11 corresponds to FIG.

Conventionally, when the reception frequency increases, the frequency division ratio N increases, and the loop gain K decreases according to the equation (3). When the loop gain K decreases, the natural frequency ωn decreases according to the equation (2). That is, the relationship changes as indicated by the dotted line in the relationship between the reception frequency (the oscillation frequency fvco of the first local oscillator 6) and the natural frequency ωn in FIG.

In the present invention, the natural frequency ωn is controlled by controlling the charge pump current as described with reference to FIG.
Is controlled in the direction opposite to the conventional one, the correction is made as shown by the solid line in the relationship between the reception frequency (the oscillation frequency fvco of the first local oscillator 6) and the natural frequency ωn in FIG.

As shown in FIG. 7, according to the present invention, the channel-to-channel deviation of the natural frequency ωn is improved so as to be smaller than that of the prior art. It is the phase transfer function H (s) that determines the phase noise characteristic of the PLL circuit as described above. The phase transfer function H (s) is a function of the natural frequency ωn, and when the natural frequency ωn changes, the phase transfer function H (s) also changes. Thus, according to the present invention,
By reducing the channel-to-channel deviation of the natural frequency ωn as compared with the related art, the channel-to-channel deviation of the phase transfer function H (s) becomes smaller, so that the channel-to-channel deviation of the phase noise characteristic of the PLL circuit can be reduced. .

Further, Japanese Patent Application Laid-Open No. 9-9312 described in the prior art
It has the following advantages over No.5. Here, it is assumed that the frequency division ratio N takes a value from 1000 to 2000, for example.
Since N is given in binary to operate the divider,
Assuming a 14-bit divider, Becomes

In Japanese Patent Application Laid-Open No. 9-93125, switching is performed by looking at the data of the upper bit.
It is assumed that the data is switched to two bands by the data of the bit.
Then, the threshold value becomes 100000000000000000, which is 1024 in decimal. Therefore, 11bi
Judging from the viewpoint, switching can be performed only at fixed points of 1000 to 1023 and 1024 to 2000. This point is not always the optimum switching frequency, and sufficient characteristics (eg, phase noise characteristics) cannot be obtained. On the other hand, in the above embodiment of the present invention, the band switching threshold is set to the analog data (VCO control voltage)
Therefore, the threshold for band switching can be set freely.
Therefore, it is possible to preferably suppress the deviation of the phase noise characteristic with respect to the frequency shift.

[0061]

As described above in detail, according to the present invention, the receiving band is 50 MHz to 806 MHz (U.S. specification), such as a tuner for receiving terrestrial digital television broadcasting.
Therefore, even in a case where the phase noise characteristic greatly affects the performance of the tuner in a very wide band, it is possible to provide a tuner for receiving a terrestrial digital television broadcast having a small deviation between reception channels in the phase noise characteristic.

The analog-to-digital conversion circuit for extracting charge pump current control data, which is a digital signal, from the control voltage of the VCO, which is an analog voltage, is composed of an arbitrary plurality of comparator circuits. Signal), the boundary value between zones when controlling by dividing into a plurality of zones can be selected analogously to any optimum value, and the displacement of the frequency to be selected can be selected. In contrast, the deviation of the phase noise characteristic can be effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a main part of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a main part of the present invention.

FIG. 3 is a circuit diagram of a main part of the present invention.

FIG. 4 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 8 is a block diagram showing an outline of a double conversion tuner.

FIG. 9 is a block diagram of a main part of a conventional technique.

FIG. 10 is a diagram for explaining FIG. 7;

FIG. 11 is a diagram for explaining FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 RF input terminal 2 band-pass filter 3 AGC (Automatic Gain Control) amplifier circuit 4 RF amplifier circuit 5 first frequency converter 6 first local oscillator 7 PLL circuit 8 band-pass filter 9 first IF amplifier circuit 10 1 band pass filter 11 second frequency converter 12 second local oscillator 13 band pass filter 14 second IF amplifier circuit 15 IF signal output terminal 16 crystal oscillator 17 phase comparator 18 charge pump circuit 19 loop filter 20 programmable Frequency divider 21 Amplifier 22 Charge pump current control circuit 23 Analog-to-digital converter 70 PLL circuit 180 Charge pump circuit

Claims (3)

[Claims] 1. A local oscillator comprising a voltage-controlled oscillator for changing an output frequency in accordance with an input voltage, and a frequency division ratio which can be varied in response to an external command. A frequency divider that derives a frequency-divided signal obtained by dividing the output of the local oscillator, a reference frequency oscillator that generates a reference frequency signal, and a phase comparison that compares a phase between the reference frequency signal and the frequency-divided signal. A charge pump circuit for generating a charge pump current for controlling the oscillation frequency of the local oscillator based on the output of the phase comparator; and smoothing the charge pump current to reduce the oscillation frequency of the local oscillator. A loop filter for deriving a control voltage for controlling; a current value of a charge pump current derived from the charge pump circuit based on the control voltage; A tuner device comprising: a PLL synthesizer circuit comprising: a charge pump current control means for setting a predetermined optimum value for reducing a change in the time constant of the filter. 2. An analog-to-digital converter for converting a control voltage of an analog signal for controlling an oscillation frequency of the local oscillator to a digital control signal for controlling a charge pump current of the charge pump circuit. The tuner device according to claim 1. 3. The tuner device according to claim 2, wherein said analog-to-digital conversion means comprises a plurality of arbitrary comparator circuits.