JP2001237700A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuitInfo
- Publication number
- JP2001237700A JP2001237700A JP2000048790A JP2000048790A JP2001237700A JP 2001237700 A JP2001237700 A JP 2001237700A JP 2000048790 A JP2000048790 A JP 2000048790A JP 2000048790 A JP2000048790 A JP 2000048790A JP 2001237700 A JP2001237700 A JP 2001237700A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency division
- frequency divider
- output
- divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は位相同期ループ回路
に関し、特に、分数分周を利用して基準周波数よりも細
かい周波数分解能を有する出力周波数を得ることができ
るＰＬＬ周波数シンセサイザを構成するのに好適な位相
同期ループ回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit and, more particularly, to a PLL frequency synthesizer capable of obtaining an output frequency having a finer frequency resolution than a reference frequency by using fractional frequency division. The present invention relates to a simple phase locked loop circuit.
【従来の技術】分数分周は可変分周ＮとＮ＋１を用い
て、Ｎ分周を(Ａ−Ｌ)回、Ｎ＋１分周をＬ回使用するこ
とにより、 平均分周数数＝｛Ｎ×(Ａ−Ｌ)＋(Ｎ＋１)×Ｌ｝÷
｛（Ａ−Ｌ）＋Ｌ｝｝＝Ｎ＋Ｌ／Ａ を得ている。従来技術のＰＬＬシンセサイザブロック、
分数分周制御ブロックを図２と図３に示す。2. Description of the Related Art Fractional frequency division is performed by using variable frequency division N and N + 1, and using N frequency division (AL) times and N + 1 frequency division L times, the average frequency division number = ｛N × (AL) + (N + 1) × L｝ ÷
{(AL) + L} = N + L / A. Prior art PLL synthesizer block,
The fractional frequency division control block is shown in FIGS.
【０００２】図２は、電圧制御発振器２７の出力が可変
分周器２１で分周され、その出力は位相比較器２４にて
基準信号２５と位相比較され、その出力がＬＰＦ２６を
通して電圧制御発振器２７の周波数制御入力３４に接続
されるＰＬＬ（位相同期ループ）回路を構成している。FIG. 2 shows that the output of a voltage controlled oscillator 27 is frequency-divided by a variable frequency divider 21, the output of which is compared in phase with a reference signal 25 by a phase comparator 24, and the output of which is passed through an LPF 26 to the voltage controlled oscillator 27. (Phase Locked Loop) circuit connected to the frequency control input 34 of FIG.
【０００３】図３は可変分周器２１とその出力信号F1を
カウントするカウンタ３６とその値によって可変分周器
２１の分周比を切り換える切換制御器３５を示してい
る。平均分周数Ｎ＋Ｌ／Ａを得る場合、入力信号を可変
分周器２１の可変分周Ｎにて分周し、信号ライン２９に
出力したF1を、カウンタ３６で(Ａ−Ｌ)までカウント
し、その後可変分周器２１を(Ｎ＋１)分周に切り換え
て、その出力F1をＡまでカウントする。そして、Ａまで
カウントしたら再び可変分周器２１をＮ分周に切り換え
る。つまり、図４の様にＮ分周を(Ａ−Ｌ)回、(Ｎ＋１)
分周をＬ回連続して使用するため、この繰り返しを周期
Ｔとした基本周波数及びその高調波成分が信号ライン２
９に発生する。この成分の内、位相比較器２４、及びＬ
ＰＦ２６（ＰＬＬループフィルタ）を通過する成分が電
圧制御発振器２１に変調を与え、出力周波数F0の近傍に
不要周波数成分を発生させる（図５）。この繰り返し周
期Ｔの周波数が低い場合、その不要周波数成分の影響を
軽減するためには、ＬＰＦのカットオフ周波数を低く設
定する必要がある。そうすると、ＰＬＬのループ応答が
遅くなり、周波数の安定するまでのロックアップ時間が
長くなってしまうという欠点がある。FIG. 3 shows a variable frequency divider 21, a counter 36 for counting the output signal F1, and a switching controller 35 for switching the frequency division ratio of the variable frequency divider 21 according to the value. To obtain the average frequency division number N + L / A, the input signal is frequency-divided by the variable frequency divider N of the variable frequency divider 21 and the F1 output to the signal line 29 is counted by the counter 36 to (AL). Then, the variable frequency divider 21 is switched to (N + 1) frequency division, and its output F1 is counted up to A. Then, after counting up to A, the variable frequency divider 21 is switched to N frequency division again. That is, as shown in FIG. 4, the frequency division by N is performed (AL) times, (N + 1)
Since the frequency division is used L times continuously, the fundamental frequency and its harmonic components having the repetition as a period T are output from the signal line 2.
Occurs at 9. Among these components, the phase comparator 24 and L
The component passing through the PF 26 (PLL loop filter) modulates the voltage controlled oscillator 21 to generate an unnecessary frequency component near the output frequency F0 (FIG. 5). When the frequency of the repetition period T is low, the cutoff frequency of the LPF needs to be set low in order to reduce the influence of the unnecessary frequency component. Then, there is a disadvantage that the loop response of the PLL becomes slow and the lock-up time until the frequency becomes stable becomes long.
【０００４】[0004]
【発明が解決しようとする課題】本発明は、繰り返し周
期Ｔの基本周波数成分およびその低次高調波成分の影響
を軽減した分数分周制御方法を、安価で簡単な構造で実
現することを目的とし、特に、ＰＬＬ周波数シンセサイ
ザを構成するのに好適な位相同期ループ回路を安価で簡
単な構造で実現することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to realize a fractional frequency dividing control method in which the influence of the fundamental frequency component of the repetition period T and its lower harmonic components is reduced with a simple and inexpensive structure. In particular, it is an object of the present invention to realize a phase locked loop circuit suitable for configuring a PLL frequency synthesizer with an inexpensive and simple structure.
【０００５】[0005]
【課題を解決するための手段】入力信号を外部からの制
御信号をもとに動作する分周器制御回路からの制御信号
によって分周比をＮ−１、Ｎ、Ｎ＋１、・・・の様に可
変できる可変分周器と、その可変分周器の分周比を切り
換えることにより平均分周数（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、
Ａは整数）を得ることができる分数分周にて、分周器出
力信号が出る毎に分周比を切り換えて、同じ分周比が２
または３回よりも多く連続しない様に制御する。そし
て、本発明は位相同期ループ回路の構成と次のとおりと
することにより、前記目的を達成できる。 ・電圧制御発振器の出力を固定分周器で分周し、その出
力を、外部からの制御信号をもとに動作する分周器制御
回路からの制御信号によって分周比をＮ−１、Ｎ、Ｎ＋
１、・・・の様に可変できる可変分周器と、その出力と
基準周波数とを位相比較する位相比較器と、その出力を
入力し高周波成分を除去するＬＰＦと、その出力により
発振周波数を変化させることができる前記電圧制御発振
器を備え、可変分周器の分周比を切り換えることにより
平均分周数（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、Ａは整数）を得る
ことができる分数分周にて、可変分周器出力信号が出る
毎に分周比を切り換えて、同じ分周比が２または３回よ
りも多く連続しない様に制御することができる分周器制
御回路を持つ（請求項１）。 ・基準周波数の出力を、外部からの制御信号をもとに動
作する分周器制御回路からの制御信号によって分周比を
Ｎ−１、Ｎ、Ｎ＋１、・・・の様に可変できる可変分周
器と、その出力と電圧制御発振器の出力を固定分周器で
分周した出力とを位相比較する位相比較器と、その出力
を入力し高周波成分を除去するＬＰＦと、その出力によ
り発振周波数を変化させることができる前記電圧制御発
振器を備え、可変分周器の分周比を切り換えることによ
り平均分周数（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、Ａは整数）を得
ることができる分数分周にて、可変分周器出力信号が出
る毎に分周比を切り換えて、同じ分周比が２または３回
よりも多く連続しない様に制御することができる分周器
制御回路を持つ（請求項２）。 ・電圧制御発振器の出力を、外部からの制御信号をもと
に動作する分周器制御回路からの制御信号によって分周
比をＮ−１、Ｎ、Ｎ＋１、・・・の様に可変できる可変
分周器と、その出力と基準周波数とを位相比較する位相
比較器と、その出力を入力し高周波成分を除去するＬＰ
Ｆと、その出力により発振周波数を変化させることがで
きる前記電圧制御発振器を備え、可変分周器の分周比を
切り換えることにより平均分周数（Ｎ＋Ｌ／Ａ）（Ｎ、
Ｌ、Ａは整数）を得ることができる分数分周にて、可変
分周器出力信号が出る毎に分周比を切り換えて、同じ分
周比が２または３回よりも多く連続しない様に制御する
ことができる分周器制御回路を持つ（請求項３）。 ・前記分周器制御回路は、可変分周器と、その可変分周
器の出力により動作する演算器と、その演算結果により
可変分周器を制御する切換制御器と、を少なくとも備
え、当該分周器制御回路は、 ０≦Ｌ＜Ａ／３の範囲では、 Ｎ−１分周とＮ＋１分周、 １／３≦Ｌ＜２Ａ／３の範囲では、Ｎ分周とＮ＋１分周、 ２Ａ／３≦Ｌ＜Ａの範囲では、 Ｎ分周とＮ＋２分周 となる可変分周器内の２組の分周比を用いて、外部から
の制御信号により前記演算器にオーバーフロー判定値Ａ
（但し、Ａは分数分周分母）、インクリメント値Ｉncを ０≦Ｌ＜Ａ／３ の範囲では Ｉnc＝（Ｌ＋Ａ）／２， Ａ／３≦Ｌ＜２Ａ／３の範囲では Ｉnc＝Ｌ， ２Ａ／３≦Ｌ＜Ａ の範囲では Ｉnc＝Ｌ／２ と設定し、Ｌoを演算結果の値（初期値は不問）とし、
前記可変分周器出力信号がでる毎に、演算器はＩnc＋Ｌ
o→Ｌoの演算を行い、その結果を判定し、Ｌo＜Ａの時
には、分周器を低分周比側に切り換え、また、Ｌo≧Ａ
の時には、Ｌo−Ａ→Ｌoとし、分周器を高分周比側に切
り換える様に制御する（請求項４）。 ・前記分周器制御回路は、可変分周器と、その可変分周
器の出力により動作する演算器と、その演算結果により
可変分周器を制御する切換制御器と、を少なくとも備
え、当該分周器制御回路は、０≦Ｌ＜Ａ／４の範囲で
は、Ｎ−１／２分周（Ｎ−１分周１回動作に引き続きＮ
分周を１回動作をさせる分数分周）とＮ＋１／２分周
（Ｎ＋１分周１回動作に引き続きＮ分周を１回動作をさ
せる分数分周）とＮ＋１分周、Ａ／４≦Ｌ＜３Ａ／４の
範囲では、ＮとＮ＋１分周、３Ａ／４≦Ｌ＜Ａの範囲で
はＮ＋１／２分周とＮ＋３／２分周となる可変分周器内
の２組の分周比を用いて、外部からの制御信号により前
記演算器にオーバーフロー判定値Ａ（分数分周分母）、
インクリメント値Ｉnc （０≦Ｌ＜Ａ／４の範囲では Ｉnc＝Ｌ＋Ａ／２、 Ａ／４≦Ｌ＜３Ａ／４の範囲では Ｉnc＝Ｌ、 ３Ａ／４≦Ｌ＜Ａの範囲では Ｉnc＝Ｌ−A／２） を設定し、Ｌoを演算結果の値（初期値は不問）とし、
前記可変分周器出力信号がでる毎に、演算器はＩnc＋Ｌ
o→Ｌoの演算を行い、その結果を判定し、Ｌo＜Ａの時
分周器を低分周比側に切り換え、またＬo≧Ａの時
Ｌo−Ａ→Ｌoとし、分周器を高分周比側に切り換える様
に制御するものである（請求項５）。Means for Solving the Problems The input signal is divided by a control signal from a frequency divider control circuit which operates based on an external control signal so that the frequency division ratio is N-1, N, N + 1,. , And by switching the frequency division ratio of the variable frequency divider, the average frequency division number (N + L / A) (N, L,
(A is an integer), the frequency division ratio is switched every time a frequency divider output signal is output, and the same frequency division ratio becomes 2
Alternatively, control is performed so as not to be continued more than three times. The object of the present invention can be achieved by the configuration of the phase locked loop circuit and the following. The output of the voltage controlled oscillator is frequency-divided by a fixed frequency divider, and the output is divided into N-1 and N by a control signal from a frequency divider control circuit operating based on an external control signal. , N +
A variable frequency divider that can be varied as in 1,..., A phase comparator that compares the phase of its output with a reference frequency, an LPF that receives its output and removes high-frequency components, A fractional frequency divider including the voltage-controlled oscillator that can be varied, and capable of obtaining an average frequency division number (N + L / A) (N, L, and A are integers) by switching a frequency division ratio of a variable frequency divider In the above, there is provided a frequency divider control circuit which can control the frequency division ratio every time a variable frequency divider output signal is output so that the same frequency division ratio does not continue more than two or three times. Item 1). A variable component capable of changing the output of the reference frequency by a control signal from a frequency divider control circuit operating based on an external control signal so that the frequency division ratio can be varied as N-1, N, N + 1,. A frequency divider, a phase comparator that compares the output of the voltage-controlled oscillator with an output obtained by dividing the output by a fixed frequency divider, an LPF that receives the output and removes high-frequency components, and an oscillation frequency determined by the output. The voltage-controlled oscillator capable of changing the frequency division ratio, and switching the frequency division ratio of the variable frequency divider to obtain an average frequency division number (N + L / A) (N, L, and A are integers). There is a frequency divider control circuit that can switch the frequency division ratio every time a variable frequency divider output signal is output in the cycle, so that the same frequency division ratio is controlled not to be continued more than two or three times ( Claim 2). The output of the voltage-controlled oscillator can be varied by a control signal from a frequency divider control circuit that operates based on an external control signal so that the frequency division ratio can be varied as N-1, N, N + 1,. A frequency divider, a phase comparator that compares the output with a reference frequency, and an LP that receives the output and removes high-frequency components
F and the voltage-controlled oscillator capable of changing the oscillation frequency by its output, and by switching the frequency division ratio of the variable frequency divider, the average frequency division number (N + L / A) (N,
(L and A are integers), so that the frequency division ratio is switched every time a variable frequency divider output signal is output so that the same frequency division ratio does not continue more than two or three times. There is a frequency divider control circuit that can be controlled. The frequency divider control circuit includes at least a variable frequency divider, a calculator that operates by an output of the variable frequency divider, and a switching controller that controls the variable frequency divider based on the calculation result. The frequency divider control circuit divides N-1 and N + 1 in the range of 0 ≦ L <A / 3, and divides N and N + 1 in the range of 1/3 ≦ L <2A / 3, 2A In the range of / 3 ≦ L <A, the overflow determination value A is supplied to the arithmetic unit by an external control signal using two sets of frequency division ratios in the variable frequency divider that divides by N and divides by N + 2.
(However, A is a fractional denominator), and the increment value Inc is Inc = (L + A) / 2 in the range of 0 ≦ L <A / 3, and Inc = L, 2A in the range of A / 3 ≦ L <2A / 3. In the range of / 3 ≦ L <A, set Inc = L / 2, and set Lo as the value of the calculation result (the initial value is unquestioned),
Every time the variable frequency divider output signal is output, the arithmetic unit is Inc + L
The calculation of o → Lo is performed, the result is determined, and when Lo <A, the frequency divider is switched to the lower frequency division ratio side, and Lo ≧ A
In this case, control is performed such that Lo-A → Lo, and the frequency divider is switched to the high frequency division ratio side (claim 4). The frequency divider control circuit includes at least a variable frequency divider, a calculator that operates by an output of the variable frequency divider, and a switching controller that controls the variable frequency divider based on the calculation result. In the range of 0 ≦ L <A / 4, the frequency divider control circuit performs N- ／ frequency division (N−1 frequency division operation, N
Fractional frequency division for one-time frequency division), N + 1/2 frequency division (fractional frequency division for one-time operation of N + 1 frequency division, and N + 1 frequency division, A / 4 ≦ L) In the range of <3A / 4, N and N + 1 frequency division, and in the range of 3A / 4 ≦ L <A, the two frequency division ratios in the variable frequency divider that are N + 1/2 frequency division and N + 3/2 frequency division are Using the external control signal, the arithmetic unit is provided with an overflow judgment value A (fractional division denominator),
Increment value Inc (Inc = L + A / 2 in the range of 0 ≦ L <A / 4, Inc = L in the range of A / 4 ≦ L <3A / 4, Inc = L− in the range of 3A / 4 ≦ L <A. A / 2) is set, and Lo is set as the value of the operation result (the initial value is unquestioned).
Every time the variable frequency divider output signal is output, the arithmetic unit is Inc + L
The calculation of o → Lo is performed, the result is determined, and when Lo <A, the frequency divider is switched to the low frequency division ratio side, and when Lo ≧ A,
Lo−A → Lo, and control is performed so that the frequency divider is switched to the high frequency division ratio side (claim 5).
【０００６】[0006]
【発明の実施の形態】＜実施例１＞本発明のＰＬＬシン
セサイザブロック図１、その分数分周制御ブロック図６
において ０≦Ｌ＜Ａ／３の範囲では、 Ｎ−１、Ｎ＋１分周 Ａ／３≦Ｌ＜２Ａ／３の範囲では、Ｎ、Ｎ＋１分周 ２Ａ／３≦Ｌ＜Ａの範囲では、 Ｎ、Ｎ＋２分周 となる２つの分周比を切り換えて分周出力を得るように
する。分周器制御回路２の内の演算器１６、切換制御器
１５では可変分周器１の出力信号Ｆ１が発生する毎に下
記の様な（演算）動作を行う。 オーバーフロー判定値Ａ：分数分周分母 インクリメント値Ｉnc ：０≦Ｌ＜Ａ／３の範囲では、Ｉnc＝(Ｌ＋Ａ)／２ Ａ／３≦Ｌ＜２Ａ／３の範囲では、Ｉnc＝Ｌ ２Ａ／３≦Ｌ＜Ａの範囲では、Ｉnc＝Ｌ／２ Ｌoを演算結果の値（初期値は不問）とすると、 動作 可変分周器１の出力信号F1にて演算器はＩnc＋
Ｌo→Ｌoの演算を行う。その結果を判定し 動作 Ｌo＜Ａの時 分周器を低分周側に切り換え
る。 動作 Ｌo≧Ａの時 Ｌo−Ａ→Ｌoとし、分周器を高
分周側に切り換える。 つまり、（Ｎ＋Ｌ／Ａ）×１０mＨzを（Ｎ＋Ｌ／Ａ）分
周して、１０mＨzを得る場合、その周波数によって、図
７の組み合わせの２組の分周比を使用する。すると分周
比はF１クロック1が１または２回で必ず切り替わること
になる（図８参照）。例えば、Ａを100以上や1000以上
とした場合、分周器の繰り返しを周期Ｔとした基本周波
数成分及びその低次高調波成分は小さくなる代わりに、
高次高調波成分が増大する。この成分は位相比較器４、
及びＬＰＦ６（ＰＬＬループフィルタ）を通してＶＣＯ
１に変調を与え、出力周波数に不要周波数成分を発生さ
せる（図９参照）。この高次高調波成分による不要周波
数成分は、F0からの離調周波数が図５の場合に比べ大き
いため、ＰＬＬのループ応答が実用上支障ない程度でＬ
ＰＦ６（ＰＬＬループフィルタ）のカットオフ周波数を
下げることにより、容易に除去できる（図１０参照）。<Embodiment 1> A PLL synthesizer block diagram 1 of the present invention and a fractional frequency division control block diagram 6 thereof
In the range of 0 ≦ L <A / 3, N−1, N + 1 division. In the range of A / 3 ≦ L <2A / 3, N, N + 1 division. In the range of 2A / 3 ≦ L <A, N, Two frequency division ratios of N + 2 frequency division are switched to obtain a frequency divided output. The arithmetic unit 16 and the switching controller 15 in the frequency divider control circuit 2 perform the following (arithmetic) operation every time the output signal F1 of the variable frequency divider 1 is generated. Overflow determination value A: Fractional frequency division denominator Increment value Inc: In the range of 0 ≦ L <A / 3, Inc = (L + A) / 2 In the range of A / 3 ≦ L <2A / 3, Inc = L 2A / 3 In the range of ≦ L <A, if Inc = L / 2 Lo is set as the value of the calculation result (the initial value is unquestioned), the operation of the calculation unit is Inc +
The calculation of Lo → Lo is performed. The result is determined and the operation is performed when Lo <A. The frequency divider is switched to the low frequency dividing side. Operation When Lo ≧ A Lo−A → Lo, and switches the frequency divider to the higher frequency division side. That, (N + L / A) a × 10 m Hz (N + L / A) min and division, the case of obtaining a 10 m Hz, with its frequency, using two sets of frequency division ratio of the combination of FIG. Then, the frequency division ratio always switches once or twice in F1 clock 1 (see FIG. 8). For example, when A is set to 100 or more or 1000 or more, the fundamental frequency component and its low-order harmonic component whose cycle T is the repetition of the frequency divider are reduced,
Higher harmonic components increase. This component is phase comparator 4,
And VCO through LPF6 (PLL loop filter)
1 is modulated to generate an unnecessary frequency component in the output frequency (see FIG. 9). The unnecessary frequency component due to the higher harmonic component has a detuning frequency from F0 greater than that in the case of FIG. 5, so that the loop response of the PLL does not hinder practical use.
It can be easily removed by lowering the cutoff frequency of PF6 (PLL loop filter) (see FIG. 10).
【０００７】＜実施例２＞他の実施例として、Ｎ−１、
Ｎ、Ｎ＋１・・・の分周器及びその組み合わせによるＮ
−1/2分周（Ｎ−１分周１回動作に引き続きＮ分周を１
回動作をさせる分数分周）、Ｎ＋1/2分周（Ｎ＋１分周
１回動作に引き続きＮ分周を１回動作をさせる分数分
周）・・・を発生させることができる分数分周制御ブロ
ック図１１（平均分周数＝Ｎ＋Ｌ／Ａ分周）にて、 ０≦Ｌ＜Ａ／４の範囲では、 Ｎ−１／２、Ｎ＋１／２分周 Ａ／４≦Ｌ＜３Ａ／４の範囲では、Ｎ、Ｎ＋１分周 ３Ａ／４≦Ｌ＜Ａの範囲では、 Ｎ＋１／２、Ｎ＋３／２分周 となる分周比（組合せ）を切り換えて分周出力を得るよ
うにする。分数分周制御回路４２の内の演算器５６、切
換制御器５５では可変分周器１の出力信号F1が発生する
毎に下記の様な（演算）動作を行う。 オーバーフロー判定値Ａ：分数分周分母 インクリメント値Ｉnc ：０≦Ｌ＜Ａ／４の範囲では、Ｉnc＝Ｌ＋Ａ／２ Ａ／４≦Ｌ＜３Ａ／４の範囲では、Ｉnc＝Ｌ ３Ａ／４≦Ｌ＜Ａの範囲では、Ｉnc＝Ｌ−Ａ／２ Ｌoを演算結果の値（初期値は不問）とすると、 動作は、可変分周器１の出力信号F1にて演算器５６は
Ｉnc＋Ｌo→Ｌoの演算を行う。その結果を判定し 動作 Ｌo＜Ａの時には、分周器を低分周側に切り換
える。 動作 Ｌo≧Ａの時には、Ｌo−Ａ→Ｌoとし、分周器
を高分周側に切り換える。 つまり、（Ｎ＋Ｌ／Ａ）×１０ｍＨｚを（Ｎ＋Ｌ／Ａ）
分周して、１０ｍＨｚを得る場合、その周波数によっ
て、図１２の組み合わせの分周比を使用する。すると分
周比は３回よりも多くの回数で連続することがない（図
８または図１３参照）。この場合、分周比が繰り返しが
３回の場合もあるが、前記実施例１と同様に、分周器の
繰り返しを周期Ｔとした基本周波数成分及びその低次高
調波成分は小さくなる代わりに、高次高調波成分が増大
する。この成分は位相検波器４、及びＬＰＦ６を通して
ＶＣＯ１に変調を与え、出力周波数に不要周波数成分を
発生させるが、この高次高調波成分による不要周波数成
分は、F0からの離調周波数が図５の場合に比べ大きいた
め、ＰＬＬのループ応答も実用上支障ない程度で、ＬＰ
Ｆ６（ＰＬＬループフィルタ）のカットオフ周波数を下
げることにより、容易に除去できる（図１０参照）。そ
の他の実施例として、図１４の様に電圧制御発振器７と
可変分周器１の間に固定分周器５７を追加することによ
り、図１の場合に比べ高い周波数を発生させるＰＬＬ回
路を実現することが可能である。また、図１５の様に、
基準周波数側に分数分周制御回路を挿入することによ
り、電圧制御発振器出力側に分数分周制御回路を挿入し
た場合と同等のＰＬＬシンセサイザを組むこともでき
る。<Embodiment 2> As another embodiment, N-1,
N by N, N + 1... Frequency dividers and their combinations
-1/2 frequency division (N-1 frequency division is performed once,
Fractional division control block capable of generating N + 1/2 frequency division (N + 1 frequency division one operation and subsequent N frequency division one operation)... In FIG. 11 (average frequency division = N + L / A frequency division), in the range of 0 ≦ L <A / 4, the frequency division of N−1 / 2 and N + 1/2 A / 4 ≦ L <3A / 4 In the range of N, N + 1 frequency division 3A / 4 ≦ L <A, a frequency division ratio (combination) of N + 1/2 and N + 3/2 frequency division is switched to obtain a frequency division output. The arithmetic unit 56 and the switching controller 55 in the fractional frequency dividing control circuit 42 perform the following (calculating) operation every time the output signal F1 of the variable frequency divider 1 is generated. Overflow determination value A: Fractional division denominator Increment value Inc: In the range of 0 ≦ L <A / 4, Inc = L + A / 2 A / 4 ≦ L <3A / 4, Inc = L 3A / 4 ≦ L In the range of <A, if Inc = LA−2Lo is taken as the value of the operation result (the initial value is unquestioned), the operation is performed by the output signal F1 of the variable frequency divider 1 and the operation unit 56 operates as Inc + Lo → Lo. Perform the operation. The result is determined and the operation is performed. When Lo <A, the frequency divider is switched to the low frequency dividing side. Operation When Lo ≧ A, Lo−A → Lo, and the frequency divider is switched to the higher frequency dividing side. That is, (N + L / A) × 10 mHz is changed to (N + L / A)
When dividing to obtain 10 mHz, the frequency division ratio of the combination of FIG. 12 is used depending on the frequency. Then, the frequency division ratio does not continue more than three times (see FIG. 8 or FIG. 13). In this case, although the frequency division ratio may be repeated three times, as in the first embodiment, the fundamental frequency component and its low-order harmonic component whose period is the repetition of the frequency divider is reduced instead of being reduced. , Higher harmonic components increase. This component modulates the VCO 1 through the phase detector 4 and the LPF 6 to generate an unnecessary frequency component in the output frequency. The unnecessary frequency component due to the higher-order harmonic component has a detuning frequency from F0 of FIG. Since the loop response of the PLL is practically no problem,
By reducing the cutoff frequency of F6 (PLL loop filter), it can be easily removed (see FIG. 10). As another embodiment, by adding a fixed frequency divider 57 between the voltage controlled oscillator 7 and the variable frequency divider 1 as shown in FIG. 14, a PLL circuit which generates a higher frequency than that of FIG. 1 is realized. It is possible to Also, as shown in FIG.
By inserting the fractional frequency division control circuit on the reference frequency side, a PLL synthesizer equivalent to the case where the fractional frequency division control circuit is inserted on the output side of the voltage controlled oscillator can be assembled.
【０００８】[0008]
【発明の効果】周波数分解能に比べて比較周波数を高く
設定できる分数分周制御ＰＬＬ方式で発生するスプリア
スノイズを、安価で簡単な構造の制御方式で軽減でき
る。According to the present invention, spurious noise generated by the fractional frequency division control PLL system in which the comparison frequency can be set higher than the frequency resolution can be reduced by an inexpensive and simple control system.
【図１】本発明のＰＬＬシンセサイザを示すブロック図
である。FIG. 1 is a block diagram showing a PLL synthesizer of the present invention.
【図２】従来技術のＰＬＬシンセサイザを示すブロック
図である。FIG. 2 is a block diagram showing a prior art PLL synthesizer.
【図３】従来技術の分数分周制御ブロック図である。FIG. 3 is a block diagram of a conventional fractional frequency division control.
【図４】従来技術の分数分周制御を示すタイミング図で
ある。FIG. 4 is a timing chart showing fractional frequency division control according to the related art.
【図５】従来技術の分数分周制御回路を使用したＰＬＬ
シンセサイザの出力スペクトラムの図である。FIG. 5 shows a PLL using a fractional frequency dividing control circuit of the prior art.
FIG. 3 is a diagram of an output spectrum of a synthesizer.
【図６】本発明の分数分周制御ブロック図である。FIG. 6 is a block diagram of a fractional frequency dividing control according to the present invention.
【図７】本発明による被分周周波数と分周に使用する分
周器組合せの関係を示す図である。FIG. 7 is a diagram showing a relationship between a frequency to be divided and a frequency divider combination used for frequency division according to the present invention.
【図８】本発明による分周器切り換えと繰り返し周期Ｔ
との関係を示すタイミング図である。FIG. 8 shows frequency divider switching and repetition period T according to the present invention.
FIG. 6 is a timing chart showing a relationship with the above.
【図９】本発明の分数分周制御回路を使用したＰＬＬシ
ンセサイザの出力スペクトラムの図である。FIG. 9 is a diagram of an output spectrum of a PLL synthesizer using the fractional frequency division control circuit of the present invention.
【図１０】本発明の分数分周制御回路を使用したＰＬＬ
シンセサイザでＬＰＦのカットオフ周波数を図９より低
く設定した時の出力スペクトラムの図である。FIG. 10 shows a PLL using the fractional frequency dividing control circuit of the present invention.
FIG. 10 is a diagram of an output spectrum when the cutoff frequency of the LPF is set lower than that in FIG. 9 in the synthesizer.
【図１１】図６とは別の実施例による分数分周制御ブロ
ック図である。FIG. 11 is a fractional frequency division control block diagram according to another embodiment different from FIG. 6;
【図１２】被分周周波数と分周に使用する分周器組合せ
の関係を示す図である。FIG. 12 is a diagram illustrating a relationship between a frequency to be divided and a frequency divider combination used for frequency division.
【図１３】本発明による分周器切り換えと繰り返し周期
Ｔとの関係を示すタイミング図である。FIG. 13 is a timing chart showing a relationship between frequency divider switching and a repetition period T according to the present invention.
【図１４】本発明を応用したＰＬＬシンセサイザ示すブ
ロック図である。FIG. 14 is a block diagram showing a PLL synthesizer to which the present invention is applied.
【図１５】本発明を応用した別のＰＬＬシンセサイザ示
すブロック図である。FIG. 15 is a block diagram showing another PLL synthesizer to which the present invention is applied.
Claims (5)
周し、その出力を、外部からの制御信号をもとに動作す
る分周器制御回路からの制御信号によって分周比をＮ−
１、Ｎ、Ｎ＋１、・・・の様に可変できる可変分周器
と、 その出力と基準周波数とを位相比較する位相比較器と、 その出力を入力し高周波成分を除去するＬＰＦと、 その出力により発振周波数を変化させることができる前
記電圧制御発振器と、 可変分周器の分周比を切り換えることにより平均分周数
（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、Ａは整数）を得ることができ
る分数分周にて、可変分周器出力信号が出る毎に分周比
を切り換えて、同じ分周比が２または３回よりも多く連
続しない様に制御することができる分周器制御回路と、
を備えた、 ことを特徴とする位相同期ループ回路。An output of a voltage controlled oscillator is frequency-divided by a fixed frequency divider, and the output is divided by a control signal from a frequency divider control circuit operating based on an external control signal to a frequency division ratio of N. −
A variable frequency divider that can be varied as 1, N, N + 1,..., A phase comparator that compares the output with a reference frequency, an LPF that receives the output and removes high-frequency components, and an output The average frequency division number (N + L / A) (N, L, and A are integers) can be obtained by switching the frequency division ratio of the variable frequency divider and the voltage controlled oscillator capable of changing the oscillation frequency by A frequency divider control circuit capable of switching the frequency division ratio every time a variable frequency divider output signal is output in fractional frequency division so that the same frequency division ratio is controlled not to be continued more than two or three times; ,
A phase-locked loop circuit comprising:
号をもとに動作する分周器制御回路からの制御信号によ
って分周比をＮ−１、Ｎ、Ｎ＋１、・・・の様に可変で
きる可変分周器と、 その出力と電圧制御発振器の出力を固定分周器で分周し
た出力とを位相比較する位相比較器と、 その出力を入力し高周波成分を除去するＬＰＦと、その
出力により発振周波数を変化させることができる前記電
圧制御発振器と、 可変分周器の分周比を切り換えることにより平均分周数
（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、Ａは整数）を得ることができ
る分数分周にて、可変分周器出力信号が出る毎に分周比
を切り換えて、同じ分周比が２または３回よりも多く連
続しない様に制御することができる分周器制御回路と、
を備えた、 ことを特徴とする位相同期ループ回路。2. The output of the reference frequency is controlled by a control signal from a frequency divider control circuit that operates based on an external control signal so that the frequency division ratio is N-1, N, N + 1,. A variable frequency divider that can be varied; a phase comparator that compares the output of the voltage-controlled oscillator with an output obtained by dividing the output by a fixed frequency divider; an LPF that receives the output and removes high-frequency components; The voltage-controlled oscillator capable of changing the oscillation frequency according to the output; and obtaining the average frequency division number (N + L / A) (N, L, and A are integers) by switching the frequency division ratio of the variable frequency divider. A frequency divider control circuit that can switch the frequency division ratio every time a variable frequency divider output signal is output in the possible frequency division so that the same frequency division ratio does not continue more than two or three times. When,
A phase-locked loop circuit comprising:
御信号をもとに動作する分周器制御回路からの制御信号
によって分周比をＮ−１、Ｎ、Ｎ＋１、・・・の様に可
変できる可変分周器と、 その出力と基準周波数とを位相比較する位相比較器と、 その出力を入力し高周波成分を除去するＬＰＦと、 その出力により発振周波数を変化させることができる前
記電圧制御発振器と、 可変分周器の分周比を切り換えることにより平均分周数
（Ｎ＋Ｌ／Ａ）（Ｎ、Ｌ、Ａは整数）を得ることができ
る分数分周にて、可変分周器出力信号が出る毎に分周比
を切り換えて、同じ分周比が２または３回よりも多く連
続しない様に制御することができる分周器制御回路と、
を備えた、 ことを特徴とする位相同期ループ回路。3. The output of the voltage-controlled oscillator is controlled by a control signal from a frequency divider control circuit that operates based on an external control signal so that the frequency division ratio is N-1, N, N + 1,. A variable frequency divider, a phase comparator that compares the output with a reference frequency, an LPF that receives the output and removes a high-frequency component, and the voltage that can change an oscillation frequency by the output. The output of the variable frequency divider can be obtained by changing the frequency division ratio of the control oscillator and the variable frequency divider to obtain an average frequency division number (N + L / A) (N, L and A are integers). A frequency divider control circuit capable of switching the frequency division ratio every time a signal is output and controlling the same frequency division ratio not to be continued more than 2 or 3 times;
A phase-locked loop circuit comprising:
と、その可変分周器の出力により動作する演算器と、そ
の演算結果により可変分周器を制御する切換制御器と、
を少なくとも備え、当該分周器制御回路は、 ０≦Ｌ＜Ａ／３の範囲では、 Ｎ−１分周とＮ＋１分周、 １／３≦Ｌ＜２Ａ／３の範囲では、Ｎ分周とＮ＋１分周、 ２Ａ／３≦Ｌ＜Ａの範囲では、 Ｎ分周とＮ＋２分周 となる可変分周器内の２組の分周比を用いて、 外部からの制御信号により前記演算器にオーバーフロー
判定値Ａ（但し、Ａは分数分周分母）、 インクリメント値Ｉncを ０≦Ｌ＜Ａ／３ の範囲では Ｉnc＝（Ｌ＋Ａ）／２， Ａ／３≦Ｌ＜２Ａ／３の範囲では Ｉnc＝Ｌ， ２Ａ／３≦Ｌ＜Ａ の範囲では Ｉnc＝Ｌ／２ と設定し、 Ｌoを演算結果の値（初期値は不問）とし、 前記可変分周器出力信号がでる毎に、演算器はＩnc＋Ｌ
o→Ｌoの演算を行い、その結果を判定し、 Ｌo＜Ａの時には、分周器を低分周比側に切り換え、 また、 Ｌo≧Ａの時には、Ｌo−Ａ→Ｌoとし、分周器を高分周
比側に切り換える様に制御するものである、ことを特徴
とする請求項３記載の位相同期ループ回路。4. The frequency divider control circuit includes: a variable frequency divider; an arithmetic unit that operates by an output of the variable frequency divider; a switching controller that controls the variable frequency divider based on the operation result;
And the frequency divider control circuit includes N-1 frequency division and N + 1 frequency division in the range of 0 ≦ L <A / 3, and N frequency division in the range of 1/3 ≦ L <2A / 3. In the range of N + 1 frequency division and 2A / 3 ≦ L <A, the arithmetic unit is supplied to the arithmetic unit by an external control signal by using two sets of frequency division ratios in the variable frequency divider, which are N frequency division and N + 2 frequency division. The overflow determination value A (where A is a fractional denominator), and the increment value Inc is Inc = (L + A) / 2 in the range of 0 ≦ L <A / 3, and Inc in the range of A / 3 ≦ L <2A / 3. = L, 2A / 3 ≦ L <A, set Inc = L / 2, and set Lo as the value of the operation result (the initial value is irrelevant). Each time the variable frequency divider output signal is output, the operation unit Is Inc + L
The calculation of o → Lo is performed, and the result is determined. When Lo <A, the frequency divider is switched to the low frequency division ratio side. When Lo ≧ A, Lo−A → Lo, and the frequency divider is changed. 4. The phase-locked loop circuit according to claim 3, wherein the phase-locked loop circuit is controlled so as to switch to a high frequency division ratio.
と、その可変分周器の出力により動作する演算器と、そ
の演算結果により可変分周器を制御する切換制御器と、
を少なくとも備え、当該分周器制御回路は、 可変分周器と、その可変分周器の出力により動作する演
算器とその演算結果により可変分周器を制御する切換制
御器のある分周器制御回路にて、 ０≦Ｌ＜Ａ／４の範囲では、 Ｎ−１／２分周（Ｎ−１分周１回動作に引き続きＮ分周
を１回動作をさせる分数分周）とＮ＋１／２分周（Ｎ＋
１分周１回動作に引き続きＮ分周を１回動作をさせる分
数分周）とＮ＋１分周、 Ａ／４≦Ｌ＜３Ａ／４の範囲では、ＮとＮ＋１分周、 ３Ａ／４≦Ｌ＜Ａの範囲ではＮ＋１／２分周とＮ＋３／
２分周となる可変分周器内の２組の分周比を用いて、外
部からの制御信号により前記演算器にオーバーフロー判
定値Ａ（分数分周分母）、インクリメント値Ｉnc （０≦Ｌ＜Ａ／４の範囲では Ｉnc＝Ｌ＋Ａ／２、 Ａ／４≦Ｌ＜３Ａ／４の範囲では Ｉnc＝Ｌ、 ３Ａ／４≦Ｌ＜Ａの範囲では Ｉnc＝Ｌ−A／２） を設定し、Ｌoを演算結果の値（初期値は不問）とし、
前記可変分周器出力信号がでる毎に、演算器はＩnc＋Ｌ
o→Ｌoの演算を行い、その結果を判定し、 Ｌo＜Ａの時 分周器を低分周比側に切り換え、 また Ｌo≧Ａの時 Ｌo−Ａ→Ｌoとし、 分周器を高分周比側に切り換える様に制御するものであ
る、ことを特徴とする請求項３記載の位相同期ループ回
路。5. The frequency divider control circuit includes: a variable frequency divider; an arithmetic unit that operates by an output of the variable frequency divider; a switching controller that controls the variable frequency divider based on the operation result;
The frequency divider control circuit comprises: a variable frequency divider; a frequency divider having an arithmetic unit operated by an output of the variable frequency divider; and a switching controller for controlling the variable frequency divider based on the operation result. In the control circuit, in the range of 0 ≦ L <A / 4, N− ／ frequency division (fractional frequency division in which N−1 frequency division is performed once and N frequency division is performed once) and N + 1 / Dividing by 2 (N +
(Numerical frequency division for performing one frequency division and one operation for N frequency division), N + 1 frequency division, and N / N + 1 frequency division and 3A / 4≤L in the range of A / 4 ≦ L <3A / 4 In the range of <A, N + 1/2 frequency division and N + 3 /
Using two sets of frequency division ratios in the variable frequency divider that divides by two, an overflow control value A (fractional frequency denominator) and an increment value Inc (0 ≦ L < Inc = L + A / 2 in the range of A / 4, Inc = L in the range of A / 4 ≦ L <3A / 4, and Inc = LA−2 in the range of 3A / 4 ≦ L <A. Let Lo be the value of the operation result (the initial value is irrelevant),
Every time the variable frequency divider output signal is output, the arithmetic unit is Inc + L
The calculation of o → Lo is performed, the result is determined, and when Lo <A, the frequency divider is switched to the low frequency division ratio side. When Lo ≧ A, Lo−A → Lo, and the frequency divider is set to high 4. The phase locked loop circuit according to claim 3, wherein the phase locked loop circuit is controlled so as to switch to the cycle ratio side.
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|---|---|---|---|
| JP2000048790A JP2001237700A (en) | 2000-02-25 | 2000-02-25 | Phase-locked loop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008028683A (en) * | 2006-07-20 | 2008-02-07 | Fujitsu Ltd | Phase-locked oscillator |
| US7652542B2 (en) | 2004-05-17 | 2010-01-26 | Nec Corporation | Signal generator, and transmitter, receiver and transceiver using same |
| JP2011080910A (en) * | 2009-10-08 | 2011-04-21 | Seiko Epson Corp | Signal generation circuit, frequency measurement device including the signal generation circuit, and signal generation method |
| JP2012505609A (en) * | 2008-10-08 | 2012-03-01 | クゥアルコム・インコーポレイテッド | Clock cleanup phase lock loop (PLL) |
-
2000
- 2000-02-25 JP JP2000048790A patent/JP2001237700A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7652542B2 (en) | 2004-05-17 | 2010-01-26 | Nec Corporation | Signal generator, and transmitter, receiver and transceiver using same |
| JP2008028683A (en) * | 2006-07-20 | 2008-02-07 | Fujitsu Ltd | Phase-locked oscillator |
| JP2012505609A (en) * | 2008-10-08 | 2012-03-01 | クゥアルコム・インコーポレイテッド | Clock cleanup phase lock loop (PLL) |
| JP2011080910A (en) * | 2009-10-08 | 2011-04-21 | Seiko Epson Corp | Signal generation circuit, frequency measurement device including the signal generation circuit, and signal generation method |
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