CN205356307U - Frequency synthesizer of short wave receiver - Google Patents
Frequency synthesizer of short wave receiver Download PDFInfo
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- CN205356307U CN205356307U CN201521136094.1U CN201521136094U CN205356307U CN 205356307 U CN205356307 U CN 205356307U CN 201521136094 U CN201521136094 U CN 201521136094U CN 205356307 U CN205356307 U CN 205356307U
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Abstract
The utility model discloses a frequency synthesizer of short wave receiver, this kind of frequency synthesizer of short wave receiver includes: a local oscillator loop, crystal oscillator, two local oscillator loops, a local oscillator loop includes: R frequency divider, phase frequency detector, charge pump, a loop filter, a voltage controlled oscillator, direct digital formula frequency synthesizer circuit, first local oscillator signal, two local oscillator loops include: phase -locked loop circuit, the 2nd loop filter, the 2nd voltage controlled oscillator, second local oscillator signal, can export "Frequency" and "Frequency" value after the crystal oscillator circular telegram, will "Frequency" and "Frequency" value are sent to R frequency divider and phase -locked loop circuit.
Description
Technical field
This utility model relates to frequency synthesizer technique field, particularly to the frequency synthesizer of a kind of short-wave receiver.
Background technology
Development along with communication technology, people have increasingly higher requirement in performance with portability, therefore people are also more and more higher to the requirement of frequency source, need to realize low spurious, Low phase noise, bandwidth, frequency resolution is high, integrated level is high frequency synthesizer, but, current frequency synthesizer is also difficult to meet the demand.
Summary of the invention
For above existing problems, the purpose of this utility model is in that to propose the frequency synthesizer of a kind of short-wave receiver, broadband one local oscillator that the frequency synthesizer of this kind of short-wave receiver produces has ultralow phase noise and spurious performance and high frequency resolution, and two local oscillators that the frequency synthesizer of this kind of short-wave receiver produces adopt the phase-locked loop chip of super Low phase noise, can having the two local oscillator points frequencies with a local oscillator same performance index, simultaneously a local oscillator all have employed digital phase-locked loop technology respectively and improves spuious with index of making an uproar mutually with two local oscillators.
For reaching above-mentioned technical purpose, this utility model adopts the following technical scheme that and is achieved.
A kind of frequency synthesizer of short-wave receiver, including: the first local oscillator loop, crystal oscillator, the second local oscillator loop.
Described first local oscillator loop, including: R frequency divider, phase frequency detector, electric charge pump, the first loop filter, the first voltage controlled oscillator, Direct Digital Synthesizer circuit, the first local oscillation signal；Phase frequency detector comprises first input end, the second input and two outfans, the first input end of the outfan electrical connection phase frequency detector of described Direct Digital Synthesizer circuit；The outfan of the second input electrical connection R frequency divider of phase frequency detector；Described electric charge pump has two inputs, is electrically connected two outfans of phase frequency detector；Electric charge delivery side of pump electrically connects the input of the first loop filter, and the outfan of the first loop filter electrically connects the input of the first voltage controlled oscillator；Described first voltage controlled oscillator has two outfans, is electrically connected the input of Direct Digital Synthesizer and the outfan of the first local oscillation signal；
Described second local oscillator loop, including: phase-locked loop circuit, the second loop filter, the second voltage controlled oscillator, the second local oscillation signal；Phase-locked loop circuit comprises the first phase-locked input and the second phase-locked input；The outfan of phase-locked loop circuit electrically connects the input of the second loop filter, and the outfan of described second loop filter electrically connects the input of the second voltage controlled oscillator；Described second voltage controlled oscillator has two outfans, is electrically connected the first phase-locked input of phase-locked loop circuit and the outfan of the second local oscillation signal；
Described crystal oscillator comprises first crystal outfan, the second crystal outfan, and described first crystal outfan electrically connects the input of described R frequency divider, and described second crystal outfan electrically connects the second phase-locked input of described phase-locked loop circuit；
Export the first frequency of oscillation after crystal oscillator energising, and the first frequency of oscillation is delivered to R frequency divider divide, obtain the first local oscillator and send to phase frequency detector with reference to after phase demodulation frequency；Simultaneously, first voltage controlled oscillator output first vibration frequency, and send to Direct Digital Synthesizer circuit, Direct Digital Synthesizer circuit sends after exporting the first phase demodulation frequency accordingly to phase frequency detector, phase frequency detector is according to the first local oscillator reference phase demodulation frequency and the first phase demodulation frequency, respectively obtain the discharge and recharge level of described first local oscillator discharge and recharge level with reference to phase demodulation frequency and described first phase demodulation frequency, and it is respectively sent to electric charge pump, after electric charge pump is respectively completed charge/discharge operation according to the described discharge and recharge level of the first local oscillator reference phase demodulation frequency and the discharge and recharge level of described first phase demodulation frequency, output error voltage, described error voltage controls the first voltage controlled oscillator after the smothing filtering of the first loop filter, first loop is in the lock state, and obtain the signal of the first voltage controlled oscillator output when the first loop is in the lock state, it is the first local oscillation signal；
Output frequency of oscillation value after crystal oscillator energising, and described frequency of oscillation value is sent to phase-locked loop circuit, described frequency of oscillation value is carried out with reference to frequency dividing by phase-locked loop circuit, produces the second local oscillator with reference to phase demodulation frequency；Second voltage controlled oscillator sends after exporting the second local frequency to phase-locked loop circuit, described second local frequency is carried out frequency programmable dividing by phase-locked loop circuit, produce the second phase demodulation frequency, then phase-locked loop circuit is according to the second local oscillator reference phase demodulation frequency and the second phase demodulation frequency, export an error voltage value, described error voltage value controls the second voltage controlled oscillator after the smothing filtering of the second loop filter, second loop is in the lock state, and obtain the signal of the second voltage controlled oscillator output when the second loop is in the lock state, it is the second local oscillation signal；
Feature of the present utility model and further improvement is that:
Described Direct Digital Synthesizer (DDS) circuit is variable Fractional-N divider.
Described phase-locked loop circuit is the up-to-date phase-locked loop chip that AD company produces, and model is ADF4113, is a kind of phase discriminator chip including electric charge pump, and its phase noise is non-normally low.
Described phase frequency detector is made up of an independent double D trigger and a multichannel NAND gate, and described double D trigger model is 74HC74D, and described multichannel NAND gate model is 74HC00.
The frequency combining method of described short-wave receiver also includes: the first local oscillator loop and the second local oscillator loop are respectively necessary for data port line, and respectively external microprocessor provides, totally 4, the data port line that first local oscillator loop comprises, be respectively as follows: the Fractional-N frequency device that controls Direct Digital Synthesizer (DDS) circuit time flare line, the first data port line, latch mouth line and reset mouth line；Totally 3, the data port line that second local oscillator loop comprises, be respectively as follows: control phase-locked loop circuit time flare line, the second data port line and enable mouth line；The wherein time flare line and control the time flare line of phase-locked loop circuit of the Fractional-N frequency device of Direct Digital Synthesizer (DDS) circuit, and the first data port line and the second data port line respectively common port line.
Described control Direct Digital Synthesizer (DDS) circuit also comprises four mouth line inputs, be electrically connected the Fractional-N frequency device that controls Direct Digital Synthesizer (DDS) circuit time flare line output terminal, the first data port line output terminal, latch mouth line output terminal and reset mouth line output terminal.
Described phase-locked loop circuit also comprises three mouth line inputs, be electrically connected control phase-locked loop circuit time flare line output terminal, the second data port line output terminal and enable mouth line output terminal.
The integrated circuit modules of described electric charge pump and described voltage controlled oscillator respectively individual packages.
Described first loop filter and the second loop filter respectively resistance capacitance (RC) passive low ventilating filter.
The beneficial effects of the utility model: highly integrated property phaselocked loop of the present utility model can be greatly promoted the interference free performance of shortwave equipment, have and better make an uproar mutually and spuious index；Meanwhile, Fractional-N divider and integrated voltage-controlled improvement can be greatly promoted the phase noise in wide-band and spurious performance, more can be suitably used for the shortwave equipment of high performance index requirement or system.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, this utility model is described in further detail.
Fig. 1 is the structural representation of a kind of short-wave receiver frequency synthesizer of the present utility model；
Fig. 2 is the electric charge pump structure schematic diagram used in this utility model；
Fig. 3 is the modularization design figure that this utility model peripheral microprocessor controls DDS circuit；
Fig. 4 is the modularization design figure that this utility model peripheral microprocessor controls PLL circuit；
Fig. 5 a is the first local oscillator loop (the first loop) of the present utility model is output spectrum test figure during 10kHz in frequency span；
Fig. 5 b is the output phase noise test figure of the first local oscillator loop (the first loop) of the present utility model；
Fig. 6 a is the frequency span of the second local oscillator loop (the second loop) of the present utility model is output spectrum test figure during 10kHz；
Fig. 6 b is the output phase noise test figure of the second local oscillator loop (the second loop) of the present utility model.
Detailed description of the invention
With reference to Fig. 1, for the structural representation of a kind of short-wave receiver frequency synthesizer of the present utility model, the frequency synthesizer of this kind of short-wave receiver, including: crystal oscillator, the first local oscillator loop, the second local oscillator loop；Wherein, the first local oscillator loop, the second local oscillator loop also respectively the first loop, the second loop.
Described crystal oscillator, for crystal oscillator temperature compensating crystal oscillator, its standard frequency is 18.432MHz.For high-resolution shortwave equipment, the frequency source of its high accuracy, high stability and near-end low phase noise selects to be very important, and therefore the present embodiment selects degree of stability to be 0.5 × 10-7The compensated oscillator with thermistor compensation network of/d；Meanwhile, in order to improve the first loop and the phase noise specifications of the second loop；Wherein, R is integer.
Described first local oscillator loop, including: R frequency divider, phase frequency detector, electric charge pump, the first loop filter (ADC circuit), the first voltage controlled oscillator (VCO), Direct Digital Synthesizer (DDS circuit), the first local oscillation signal；Described phase frequency detector comprises first input end, the second input and two outfans；The outfan of described Direct Digital Synthesizer electrically connects the first input end of described phase frequency detector, and the second input of described phase frequency detector electrically connects the outfan of described R frequency divider；Described electric charge pump has two inputs, is electrically connected two outfans of phase frequency detector；Described electric charge delivery side of pump electrically connects the input of the first loop filter (ADC circuit), and the outfan of the first loop filter electrically connects the input of the first voltage controlled oscillator；Described first voltage controlled oscillator has two outfans, is electrically connected the input of Direct Digital Synthesizer and the outfan of the first local oscillation signal.
Wherein, described R frequency divider, R is 4 fixing frequency dividings, and the input of R frequency divider electrically connects the outfan of described crystal oscillator, and described R frequency divider is for dividing the output signal of described crystal oscillator, and the frequency representation of the output signal obtained is fpd, the output signal frequency of crystal oscillator is expressed as fref, then fpd=fref/ R；R frequency divider is independently realized 4 frequency dividings by the double D trigger that model is 74HC74D, it is not necessary to carried out Data Control frequency dividing by microprocessor, so that circuit is simplified, the phase demodulation frequency needed for phase frequency detector (PFD) is 6.408MHz.
Described phase frequency detector (PFD) is made up of the multichannel NAND gate that the independent double D trigger that a model is 74HC74D and model are 74HC00；Second input of described phase frequency detector electrically connects the outfan of described R frequency divider so that the output signal frequency of described R frequency divider is coupled in described phase frequency detector, and namely the outfan of described R frequency divider is for providing the comparison frequency of described phase frequency detector.
With reference to Fig. 2, for the electric charge pump structure schematic diagram used in this utility model, described electric charge pump has two inputs, is electrically connected two outfans of phase frequency detector；Described electric charge pump adopts the integration pump circuit module of individual packages, has higher precision.
Specifically, exporting the frequency of oscillation of 18.432MHz after crystal oscillator energising, and the frequency of oscillation of 18.432MHz is delivered to R frequency divider carry out 4 frequency dividings, first local oscillator of output 4.608MHz sends to phase frequency detector (f with reference to after phase demodulation frequencyR)；, sending to Direct Digital Synthesizer (DDS) circuit after the first voltage controlled oscillator output first vibration frequency, Direct Digital Synthesizer (DDS) circuit exports the first phase demodulation frequency f accordingly meanwhileDRear transmission to phase frequency detector, phase frequency detector to first local oscillator of 4.608MHz with reference to phase demodulation frequency and the first phase demodulation frequency fDCarry out frequency and phase analysis, respectively obtain the discharge and recharge level of described first local oscillator reference phase demodulation frequency and described first phase demodulation frequency fDDischarge and recharge level, and be respectively sent to electric charge pump, electric charge pump is according to described first local oscillator discharge and recharge level with reference to phase demodulation frequency and described first phase demodulation frequency fDDischarge and recharge level be respectively completed charge/discharge operation after, output error voltage, described error voltage is proportional to first local oscillator of 4.608MHz with reference to phase demodulation frequency and the first phase demodulation frequency fDBetween phase contrast, described error voltage controls the frequency of oscillation of the first voltage controlled oscillator after the smothing filtering of the first loop filter so that it is respectively towards reducing first local oscillator of 4.608MHz with reference to phase demodulation frequency and the first phase demodulation frequency fDDifference on the frequency and the change of phase contrast direction, until first local oscillator of 4.608MHz is with reference to phase demodulation frequency and the first phase demodulation frequency fDFrequency is respectively equal and first local oscillator of its 4.608MHz is with reference to phase demodulation frequency and the first phase demodulation frequency fDBetween phase contrast when being constant, the first loop is in the lock state, and is then exported signal when the first loop is in the lock state by the first voltage controlled oscillator, is the first required local oscillation signal；Wherein, totally 4, the data port line that the first local oscillator loop comprises, be respectively as follows: the Fractional-N frequency device that controls Direct Digital Synthesizer (DDS) circuit time flare line, the first data port line, latch mouth line and reset mouth line.
With reference to Fig. 3, control the modularization design figure of DDS circuit for this utility model peripheral microprocessor；Direct Digital Synthesizer (DDS) circuit in this utility model embodiment, i.e. Fractional-N divider, the incoming frequency of Direct Digital Synthesizer (DDS) circuit is expressed as fo, described foAlso it is the output frequency of the first local oscillator loop, the frequency synthesizer of a kind of short-wave receiver of the present utility model adopts PLL+DDS scheme to produce broadband first local oscillation signal of 47.099861～75.499761MHz/USB, and namely the reference frequency output of described first local oscillator loop (the first loop) is 47.099861～75.499761MHz/USB；The output frequency of Direct Digital Synthesizer (DDS) circuit is expressed as fDDS, fDDSAlso be the second incoming frequency of described phase frequency detector, i.e. phase demodulation frequency, then the computing formula of the frequency dividing ratio N of the first local oscillator loop is: N=fDDS*232/fo, frequency dividing ratio N is also frequency control word, fDDSRepresent the output frequency during locking of Direct Digital Synthesizer (DDS) circuit loop and fDDS=4.608MHz；Wherein, N represents the decimal being not less than 0.
Such as: need the output frequency f of the first local oscillator loopoFor 65.5643MHz, then frequency dividing ratio N (being also frequency control word) N=4.608*232/ 65.5643=(11FE02D1)H=(10001111111100000001011010001)B.In conjunction with Fig. 3, controlling the modularization design figure of DDS circuit for this utility model peripheral microprocessor, DDS circuit uses serial input, there are 40 Bits Serial clock signals, when rising edge clock signal, data signal write depositor, an often data signal of write, reset signal will by high step-down；And often writing a data signal, latch signal is by will being uprised by low, and wherein low level latch signal is effective.
Described second local oscillator loop, including: phaselocked loop (PLL) circuit, the second loop filter, the second voltage controlled oscillator, the second local oscillation signal；Phase-locked loop circuit comprises the first phase-locked input and the second phase-locked input；The outfan of phase-locked loop circuit electrically connects the input of the second loop filter, and the outfan of described second loop filter electrically connects the input of the second voltage controlled oscillator；Described second voltage controlled oscillator has two outfans, is electrically connected the first phase-locked input of phase-locked loop circuit and the outfan of the second local oscillation signal.
Described crystal oscillator comprises first crystal outfan, the second crystal outfan, and described first crystal outfan electrically connects the input of described R frequency divider, and described second crystal outfan electrically connects the second phase-locked input of described phase-locked loop circuit.Crystal oscillator can export frequency of oscillation and frequency of oscillation value after powering on, described frequency of oscillation and frequency of oscillation value are respectively sent to R fraction frequency device input end and phase-locked loop circuit first input end.
In this utility model embodiment, described second local oscillator loop is two local oscillator phaselocked loop (PLL) circuit, described second local oscillator phase-locked loop circuit adopts AD company to produce, model is the phaselocked loop phase discriminator chip of ADF4113, described phaselocked loop phase discriminator chip is that one has ultralow phase noise, and include the phase discriminator chip of electric charge pump, comprise the digital phase frequency detector of a low noise, one electric charge pump accurately, the M frequency divider able to programme of the R parametric frequency divider of one 14-bit and a 19-bit, the M frequency divider able to programme of described 19-bit comprises the A enumerator of a 6-bit, the B enumerator of one 13-bit and dual-modulus prescaler M/M+1；Wherein, M represents the decimal being not less than 0.
Microcomputer control signal is sent to phaselocked loop (PLL) circuit, the frequency of oscillation value of 18.432MHz is exported by crystal oscillator after being energized, and send to phaselocked loop (PLL) circuit, frequency of oscillation and the microcomputer control signal of 18.432MHz are carried out with reference to frequency dividing by phaselocked loop (PLL) circuit, produce the second local oscillator with reference to phase demodulation frequency (fr)；Second voltage controlled oscillator sends after exporting the second local frequency to phase-locked loop circuit, and the second local frequency is carried out frequency programmable dividing by phase-locked loop circuit, produces the second phase demodulation frequency (fv)；Then phase-locked loop circuit is to the second local oscillator reference phase demodulation frequency frWith the second phase demodulation frequency fvCarrying out frequency and phase bit comparison respectively, export an error voltage value, described error voltage value is proportional to the second local oscillator with reference to phase demodulation frequency frWith the second phase demodulation frequency fvBetween phase contrast, described error voltage value controls the frequency of oscillation of the second voltage controlled oscillator after the smothing filtering of the second loop filter, so as to respectively towards reducing the second local oscillator with reference to phase demodulation frequency frWith the second phase demodulation frequency fvBetween difference on the frequency and the direction change of phase contrast, until the second local oscillator is with reference to phase demodulation frequency frWith the second phase demodulation frequency fvFrequency is respectively equal and the second local oscillator is with reference to phase demodulation frequency frWith the second phase demodulation frequency fvBetween phase contrast when being constant, the second loop is in the lock state, and finally exports the signal of the second voltage controlled oscillator output when the second loop is in the lock state, is the second required local oscillation signal；Wherein, totally 3, the data port line that the second local oscillator loop comprises, be respectively as follows: control phase-locked loop circuit time flare line, the second data port line and enable mouth line；The wherein time flare line and control the time flare line of phase-locked loop circuit of the Fractional-N frequency device of Direct Digital Synthesizer (DDS) circuit, and the first data port line and the second data port line respectively common port line.
In conjunction with Fig. 4, the modularization design figure of phase-locked loop circuit is controlled for this utility model peripheral microprocessor, described external microprocessor controls phase-locked loop circuit, its signal comprised has: data signal, clock signal and enable signal three kinds, while described external microprocessor controls each group of data of phase-locked loop circuit, data signal can be sent respectively, clock signal and enable signal, each group of data have 24 clock signals, described clock signal is rising edge, and enable signal is three 24 bit shift register that data signal during low level writes phase-locked loop circuit successively, and data signal during high level preferentially writes, successively by data signal, clock signal and enable signal write initialization register, R register and M depositor；Wherein, the output frequency of the second local oscillator loop is 45.999861MHz, it is 18.432MHz with reference to mark frequency, taking phase demodulation frequency is 18432 ÷ 115=160.2783kHz, namely reference frequency dividing ratio is R=115, M=45999.861 ÷ 160.2783=287=B (13) × P+A (6)=35 × 8+7.R represents the reference frequency dividing ratio of integer, and M represents the decimal being not less than 0.
The first loop filter in this utility model embodiment and the second loop filter respectively three rank passive low ventilating filter, described three rank passive low ventilating filters are for carrying out low-pass filtering to the output signal of described electric charge pump.
The time flare line and control the time flare line of phase-locked loop circuit of the Fractional-N frequency device of Direct Digital Synthesizer (DDS) circuit in this utility model embodiment, and the first data port line and the second data port line respectively common port line.
The integration module circuit of described electric charge pump, described first voltage controlled oscillator and described second voltage controlled oscillator respectively individual packages.
Described first loop filter and the second loop filter respectively resistance capacitance (RC) passive low ventilating filter.
With reference to Fig. 5 a, it is output spectrum test figure during 10kHz for the first local oscillator loop (the first loop) of the present utility model in frequency span；With reference to Fig. 5 b, for the output phase noise test figure of the first local oscillator loop (the first loop) of the present invention；With reference to Fig. 6 a, the frequency span for the second local oscillator loop (the second loop) of the present utility model is output spectrum test figure during 10kHz；With reference to Fig. 6 b, the output phase noise for the second local oscillator loop (the second loop) of the present utility model tests figure.In Fig. 5 a and Fig. 6 a, transverse axis represents the output frequency of frequency synthesizer, and the longitudinal axis represents the output level of frequency synthesizer, and unit is dBm；In Fig. 5 b and Fig. 6 b, transverse axis represents and the frequency interval of frequency synthesizer output signal frequency, and the longitudinal axis represents output power single sideband phase noise power in 1Hz bandwidth, and unit is dBc/Hz.
Obviously, this utility model can be carried out various change and modification without deviating from the spirit and scope of the present invention by those skilled in the art；So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. the frequency synthesizer of a short-wave receiver, it is characterised in that including: the first local oscillator loop, crystal oscillator, the second local oscillator loop；
Described first local oscillator loop, including: R frequency divider, phase frequency detector, electric charge pump, the first loop filter, the first voltage controlled oscillator, Direct Digital Synthesizer circuit, the first local oscillation signal；Phase frequency detector comprises first input end, the second input and two outfans, the first input end of the outfan electrical connection phase frequency detector of described Direct Digital Synthesizer circuit；The outfan of the second input electrical connection R frequency divider of phase frequency detector；Described electric charge pump has two inputs, is electrically connected two outfans of phase frequency detector；Electric charge delivery side of pump electrically connects the input of the first loop filter, and the outfan of the first loop filter electrically connects the input of the first voltage controlled oscillator；Described first voltage controlled oscillator has two outfans, is electrically connected the input of Direct Digital Synthesizer and the outfan of the first local oscillation signal；
Described second local oscillator loop, including: phase-locked loop circuit, the second loop filter, the second voltage controlled oscillator, the second local oscillation signal；Phase-locked loop circuit comprises the first phase-locked input and the second phase-locked input；The outfan of phase-locked loop circuit electrically connects the input of the second loop filter, and the outfan of described second loop filter electrically connects the input of the second voltage controlled oscillator；Described second voltage controlled oscillator has two outfans, is electrically connected the first phase-locked input of phase-locked loop circuit and the outfan of the second local oscillation signal；
Described crystal oscillator comprises first crystal outfan, the second crystal outfan, and described first crystal outfan electrically connects the input of described R frequency divider, and described second crystal outfan electrically connects the second phase-locked input of described phase-locked loop circuit；
Export the first frequency of oscillation after crystal oscillator energising, and the first frequency of oscillation is delivered to R frequency divider divide, obtain the first local oscillator and send to phase frequency detector with reference to after phase demodulation frequency；Simultaneously, first voltage controlled oscillator output first vibration frequency, and send to Direct Digital Synthesizer circuit, Direct Digital Synthesizer circuit sends after exporting the first phase demodulation frequency accordingly to phase frequency detector, phase frequency detector is according to the first local oscillator reference phase demodulation frequency and the first phase demodulation frequency, respectively obtain the discharge and recharge level of described first local oscillator discharge and recharge level with reference to phase demodulation frequency and described first phase demodulation frequency, and it is respectively sent to electric charge pump, after electric charge pump is respectively completed charge/discharge operation according to the described discharge and recharge level of the first local oscillator reference phase demodulation frequency and the discharge and recharge level of described first phase demodulation frequency, output error voltage, described error voltage controls the first voltage controlled oscillator after the smothing filtering of the first loop filter, first loop is in the lock state, and obtain the signal of the first voltage controlled oscillator output when the first loop is in the lock state, it is the first local oscillation signal；
Output frequency of oscillation value after crystal oscillator energising, and described frequency of oscillation value is sent to phase-locked loop circuit, described frequency of oscillation value is carried out with reference to frequency dividing by phase-locked loop circuit, produces the second local oscillator with reference to phase demodulation frequency；Second voltage controlled oscillator sends after exporting the second local frequency to phase-locked loop circuit, described second local frequency is carried out frequency programmable dividing by phase-locked loop circuit, produce the second phase demodulation frequency, then phase-locked loop circuit is according to the second local oscillator reference phase demodulation frequency and the second phase demodulation frequency, export an error voltage value, described error voltage value controls the second voltage controlled oscillator after the smothing filtering of the second loop filter, second loop is in the lock state, and obtain the signal of the second voltage controlled oscillator output when the second loop is in the lock state, it is the second local oscillation signal.
2. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that described first local oscillator loop and described second local oscillator loop are respectively necessary for data port line, and respectively external microprocessor provides.
3. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that described second local oscillator loop is the second local oscillator phase-locked loop circuit, described second local oscillator phase-locked loop circuit is the phaselocked loop phase discriminator chip of ADF4113.
4. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that described phase frequency detector is made up of the multichannel NAND gate that the independent double D trigger that a model is 74HC74D and model are 74HC00.
5. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that described Direct Digital Synthesizer circuit is variable decimal frequency divider.
6. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that the integrated circuit modules of described electric charge pump and described voltage controlled oscillator respectively individual packages.
7. the frequency synthesizer of a kind of short-wave receiver as claimed in claim 1, it is characterised in that described first loop filter and described second loop filter respectively resistance capacitance passive low ventilating filter.
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| CN201521136094.1U CN205356307U (en) | 2015-12-31 | 2015-12-31 | Frequency synthesizer of short wave receiver |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769830A (en) * | 2020-08-06 | 2020-10-13 | 成都凌德科技有限公司 | Broadband local oscillation circuit and local oscillation signal generating method |
| CN112688686A (en) * | 2020-12-14 | 2021-04-20 | 中电科仪器仪表有限公司 | Miniaturized broadband frequency synthesizer |
| CN113156374A (en) * | 2020-12-29 | 2021-07-23 | 南京理工大学 | Ku wave band three-channel receiving and transmitting assembly |
-
2015
- 2015-12-31 CN CN201521136094.1U patent/CN205356307U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769830A (en) * | 2020-08-06 | 2020-10-13 | 成都凌德科技有限公司 | Broadband local oscillation circuit and local oscillation signal generating method |
| CN112688686A (en) * | 2020-12-14 | 2021-04-20 | 中电科仪器仪表有限公司 | Miniaturized broadband frequency synthesizer |
| CN113156374A (en) * | 2020-12-29 | 2021-07-23 | 南京理工大学 | Ku wave band three-channel receiving and transmitting assembly |
| CN113156374B (en) * | 2020-12-29 | 2023-09-15 | 南京理工大学 | Ku wave band three-channel receiving and transmitting assembly |
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