CN202713275U - Narrowband frequency-adjustable PLL oscillation circuit - Google Patents

Abstract

The utility model provides a PLL oscillation circuit which is of high stability and capable of outputting specified-frequency (2.4GHz-2.5GHz) frequency points. According to the PLL oscillation circuit, phase comparison is performed on frequencies coming from an output end and pre-scaling signals of a reference frequency source; a phase difference adopted as control voltage is applied to a loop filter so as to control the circuit and enable the same to precisely set frequency division ratio of output frequencies so as to set the output frequencies; the noise and high frequency components in phase difference signals are filtered by the loop filter, and the filtered phase difference signals are applied to a VCO so as to control the frequency changes of the VCO, and as a result, a phase difference between input signals and VCO signals is gradually decreased, and a set frequency point of the out frequencies can be locked.

Description

The PLL oscillating circuit that narrow band frequency is adjustable

Technical field

The utility model relates to PLL(Phase Locked Loop, phase-locked loop) oscillating circuit, be particularly related to different frequency (2.400GHz---2.500GHz) set its stepping be N MHz(wherein N be integer), and show the signal frequency of current output by display unit.

Background technology

[technology in the past]

PLL is a negative feedback system, utilizes the back coupling signal in the loop, with signal frequency and the phase place of output, is locked on the frequency and phase place of input reference signal.

The phase-locked loop is a control system that realizes the phase place locking, and in the frequency synthesis of phase-locked loop, the phase-locked loop has the function of frequency stabilization.With the development of work communications satellite and measuring instrument technology, phase-locked time frequency synthesizer has been widely used as the high-frequency signals source.

PLL is comprised of phase comparator, loop filter, voltage controlled oscillator, frequency divider, as shown in Figure 3.

Main is applied in the wireless telecommunication system, use in the what transmitter and receiver phase-locked loop, with provide the local oscillations signal with the baseband signal raising frequency to radio-frequency (RF) signal, make communication system that larger capacity can be arranged, or radio-frequency (RF) signal to the intermediate-frequency band that antenna end receives carried out the signal demodulation.

The PLL oscillating circuit possesses: the signal behind the pre-frequency division of external reference signal and the signal behind the 1/N frequency division are compared the phase comparator of output phase difference signal (Phase Comparator); Charge pump (Charge Pump) with the Voltage-output phase difference of pulsewidth degree; To carry out the loop filter (Loop Filter) of smothing filtering from the output voltage of charge pump; By control the frequency output of voltage controlled oscillator from the control voltage of loop filter.

In addition, become the frequency signal of N*Fref during output signal.

The external reference source that utilizes high stability specifically as reference signal with through behind the frequency divider frequency division signal carry out the phase bit comparison, to draw a phase error voltage, noise effect by its high fdrequency component of loop filter filtering obtains a direct voltage and then control voltage controlled oscillator (VCO) is controlled, and generates and carry out high-precision signal.

The utility model content

The PLL oscillating circuit that PLL oscillating circuit is in the past particularly simulated needs adjust the parameter of circuit devcie when needing to export different frequency signals usually, may cause like this uncertainty of output signal.

Particularly when output signal was radio frequency (Radio Frequency) signal, different devices is the difference of the distributed constant of circuit together, may be that the aspects such as power of output signal impact.

The utility model is based on described truth and finishes, and its purpose is to provide a kind of simple and fast can export different frequency signals.

In order to solve described problem in the past, a kind of PLL oscillating circuit is provided, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit utilizes the output of voltage-controlled oscillator to carry out frequency division and compare with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of described voltage-controlled oscillator and export.The utility model provides a kind of PLL oscillating circuit, have: PLL IC, the input external reference signal with from the oscillation output signal of voltage controlled oscillator, carry out the comparison of phase place with reference signal to carrying out from the output signal of voltage controlled oscillator behind the Fractional-N frequency, detect phase difference and export the phase signal corresponding with this phase difference; Loop filter, employing be RC three rank passive filters, filtering is from the noise of the high fdrequency component in the phase error signal of PLL IC; Voltage controlled oscillator is according to good from process filtered phase error signal (control voltage) oscillation output signal; And arithmetic processing apparatus, comprise finger-impu system, show output device and monolithic microcomputer kernel device; It is input as keyboard to the setting of function frequency, and output is the current function of liquid crystal display and frequency on the one hand, on the other hand for exporting the Serial Control word of PLL IC.

The utility model provides a kind of PLL oscillating circuit, possess following characteristics: voltage controlled oscillator is according to exporting oscillation frequency signal through the voltage that is proportional to phase error behind the loop filtering according to the phase error signal of inputting (voltage) and oscillation frequency signal; Frequency divider carries out Fractional-N frequency to the frequency signal that feeds back to PLL IC; Phase comparator compares and detected phase is poor the phase place of signal and sine wave signal, and the output phase signal corresponding with this phase difference; Loop filter, the noise of the high fdrequency component in the filtering phase signal; Arithmetic processing apparatus utilizes keyboard input set-up function and frequency, and by software control and certain algorithm, the frequency values of setting is converted into PLL IC Serial Control word, and demonstrates corresponding function and frequency values in display unit; Described calculation process rises by keyboard and function display carries out the setting of output frequency; Can to (2.400GHz---2.500GHz) of frequency output take stepping as 1MHz or N MHz regulate; The frequency adjustment mode can be according to 2._** mode, 2.*_* mode or 2.**_ mode, selects the frequency band that will regulate by keypress function; Change in the register that serial data is input to PLL IC by algorithm, reach the purpose of setting output frequency.

The utility model is in described PLL oscillating circuit, because the frequency model that will export is

2.400GHz---2.500GHz, be to belong to radiofrequency signal, so the voltage controlled oscillator output frequency is radiofrequency signal output.

The utility model is in described PLL oscillating circuit, arithmetic processing apparatus has singlechip controller, the frequency values of input can be converted into the frequency division of the frequency ratio in the software programming of arithmetic processing apparatus, again frequency dividing ratio be changed into the control word of PLL IC, to reach the target of setting output frequency.

The utility model in described PLL oscillating circuit, simple and convenient for input mode, employing be 4*4 matrix keyboard input mode.

The utility model is in described PLL oscillating circuit, and the 16*2 liquid crystal indicator shows current frequency.

Description of drawings

Fig. 1 is the structured flowchart of the PLL oscillating circuit of execution mode of the present utility model.

Fig. 2 is the particular circuit configurations block diagram of PLL IC.

Fig. 3 is the structured flowchart of general oscillating circuit example.

Symbol description

1:PLL IC; 2: loop filter; 3: voltage controlled oscillator (VCO); 4: finger-impu system; 5: display unit; 6: operation control device; 7:14 bit R counter; 8: phase-frequency detector; 9: charge pump; 10: multiplexer; 11:6 bit A counter; 12:13 bit B counter; 13:P/P+1; 14:24 bit input register; 15: phase comparator; 16: charge pump; 17: loop filter; 18:VCO; 19: frequency divider (1/N).

Embodiment

With reference to accompanying drawing, execution mode of the present utility model is described.

The embodiment general introduction

The PLL oscillating circuit of execution mode of the present utility model has: voltage controlled oscillator; Integrated phase detector, the PLL IC of frequency divider, it is input external reference signal and from the oscillation output signal of voltage controlled oscillator, to two signals phase place compare, poor and the output phase signal corresponding with this phase difference of detected phase, and can input the serial data control word that gives with operation control device; Filtering is from the loop filter of the noise of the high fdrequency component in the PLL IC phase error signal; Can carry out the arithmetic and control unit that data are processed, keyboard data can be transferred to the Serial Control word of PLLIC, and data are inputed among the PLL IC; The frequency functionality display unit.

Oscillating circuit: Fig. 1.

With reference to Fig. 1, embodiment of the present utility model is described.Fig. 1 is the oscillating circuit structured flowchart of execution mode of the present utility model.

As shown in Figure 1, the PLL oscillating circuit figure of the execution mode of this utility model has PLLIC(Integrated Circuit basically, integrated circuit), loop filter, voltage controlled oscillator, arithmetic processing apparatus (MPU:Micro Processing Unit, microprocessor unit).

PLL oscillating circuit each several part

[PLL?IC]

PLL IC is input to terminal REFin with external reference source, and from VCO oscillation output signal is input to terminal RF IN A and terminal RF IN B, carries out the phase bit comparison and the voltage that falls pulse duration corresponding to phase difference outputs to loop filter as charge pump output.

Loop filter

Loop filter adopts be RC three rank passive filter filterings output is high fdrequency component noise in the phase signal from PLL IC, carry out smothing filtering and output to VCO.

[VCO]

The frequency that VCO expects by the output of vibrating from the control voltage change frequency of loop filter, and say that the part of output signal outputs among the PLL IC.

[MPU]

What MPU adopted is singlechip controller, input from 4*4 matrix keyboard input unit, and show output frequency by the 16*2 liquid crystal indicator, and to PLL IC output string line frequency control word, and be provided with reset key and mains switch.That is: MUP is according to the setting data of finger-impu system input, and signal is all the time outputed to the terminal CLK of PLL IC, and data-signal is outputed to the terminal DATA of PLL IC, is the terminal LE that can signal outputs to PLL IC with latching.

PLL?IC

With reference to Fig. 2, specify the PLL IC in the PLL oscillating circuit.Fig. 2 is the concrete circuit structure block diagram of PLL IC.In addition, the PLL IC of Fig. 2 represents that the 2.4GHz of Ya De promise semiconductor (Aanlogue Devices) is speciogenesis device PLL " ADF4113 ".

The ADF4113 clock generator be used for to consist of needs the stable reference signal of low-down noise

The pll clock source.

PLL IC has amplifier as shown in Figure 2,24 bit input registers (24-BIT INPUT REGISTER), differential amplifier, 14 bit R counters (14-BIT R COUNTER) R counter latchs circuit (R COUNTERLATCH), function latch cicuit (FUCTION LATCH), 13 bit B counters (13-BITCOUNTER), 6 bit A counters (6-BIT COUNTER), amplifier, phase-frequency detector (PHASE FREQUENCY DETECTOR), charge pump (CHARGE PUMP), reference circuit output (REFERENCE), lock detector (LOCK DETECTOR), the 1st present situation initialization circuit (CURRENT SETTING 1), the 2nd present situation initialization circuit (CURRENT SETTING 2), multiplexer (MUX), and amplifier.In the PLL oscillating circuit, externally during the output signal of reference clock 10MHz, VCO in the situation of 2.---2.5GHz, phase comparison frequency can be set as 1MHz.With 14 bit R(with reference to) counter (14-BITR COUNTER) be set as 10 frequency divisions (10MHz/10=1MHz), and:

Fvco=[（P*B）+A]*Fref/R

Wherein P is PRESCALER, B=Fvco/1000, A=Fvco-(32*(10000) B).

More than be the programmed algorithm that is converted into corresponding register by output frequency, the numeral of keyboard input can be changed into the frequency dividing ratio of digital frequency divider by above algorithm.

[effect of execution mode]

According to the input value of keyboard can to (2.400GHz---2.500GHz) of frequency output take stepping as 1MHz or N MHz regulate; The frequency adjustment mode can be according to 2._** mode, 2.*_* mode or 2.**_ mode, selects the frequency band that will regulate by keypress function; Change in the register that serial data is input to PLL IC by algorithm, reach the purpose of the output frequency of setting.Then can input the respective frequencies signal after determining, and lock speed is fast.

Claims (4)

1. PLL oscillating circuit that narrow band frequency is adjustable, it is characterized in that, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit utilizes the output of voltage-controlled oscillator to carry out frequency division and compare with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of described voltage-controlled oscillator and export, this PLL circuit is characterised in that to have:

Reference oscillator is as carrying out the reference of phase bit comparison with output signal;

Voltage controlled oscillator is according to the control voltage of inputting and oscillation frequency signal;

PLL IC, input external reference signal and from the oscillation output signal of described voltage controlled oscillator, phase place to two signals compares, poor and the output phase signal corresponding with phase difference of detected phase, and output represents lock-out state that described two signals are synchronous or the lock detecting signal of nonsynchronous released state;

Loop filter is removed the noise from the high fdrequency component in the phase signal of described PLL IC;

Arithmetic processing apparatus, by keyboard and display unit, to the PLLIC input initialization, function and frequency dividing ratio digital control word carry out assignment for the register of PLL IC, carry out the setting of function FREQUENCY CONTROL, to reach the Frequency point of output appointment.

2. PLL oscillating circuit that narrow band frequency is adjustable is characterized in that possessing:

Voltage controlled oscillator is according to exporting oscillation frequency signal through the voltage that is proportional to phase error behind the loop filtering;

Digital frequency divider carries out frequency division to the frequency signal that feeds back to PLL IC;

Phase comparator compares and detected phase is poor the phase place of signal and sine wave signal, exports the phase signal corresponding with this phase difference;

Loop filter, the high frequency noise components of filtering phase signal;

Arithmetic processing apparatus, the frequency control word of input appointment;

Described calculation process rises by keyboard and function display carries out the setting of output frequency; Can to (2.400GHz---2.500GHz) of frequency output take stepping as 1MHz or N MHz regulate; The frequency adjustment mode can be according to 2._** mode, 2.*_* mode or 2.**_ mode, selects the frequency band that will regulate by keypress function; Change in the register that serial data is input to PLL IC by algorithm, reach the purpose of setting output frequency.

3. PLL oscillating circuit according to claim 1, it is characterized in that: described arithmetic processing apparatus has singlechip controller, 4*4 matrix keyboard input unit, the 16*2 liquid crystal indicator, wherein singlechip controller is provided with a reset key and mains switch.

4. PLL oscillating circuit according to claim 1 is characterized in that: what described loop filter adopted is RC three rank passive filters.

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