CN102447475A - Phase locked loop (PLL) oscillating circuit with adjustable narrow-band frequency - Google Patents

Abstract

The invention provides a phase locked loop (PLL) circuit which can output a frequency point with designated frequency (2.4 to 2.5GHz) and also has high stability. In the PLL circuit, the phase comparison of the frequency from an output end and a frequency pre-dividing signal of a reference frequency source is carried out, a phase difference is used as control voltage added onto a loop filter, and the frequency dividing proportion of the output frequency can be accurately set by a control circuit so as to set the output frequency. After noise and high-frequency component are filtered off by the loop filter, the output frequency is added onto a voltage controlled oscillator (VCO) so as to control the frequency change of the VCO, so that the phase difference between an input signal and a VCO signal is gradually decreased, and finally, the set frequency point is output in a locked way.

Description

The PLL oscillating circuit that narrow band frequency is adjustable

Technical field

The present invention relates to PLL (Phase Locked Loop; Phase-locked loop) oscillating circuit; Its stepping of setting that is particularly related to different frequency (2.400GHz---2.500GHz) is N MHz (wherein N is an integer), and shows the signal frequency of current output through display unit.

Background technology

[technology in the past]

PLL is a negative feedback system, in the loop, utilizes the back coupling signal, with the signal frequency and the phase place of output, is locked on the frequency and phase place of input reference signal.

The phase-locked loop is a control system that realizes phase locking, and in the frequency synthesis of phase-locked loop, the phase-locked loop has the function of frequency stabilization.With the development of work communications satellite and measuring instrument technology, lock returns frequency synthesizer mutually and has been widely used as the high-frequency signals source.

PLL is made up of phase comparator, loop filter, voltage controlled oscillator, frequency divider, and is as shown in Figure 3.

Main is applied in the wireless telecommunication system; Use in the what transmitter and receiver phase-locked loop; With provide the local oscillations signal with the baseband signal raising frequency to RF signal, make communication system that bigger capacity can be arranged, or RF signal to the intermediate frequency frequency range that antenna end receives carried out the signal demodulation.

The PLL oscillating circuit possesses: to external reference signal presort frequently after signal and the signal behind the 1/N frequency division compare the phase comparator of output phase difference signal (Phase Comparator); Charge pump (Charge Pump) with the voltage phase difference output of pulsewidth degree; To carry out the loop filter (Loop Filter) of smothing filtering from the output voltage of charge pump; Through control the frequency output of voltage controlled oscillator from the control voltage of loop filter.

Become the frequency signal of N*Fref when in addition, exporting signal.

Be the external reference source that utilizes high stability specifically as reference signal with through behind the frequency divider frequency division signal carry out bit comparison mutually; To draw a phase error voltage; Noise effect through its high fdrequency component of loop filter filtering obtains a direct voltage and then control voltage controlled oscillator (VCO) is controlled, and generates and carry out high-precision signal.

Summary of the invention

The PLL oscillating circuit that PLL oscillating circuit is in the past particularly simulated needs adjust the parameter of circuit devcie when needing to export different frequency signals usually, may cause the uncertainty of output signal like this.

Particularly when the output signal was radio frequency (Radio Frequency) signal, different devices is the difference of the distributed constant of circuit together, possibly be that the aspects such as power of output signal impact.

The present invention is based on said truth and accomplishes, and its purpose is to provide a kind of simple and fast can export different frequency signals.

In order to solve said problem in the past; The invention provides a kind of PLL oscillating circuit; Have: PLLIC; The input external reference signal with from the oscillation output signal of voltage controlled oscillator, the output signal from voltage controlled oscillator is carried out carrying out the comparison of phase place with reference signal behind the Fractional-N frequency, detect phase difference and export the phase signal corresponding with this phase difference; Loop filter, filtering is from the noise of the high fdrequency component in the phase error signal of PLL IC; Voltage controlled oscillator is according to good from process filtered phase error signal (control voltage) oscillation output signal; And arithmetic processing apparatus, comprise finger-impu system, show output device and monolithic microcomputer kernel device; It is input as the setting of keyboard to the function frequency, and output is current function of liquid crystal display and frequency on the one hand, on the other hand for exporting the Serial Control word of PLL IC.

The present invention provides a kind of PLL oscillating circuit, possesses: voltage controlled oscillator is according to the phase error signal of being imported (voltage) and oscillation frequency signal; Frequency divider carries out Fractional-N frequency to this frequency signal; Phase comparator compares and detected phase is poor the phase place of signal and sine wave signal, and the output phase signal corresponding with this phase difference; Loop filter, the noise of the high fdrequency component in the filtering phase signal; Arithmetic processing apparatus utilizes keyboard input set-up function and frequency values, and through software control and certain algorithm, the frequency values of setting is converted into PLL IC Serial Control word, and on display unit, demonstrates corresponding function and frequency values.

The present invention because the frequency model that will export is 2.400GHz---2.500GHz, is to belong to radiofrequency signal in said PLL oscillating circuit, so the voltage controlled oscillator output frequency is radiofrequency signal output.

The present invention can be converted into the frequency division of the frequency ratio with the frequency values of input in the software programming of arithmetic processing apparatus in said PLL oscillating circuit, frequency dividing ratio is changed into the control word of PLL IC, to reach the target of setting output frequency again.

The present invention in said PLL oscillating circuit, simple and convenient for input mode, employing be 4*4 matrix keyboard input mode.

The present invention is in said PLL oscillating circuit, and display unit only needs the simple current frequency that shows.

Description of drawings

Fig. 1 is the structured flowchart of the PLL oscillating circuit of execution mode of the present invention.

Fig. 2 is the particular circuit configurations block diagram of PLL IC.

Fig. 3 is the structured flowchart of general oscillating circuit.

Symbol description

1:PLL IC; 2: loop filter; 3: voltage controlled oscillator (VCO); 4: finger-impu system; 5: display unit; 6: operation control device; 7:14 bit R counter; 8: phase-frequency detector; 9: charge pump; 10: multiplexer; 11:6 bit A counter; 12:13 bit B counter; 13:P/P+1; 14:24 bit input register; 15: phase comparator; 16: charge pump; 17: loop filter; 18:VCO; 19: frequency divider (1/N).

Embodiment

With reference to accompanying drawing, execution mode of the present invention is described.

The embodiment general introduction

The PLL oscillating circuit of execution mode of the present invention has: voltage controlled oscillator; Integrated phase detector; The PLL IC of frequency divider; It is input external reference signal and from the oscillation output signal of voltage controlled oscillator; To two signals phase place compare detected phase difference and export the phase signal corresponding, and can import the serial data control word that gives with operation control device with this phase difference; Filtering is from the loop filter of the noise of the high fdrequency component in the PLL IC phase error signal; Can carry out the arithmetic and control unit of data processing, can keyboard data be transferred to the Serial Control word of PLLIC, and data are inputed among the PLL IC; The frequency functionality display unit.

Oscillating circuit: Fig. 1.

With reference to Fig. 1, embodiment of the present invention are described.Fig. 1 is the oscillating circuit structured flowchart of execution mode of the present invention.

As shown in Figure 1; The PLL oscillating circuit figure of this working of an invention mode has PLLIC (Integrated Circuit basically; Integrated circuit), loop filter, voltage controlled oscillator, arithmetic processing apparatus (MPU:Micro Processing Unit, microprocessor unit).

PLL oscillating circuit each several part

[PLL?IC]

PLL IC is input to terminal REFin with external reference source; And from VCO oscillation output signal is input to terminal RF IN A and terminal RF IN B, carries out the phase bit comparison and the voltage that falls the corresponding pulse duration of phase difference outputs to loop filter as charge pump output.

Loop filter

Output is the high fdrequency component noise in the phase signal from PLL IC in the loop filter filtering, carries out outputing to VCO behind the smothing filtering.

[VCO]

VCO is through the output desired frequency of vibrating from the control voltage of loop filter change frequency, and says that the part of output signal outputs among the PLL IC.

[MPU]

MUP imports from the matrix keyboard input unit, and shows output frequency through liquid crystal indicator, and to PLL IC output serial frequency control word.That is: MUP is according to the setting data of finger-impu system input, and signal is all the time outputed to the terminal CLK of PLL IC, and data-signal is outputed to the terminal DATA of PLL IC, is the terminal LE that can signal outputs to PLL IC with latching.

PLL?IC

With reference to Fig. 2, specify the PLL IC in the PLL oscillating circuit.Fig. 2 is the concrete circuit structure block diagram of PLL IC.In addition, the PLL IC of Fig. 2 representes that the 2.4GHz of Ya De promise semiconductor (Aanlogue Devices) is speciogenesis device PLL " ADF4113 ".

The ADF4113 clock generator is used to constitute the stable reference signal of the low-down noise of needs

The pll clock source.

PLL IC is as shown in Figure 2, has amplifier, 24 bit input registers (24-BIT INPUT REGISTER), differential amplifier, 14 bit R counters (14-BIT R COUNTER) R counter and latchs circuit (R COUNTERLATCH), function latch cicuit (FUCTION LATCH), 13 bit B counters (13-BIT COUNTER), 6 bit A counters (6-BIT COUNTER), amplifier, phase-frequency detector (PHASE FREQUENCY DETECTOR), charge pump (CHARGE PUMP), reference circuit output (REFERENCE), lock detector (LOCK DETECTOR), the 1st present situation initialization circuit (CURRENT SETTING 1), the 2nd present situation initialization circuit (CURRENT SETTING 2), multiplexer (MUX) and amplifier.In the PLL oscillating circuit, externally during the output signal of reference clock 10MHz, VCO under the situation of 2.4---2.5GHz, can phase comparison frequency be set at 1MHz.With 14 bit R (reference) counters (14-BIT R COUNTER) be set at 10 frequency divisions (10MHz/10=1MHz), and:

Fvco＝[(P*B)+A]*Fref/R

Wherein P is PRESCALER, B=Fvco/1000, A=Fvco-(32* (10000) B).

More than be the programmed algorithm that is converted into corresponding register by output frequency, can the numeral of keyboard input be changed into the frequency dividing ratio of digital frequency divider by above algorithm.

[effect of execution mode]

Can export corresponding frequency according to the input value of keyboard, and frequency is regulated with the stepping of N MHz.Its display mode be 2._ _ _ GHz, the position of need regulating through the keyboard function key selection, frequency setting just then.The frequency signal of exportable correspondence then after confirming, and lock speed is fast.

Claims (4)

1. PLL circuit; Have voltage-controlled oscillator with bit comparison mutually if only; This phase bit comparison compares with the phase place of reference signal if only frequency division is carried out in the output of how said voltage-controlled oscillator; Will be based on the signal of phase difference as the control voltage of said voltage-controlled oscillator and export, this PLL circuit is characterised in that to have:

Reference oscillator is as carrying out the reference of bit comparison mutually with the output signal;

Voltage controlled oscillator is according to the control voltage of being imported and oscillation frequency signal;

PLL IC; Input external reference signal and from the oscillation output signal of said voltage controlled oscillator; Phase place to two signals compares; Detected phase difference and export the phase signal corresponding, and the lock-out state of said two signal Synchronization of output expression or the lock detecting signal of nonsynchronous released state with phase difference;

Loop filter is removed the noise from the high fdrequency component in the phase signal of said PLL IC;

Arithmetic processing apparatus, through keyboard and display unit, to PLL IC input initialization, function and frequency dividing ratio digital control word carry out assignment for the register of PLL IC, carry out the setting of function FREQUENCY CONTROL, to reach output specified frequency point.

2. PLL oscillating circuit is characterized in that possessing:

Voltage controlled oscillator is according to exporting oscillation frequency signal through the voltage that is proportional to phase error behind the loop filtering;

Digital frequency divider carries out frequency division to the frequency signal that feeds back to PLL IC;

Phase comparator compares and detected phase is poor the phase place of signal and sine wave signal, exports the phase signal corresponding with this phase difference;

Loop filter, the high frequency noise components of filtering phase signal;

Arithmetic processing apparatus, input specified frequency control word;

Described calculation process rises through keyboard and function display carries out the setting of output frequency.Can be that 1MHz or N MHz regulate with the stepping to (2.400GHz---2.500GHz) of frequency output.The frequency adjustment mode can be according to 2._** mode, 2.*_* mode or 2.**_ mode, selects the frequency band that will regulate through keypress function.Change in the register that serial data is input to PLLIC through algorithm, reach the purpose of setting output frequency.

3. PLL circuit according to claim 1 is characterized in that: described arithmetic processing apparatus has singlechip controller, 4*4 matrix keyboard input unit, and the 16*2 liquid crystal indicator, wherein singlechip controller is provided with a reset key and mains switch.

4. PLL circuit according to claim 1 is characterized in that: what described loop filter adopted is RC three rank passive filters.

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