CN110581708B - Frequency-locked loop type full digital frequency synthesizer - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The application relates to a frequency-locked loop type all-digital frequency synthesizer. The method comprises the following steps: the device comprises a frequency discriminator module, a frequency integration module and a frequency tuning module; the frequency discriminator module, frequency integral module and frequency tuning module connect gradually, and the output end signal feedback of the output of frequency tuning module is to the frequency discriminator module, and the frequency discriminator module includes: the variable frequency counter is used for comparing with the frequency control word to obtain an integer frequency error; the time-to-digital converter is used for obtaining fractional frequency errors, the frequency discriminator module is also used for adding the integer frequency errors and the fractional frequency errors to obtain system frequency errors, the frequency integration module is used for obtaining system phase errors, and the frequency tuning module is used for receiving the system phase errors and processing the system phase errors to obtain output end signals and output the output end signals. The invention can avoid the problem of incapability of locking caused by fuzzy phase error while realizing all functions of the phase-locked loop type all-digital frequency synthesizer.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and in particular, to a frequency-locked loop type all-digital frequency synthesizer.
Background
The analog frequency synthesizer based on the charge pump phase-locked loop structure has a high requirement on the stability of a loop due to poor matching and non-ideal characteristics of an analog circuit module, meanwhile, along with the gradual development of an integrated circuit process, the matching and non-ideal characteristics of a device become more obvious, the advanced process can further reduce the power supply Voltage, and the design margin of the circuit and the single-sub-band frequency tuning range of a Voltage-Controlled Oscillator (VCO) can be further compressed. In addition, the frequency synthesizer design method based on the analog circuit has poor portability and high design complexity, and particularly under the condition of a wide frequency range, the compromise factors are more.
The method for solving the problems is a Digital design of an analog circuit, namely, an All-Digital Frequency Synthesizer (ADFS) structure is adopted, the concept of the ADFS is firstly proposed and designed and realized by doctor R.B. Staszewski of TI company in 2003, and the method mainly aims to solve a series of design problems of the Frequency Synthesizer under a deep submicron CMOS process and realize the efficient integration of the Frequency Synthesizer in a System on Chip (SoC), the production of the design technology greatly accelerates the digitalization process of the Frequency Synthesizer, and most of high-performance ADFS designed at present can be compared with the performance of the analog Frequency Synthesizer, but has a simpler design process, smaller area and lower power consumption.
Until now, all the ADFS circuit structures are implemented based on the phase-locked loop architecture, but the system structure faces an unavoidable design difficulty: the Variable Phase Accumulator (VPA) and the Reference Phase Accumulator (RPA) belong to a continuous Digital Phase Accumulator, and since the bit length of the Digital Accumulator is limited, the initial output frequency of the Digital-controlled Oscillator (DCO) is greatly different from the expected output frequency, and the loop bandwidth of the Phase-locked loop is small (the proportional factor and the integral factor in the proportional-integral filter are set to be small, which results in a small feedback rate of the system), and the two accumulators have asynchronous overflow (for the Accumulator of a bit, the fuzzy value is 2 a If multiple asynchronous overflows occur within a system synchronous clock cycle, the ambiguity value is 2 ab Where b is the number of asynchronous overflows), thereby causing the situation that the difference (phase error) between the two is fuzzy, introducing large pulse fluctuation in the loop, prolonging the locking time of the loop, and even causing the loss of lock of the loop when the difference is serious. For the case of single asynchronous overflow, a fuzzy compensation unit (the working principle of the fuzzy compensation unit is to judge according to the input system phase error and a preset threshold value, and then compensate the system phase error according to a fuzzy value and outputActual system phase error), but the bit width of the accumulator and the coefficient of the loop filter must be carefully designed by adopting the compensation method, and simulation verification of the situation of multiple edges is performed, so as to avoid the situation of multiple asynchronous overflow of the accumulator in one system synchronous clock period, otherwise, the fuzzy compensation unit still cannot completely avoid the generation of pulse fluctuation in the system phase error, which undoubtedly greatly increases the workload of design, especially when designing an all-digital frequency synthesizer with a wide frequency output range.
Disclosure of Invention
Therefore, in order to solve the above technical problems, it is necessary to provide a frequency-locked loop type full digital frequency synthesizer capable of solving the problem that the phase difference ambiguity in the full digital frequency synthesizer based on the phase-locked loop architecture causes the loop locking time to be prolonged and even the loop cannot be locked.
A frequency-locked loop type full digital frequency synthesizer, comprising:
the frequency detector comprises a frequency detector module, a frequency integration module and a frequency tuning module;
the frequency discriminator module, the frequency integration module and the frequency tuning module are sequentially connected, and an output end signal of an output end of the frequency tuning module is fed back to the frequency discriminator module;
the frequency discriminator module comprises:
the variable frequency counter is connected with the output end of the frequency tuning module, counts the output frequency of the output end signal and compares the output frequency with a frequency control word to obtain an integer frequency error;
the time-to-digital converter is used for respectively calibrating the time quantum that the input reference frequency signal at the current moment and the input reference frequency signal at the previous moment leads the output end signal at the rising edge moment of the system synchronous signal, and normalizing the period of the output end signal according to the difference of the time quantum to obtain a fractional frequency error;
the frequency discriminator module is also used for adding the integer frequency error and the decimal frequency error to obtain a system frequency error;
the frequency integration module is used for receiving the system frequency error, accumulating the system frequency error and limiting amplitude to obtain a system phase error;
and the frequency tuning module is used for receiving the system phase error, processing the system phase error, obtaining and outputting an output end signal.
In one embodiment, the variable frequency counter comprises: m-stage pre-frequency dividers and serial carry binary counters;
the m-stage prepositive frequency divider reduces the frequency of the output end signal by 2 m Multiplying and providing a counting result of high bits; the serial carry binary counter accumulates the output frequency signals of the m-stage prescalers and provides a technical result of low bit.
In one embodiment, the internal flip-flop of the variable frequency counter is a true one-way clock architecture flip-flop.
In one embodiment, the real unidirectional clock structure trigger is a real unidirectional clock D trigger with a trigger reset function; the true unidirectional clock D flip-flop further comprises: the output end signal of the inverter is input into the inverter to carry out inversion and delay operation, and the output end of the inverter is connected with the input end of the AND gate; and the output end signal and the signal output by the output end of the phase inverter are subjected to AND operation in the AND gate to generate a high-level reset pulse, and the high-level reset pulse is used for resetting the true unidirectional clock D trigger.
In one embodiment, the internal flip-flop of the variable frequency counter is implemented using a current mode logic structure.
In one embodiment, the discriminator module further comprises: a retiming unit to generate the system synchronization signal in frequency correspondence with the input reference frequency signal from the output end signal and the input reference frequency signal.
In one embodiment, the frequency integration module comprises: and the amplitude limiting accumulator is used for integrating and limiting the system frequency error to obtain a system phase error.
In one embodiment, the frequency tuning module comprises: a digital loop filter and a digital controlled oscillator which are connected in sequence; the digital loop filter receives the system phase error, and generates an integer digital frequency tuning word and a decimal digital frequency tuning word after filtering the system phase error; and the numerically controlled oscillator tunes the output frequency of the output end signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word to complete locking.
Under the condition that the function and performance of the frequency-locked loop type full digital frequency synthesizer are same as those of the traditional phase-locked loop type full digital frequency synthesizer, the frequency-locked loop type full digital frequency synthesizer replaces continuous phase accumulators (VPA and RPA) in the phase-locked loop type full digital frequency synthesizer by using a variable frequency counter with an accumulation and zero clearing function, so that the asynchronous overflow condition of the VPA and the RPA in the phase-locked loop type full digital frequency synthesizer can be completely avoided, the generation of pulse fluctuation in the locking process of the phase-locked loop type full digital frequency synthesizer is completely eradicated, the stability of loop locking is improved, and the frequency-locked loop type full digital frequency synthesizer has higher reliability.
Drawings
FIG. 1 is a schematic block diagram of an embodiment of a frequency-locked loop type full digital frequency synthesizer;
FIG. 2 is a schematic diagram of the operation of a time-to-digital converter in one embodiment;
FIG. 3 is a schematic diagram of a variable frequency counter according to an embodiment;
FIG. 4 is a diagram illustrating an embodiment of a true unidirectional clock D flip-flop with a trigger reset function;
FIG. 5 is a schematic diagram of another embodiment of a frequency-locked loop type full-digital frequency synthesizer;
FIG. 6 is a simulation of the counting result and the frequency error of the variable frequency counter in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, a schematic block diagram of a frequency-locked loop type full digital frequency synthesizer is provided, as shown in fig. 1, the frequency-locked loop type full digital frequency synthesizer includes three modules, namely a frequency discriminator module 100, a frequency integration module 200, and a frequency tuning module 300, the frequency discriminator module 100, the frequency integration module 200, and the frequency tuning module 300 are connected in sequence, and an output signal at an output of the frequency tuning module 300 is fed back to the frequency discriminator module 100.
Specifically, the frequency discriminator module 100 mainly includes a variable frequency counter 110 and a time-to-digital converter 120, where the variable frequency counter 110 is connected to the output end of the frequency tuning module 300, and counts the output frequency of the output end signal, and compares the output frequency with the frequency control word to obtain the integer frequency error.
The time-to-digital converter 120 is configured to calibrate time amounts of the input reference frequency signal at the current time and the input reference frequency signal at the previous time before the output end signal at the rising edge of the system synchronization signal, and normalize a period of the output end signal according to a difference between the time amounts to obtain a fractional frequency error.
It should be noted that, compared to the time-to-digital converter of the conventional phase-locked loop type full-digital frequency synthesizer, the time-to-digital converter 120 adds a differential function (the digital domain is differential), and the operation and structure thereof are shown in fig. 2.
The discriminator module 100 is further configured to add the integer frequency error and the fractional frequency error to obtain a system frequency error.
The frequency integration module 200 is configured to receive the system frequency error, and accumulate the system frequency error to obtain a system phase error.
The frequency tuning module 300 is configured to receive the system phase error, process the system phase error, obtain an output end signal, and output the output end signal.
In this embodiment, the frequency tuning is performed on the output end signal to complete the locking, so that all the functions of the frequency-locked loop type full digital frequency synthesizer are completed.
Under the condition that the function and performance of the frequency-locked loop type full-digital frequency synthesizer are the same as those of the traditional frequency-locked loop type full-digital frequency synthesizer, the frequency-locked loop type full-digital frequency synthesizer replaces continuous phase accumulators (VPA and RPA) in the frequency-locked loop type full-digital frequency synthesizer by using a variable frequency counter with an accumulation and zero clearing function, so that the asynchronous overflow condition of the VPA and the RPA in the frequency-locked loop type full-digital frequency synthesizer can be completely avoided, the generation of pulse fluctuation in the locking process of the frequency-locked loop type full-digital frequency synthesizer is completely eradicated, the stability of loop locking is increased, and the frequency-locked loop type full-digital frequency synthesizer has higher reliability.
It should be noted that the detection of the phase error of the system by the phase-locked loop type full digital frequency synthesizer is mainly realized by integrating the frequency, and the frequency-locked loop can be equivalent to that the integration of the frequency is differentiated first and then integrated, and is equivalent in a frequency domain model, so that the phase-locked loop type full digital frequency synthesizer and the phase-locked loop type full digital frequency synthesizer have the same function and performance.
In one embodiment, the variable frequency counter comprises: m-stage pre-frequency dividers and serial carry binary counters;
the m-stage prepositive frequency divider reduces the frequency of the output end signal by 2 m Multiplying and providing a counting result of high bits; and the serial carry binary counter accumulates the output frequency signals of the m-stage pre-frequency dividers and provides a counting result of a low bit.
Specifically, as shown in fig. 3, the variable frequency counter is an n-bit counter, the output signal is represented by CKV, and the frequency of the output signal is reduced by 2 m The speed requirement on a subsequent serial carry binary counter is greatly relieved, the serial carry binary counter performs 1 adding operation once every time a divided clock arrives, and the final counting output is Out [0 n-1]。
In one embodiment, the internal flip-flops of the variable frequency counter are true one-way clock architecture flip-flops.
In another embodiment, to handle higher frequencies, a true unidirectional clock architecture flip-flop may be implemented with a current mode logic architecture.
In a specific embodiment, the true unidirectional clock structure flip-flop is a true unidirectional clock D flip-flop with a trigger reset function, and the true unidirectional clock D flip-flop further includes: the output end signal of the inverter and the signal output by the output end of the inverter are subjected to AND operation in the AND gate to generate a high-level reset pulse, and the high-level reset pulse is used for resetting the true unidirectional clock D trigger.
Specifically, as shown in fig. 4, a schematic block diagram of a reset true unidirectional clock D flip-flop is provided, in which an inverter and an and gate are combined to generate an RST reset signal for resetting the true unidirectional clock D flip-flop. As can be seen from the figure, when the next rising edge of the CKV clock signal arrives, the counting is restarted, and the frequency detection function for the output end signal is completed.
In another embodiment, the delay time of the inverter is adjustable and can be determined according to specific simulation results.
In one embodiment, the discriminator module further comprises: a retiming unit for generating a system synchronization signal having a frequency identical to an input reference frequency signal according to the output terminal signal and the input reference frequency signal.
In one embodiment, the frequency integration module comprises: a clipping accumulator. And the amplitude limiting accumulator is used for integrating the system frequency error and avoiding the overturning of the accumulator through amplitude limiting to obtain the system phase error.
In one embodiment, the frequency tuning module comprises: the digital loop filter receives a system phase error, and generates an integer digital frequency tuning word and a decimal digital frequency tuning word after filtering the system phase error; and the numerical control oscillator tunes the output frequency of the output end signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word to complete locking.
In one embodiment, as shown in FIG. 5, a schematic block diagram of a specific frequency-locked loop type full digital frequency synthesizer is provided, wherein TDC represents a time-to-digital converter, DFF represents a D-type flip-flop, and retiming f ref Representing a retiming unit, DLF a digital loop filter, where the input parameters alpha and beta represent the proportional and integral coefficients of a proportional-integral filter, respectively, lambda i I =1, 2.. The.. N denotes the filter coefficients of an infinite impulse response filter, f ref Representing an input reference frequency signal, CKV an output signal, CKR a system synchronization signal, T v Indicating the period of the output signal, FCW (N) indicating a frequency control word with a division ratio N, R v [k]Represents the counting result of the variable frequency counter at the rising edge of the kth system synchronous clock, epsilon [ k ]]Indicating fractional frequency error, R, at the time of the rising edge of the kth system synchronous clock e [k]Indicating the system frequency error at the kth system synchronous clock rising edge moment, OTW _ I indicating an integer digital frequency tuning word, OTW _ F indicating a fractional digital frequency tuning word, the DCO output, i.e. the output terminal signal, which is consistent with CKV.
In this embodiment, the bit setting of the variable frequency counter only needs to cover the maximum frequency dividing ratio, which has lower bit number compared to VPA, and meanwhile, the fuzzy compensation unit in the phase-locked loop type full digital frequency synthesizer is replaced by the amplitude limiting function, so that the design complexity is lower. The integrating module in the proportional-integral filter is also implemented by a limiting accumulator with the same function as that in the frequency integrating module to avoid the value inversion during the locking process.
In the locking process of the frequency-locked loop type all-digital frequency synthesizer shown in fig. 5, the counting result of the variable frequency counter and the simulation result of the frequency error are shown in fig. 6, wherein the set loop bandwidth is 250khz, the difference between the dco initial frequency and the expected output frequency is 2GHz, and the frequency control word is 192.3077.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A frequency-locked loop type all-digital frequency synthesizer, comprising:
the device comprises a frequency discriminator module, a frequency integration module and a frequency tuning module;
the frequency discriminator module, the frequency integration module and the frequency tuning module are sequentially connected, and an output end signal of an output end of the frequency tuning module is fed back to the frequency discriminator module;
the frequency discriminator module comprises:
the variable frequency counter is connected with the output end of the frequency tuning module, counts the output frequency of the output end signal and compares the output frequency with a frequency control word to obtain an integer frequency error;
the time-to-digital converter is used for respectively calibrating the time quantum of the input reference frequency signal at the current moment and the time quantum of the input reference frequency signal at the last moment, which leads the output end signal at the rising edge moment of the system synchronizing signal, and normalizing the period of the output end signal according to the difference value of the time quantum to obtain a fractional frequency error;
the frequency discriminator module is also used for adding the integer frequency error and the decimal frequency error to obtain a system frequency error;
the frequency integration module is used for receiving the system frequency error, accumulating the system frequency error and limiting amplitude to obtain a system phase error;
and the frequency tuning module is used for receiving the system phase error, processing the system phase error, obtaining and outputting an output end signal.
2. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the variable frequency counter comprises: m-stage pre-frequency dividers and serial carry binary counters;
the m-stage prescaler reduces the frequency of the output end signal by 2 m Multiplying and providing a counting result of high bits; and the serial carry binary counter accumulates the output frequency signals of the m-stage pre-frequency dividers and provides a counting result of a low bit.
3. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the internal flip-flop of the variable frequency counter is a true one-way clock structure flip-flop.
4. The frequency-locked loop type all-digital frequency synthesizer according to claim 1, wherein the internal flip-flop of the variable frequency counter is implemented using a current-mode logic structure.
5. The frequency-locked loop type all-digital frequency synthesizer according to claim 3, wherein the true one-way clock structure flip-flop is a true one-way clock D flip-flop with a trigger reset function;
the true unidirectional clock D flip-flop further comprises: the output end signal of the inverter is input into the inverter to carry out inversion and delay operation, and the output end of the inverter is connected with the input end of the AND gate;
and the output end signal and the signal output by the output end of the phase inverter are subjected to AND operation in the AND gate to generate a high-level reset pulse, and the high-level reset pulse is used for resetting the true unidirectional clock D trigger.
6. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the discriminator module further comprises:
a retiming unit to generate the system synchronization signal in frequency correspondence with the input reference frequency signal from the output end signal and the input reference frequency signal.
7. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the frequency integration module comprises:
and the amplitude limiting accumulator is used for integrating and limiting the system frequency error to obtain a system phase error.
8. The frequency-locked loop type all-digital frequency synthesizer according to any one of claims 1 to 4, wherein the frequency tuning module comprises:
a digital loop filter and a digital controlled oscillator which are connected in sequence;
the digital loop filter receives the system phase error, and generates an integer digital frequency tuning word and a decimal digital frequency tuning word after filtering the system phase error;
and the numerically controlled oscillator tunes the output frequency of the output end signal according to the integer digital frequency tuning word and the decimal digital frequency tuning word to complete locking.
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|---|---|---|---|---|
| US4580107A (en) * | 1984-06-06 | 1986-04-01 | The United States Of America As Represented By The Secretary Of The Air Force | Phase lock acquisition system having FLL for coarse tuning and PLL for fine tuning |
| CN1388649A (en) * | 2002-07-22 | 2003-01-01 | 清华大学 | Phase-locked loop frequency synthesizer with digital coarse tuning loop |
| CN101640533A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Rapid locking method for full digital phase-locked loop |
| WO2017211060A1 (en) * | 2016-06-08 | 2017-12-14 | 江苏现代电力科技股份有限公司 | High-precision phase locking method for intelligent integrated low-pressure reactive power module |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4580107A (en) * | 1984-06-06 | 1986-04-01 | The United States Of America As Represented By The Secretary Of The Air Force | Phase lock acquisition system having FLL for coarse tuning and PLL for fine tuning |
| CN1388649A (en) * | 2002-07-22 | 2003-01-01 | 清华大学 | Phase-locked loop frequency synthesizer with digital coarse tuning loop |
| CN101640533A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Rapid locking method for full digital phase-locked loop |
| WO2017211060A1 (en) * | 2016-06-08 | 2017-12-14 | 江苏现代电力科技股份有限公司 | High-precision phase locking method for intelligent integrated low-pressure reactive power module |
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