WO2017211060A1

WO2017211060A1 - High-precision phase locking method for intelligent integrated low-pressure reactive power module

Info

Publication number: WO2017211060A1
Application number: PCT/CN2016/109927
Authority: WO
Inventors: 夏武; 王新明; 王宗臣; 冯国伟; 杨建�; 夏文
Original assignee: 江苏现代电力科技股份有限公司
Priority date: 2016-06-08
Filing date: 2016-12-14
Publication date: 2017-12-14
Also published as: CN106055000A; CN106055000B

Abstract

Disclosed is a high-precision phase locking method for an intelligent integrated low-pressure reactive power module, the method comprising a multiplicative phase discrimination link (1), a variable frequency period integration link (2), a variable parameter integration separation speed change PI regulation link (3), an angular frequency integration link (4), a frequency estimation link (5), remainder (6), sine (7) and cosine (8). An improved PI regulator uses a variable parameter integration separation speed change PI regulator for regulation, so that the phase locking precision is improved and the static deviation is eliminated under the premise that the rapidity of phase locking can be ensured. An improved loop filter can eliminate the influence of harmonic wave and frequency changes on the output precision of a phase-locked loop when in a steady state.

Description

Intelligent integrated low voltage reactive module high precision phase locking method

Technical field

The invention relates to a phase locking method, in particular to an intelligent integrated low voltage reactive module high precision phase locking method.

Background technique

In the field of low-voltage power distribution, regardless of instrumentation or reactive compensation module, synchronous grid phase is required for accurate calculation and control to achieve compensation and optimization. Unbalanced and impact industrial electrical equipment such as rolling mills and intermediate frequency furnaces are increasing, resulting in many power quality problems such as low power factor, voltage fluctuation and flicker, and three-phase voltage and current imbalance. Therefore, when reactive power compensation is applied to such an impact load, instantaneous reactive power is needed for fast compensation, and the key to calculating instantaneous reactive power is the calculation of the synchronous phase-locked loop of the power grid.

At present, the common phase-locking technologies are divided into the following types. One is through the hardware-based zero-crossing comparison technique, using the zero-crossing comparison method, the grid voltage signal is used to isolate the analog signal, and the isolated voltage signal is filtered through low-pass filtering. Except for higher harmonic voltage components. This method may cause multiple levels of jitter in the vicinity of the voltage zero point in the case of severe harmonic distortion of the grid voltage, which will invalidate the synchronization. The second method: the fundamental wave Fourier transform calculates the phase method, which can only be used in the case of fixed frequency, and the calculation amount is large. The third type: phase-locking technology based on dq algorithm, this method can be divided into three-phase and single-phase phase-locked, three-phase phase lock is only suitable for voltage balance and voltage distortion is not serious, sensitive to grid voltage, phase-locked error Big; single phase needs to be born It is a quadrature signal, one adopts the hysteresis 90° mode, and the other adopts the generalized integration method. The former cannot achieve the accurate lag of 90° due to the fluctuation of the grid frequency, and the frequency tracking is inaccurate, resulting in phase-locked failure. Sensitive, due to frequency fluctuations and harmonics, the quadrature signal obtained by the generalized integration method will contain harmonic components, resulting in phase-locked distortion.

The traditional loop filter is composed directly of the PI regulator. This loop filter has poor steady-state accuracy and cannot completely eliminate the influence of harmonics and frequency changes on the output precision of the phase-locked loop. Because of the traditional phase-locked loop PI regulator If the adjustment coefficient is too large, the phase locking speed is fast, but the output fluctuation is large, and the result is not accurate. If the selection is small, although the fluctuation will reduce the fluctuation, the phase locking speed is greatly reduced.

Summary of the invention

The technical problem to be solved by the invention is to provide an intelligent integrated low-voltage reactive module high-precision phase-locking method, which has simple program realization, fast calculation speed, fast tracking speed and improved synchronization precision of the phase-locked loop.

In order to solve the above technical problems, the technical solution adopted by the present invention is:

A high-precision phase-locking method for intelligent integrated low-voltage reactive module, which comprises: multi-phase phase-detecting link, variable frequency cycle integral link, variable parameter integral separation and shifting PI adjustment link, angular frequency integral link, frequency estimation link, and remainder , sine and cosine;

The multi-phase phase-detection link is used as the phase detector of the phase-locking technology. The input signal is the cosine of the digital voltage of the grid and the phase of the phase-locked output after the analog-to-digital conversion. The variable frequency period integral link and the variable parameter integral separation speed PI adjustment link are improved. The loop filter, the input signal of the variable frequency period integral link is the output of the multiplication phase detection link and the output of the frequency estimation link. The output of the frequency cycle integral link is sent to the variable parameter integral separation speed shift PI adjustment link; the output of the variable parameter integral separation speed shift PI adjustment link is respectively sent into the angular frequency integral link and the frequency estimation link to calculate the phase and frequency of the grid voltage; the angular frequency The cosine value of the output of the integral link is fed back to the phase detector for closed loop control;

The frequency estimation link is composed of a frequency change rate limiter and a low-pass filter. The input of the frequency change rate limiter is the output of the integral-separated variable-speed PI adjustment link, and the frequency and the angular frequency are converted to have a fluctuating frequency, and are sent to Low-pass filter; the output of the low-pass filter is an estimated value of the grid frequency, and is sent back to the variable frequency period integral link for closed-loop control;

The input signal of the remainder is the output of the angular frequency integral link. After the remainder operation, the synchronous phase angle of the grid is output, and the phase angle is ensured to be between [0, 2π], so as to avoid the numerical overflow error caused by the integral operation; the sinusoidal input signal is The grid synchronous phase angle of the output is output, and the fundamental frequency synchronization value of the output grid is output; the input signal of the cosine is the synchronous phase angle of the grid of the surplus output, and the standard value of the fundamental wave lag of 90° is output as the indirect feedback amount of the phase. , to achieve phase closed loop control.

Further, the variable frequency period integral link is composed of a periodic sliding window integral link and an integral error correction link.

Further, the cycle sliding window integral link determines the value of the sliding window according to the feedback grid frequency, calculates the integral sliding window integral amount, and multiplies the integral amount by the feedback frequency to obtain an integer partial variable frequency period. Integral link output R ₁ ,

Where: Fre is the grid feedback frequency, N _cur represents the latest sampling data point, N _int is a periodic sampling integer point, and U _i is the output of the i-th moment of the phase-detection link.

For the accumulated value of the previous sample point,

The latest phase-detection link output,

Phase detection link output before a cycle.

Further, the integral error correction link determines the integer point of one cycle and the number of error points due to rounding according to the grid frequency returned by the feedback, and the sampling time interval, and then estimates the error moment according to the error point number and the integral definition. The phase-detected output value is then estimated based on the above estimated value, and the integral error of the current moment caused by the error point is estimated. Finally, the integral error of the current time is multiplied by the feedback frequency to obtain the integral error correction link output R ₂ .

Further, the error time phase detection output value estimation uses three-point quasi-linear interpolation principle for interpolation estimation, and the arbitrary phase time k is set, and the obtained phase-detection link output is U _k , and the phase-detection link output obtained at the k-1 time is U _k-1 , the output of the phase _- detection link obtained at time k-2 is U _k-2 , then the output of the phase _- detection link corresponding to k + ΔNT _s is estimated to be U _{k + ΔN} , which is obtained by the three-point quasi-linear interpolation principle. U _k+ΔN is U _k+ΔN =U _k +[a×(U _k -U _k-1 )+(1-a)×(U _k-1 -U _k-2 )]×(N _float -N _Int ), where a takes any decimal of [0,1].

Further, the integral error correction link output quantity R _{2 is} error-corrected according to the discrete integral definition, the error time phase detector output value estimation and the frequency feedback link feedback frequency, and the specific implementation form thereof:

Further, the variable parameter integral separation shift PI adjustment link includes a variable parameter portion and an integral separation shift portion.

Further, the variable parameter portion passes the absolute value of the voltage peak in the previous period of the current time as the basis for changing k _p , k _i , and plays the role of removing harmonics on the phase locking accuracy. Its parameters k _p , k _i concrete realization form:

Where ε is the damping coefficient, Δf is the allowable tracking frequency range, and U _max is the absolute value of the voltage peak in the previous period of the current time.

Further, the integral separation shifting portion superimposes the output of the cycle sliding window integral link and the integral error correction link as the error input e(k)=R ₁ (k)+R ₂ (k) of the PI adjustment, and constructs an integral. Separate the shifting function f[e(k)],

Among them, β ≤ α, Ι section shift threshold α, ΙΙ section shift threshold β, to ensure that the error is larger, so that the integral is slower, avoiding the system stability caused by integral, high overshoot, when the error is small, make the integral faster, make full use of The advantage of high steady-state accuracy.

Further, the variable parameter integral separates the output grid synchronization angular frequency ω(k) of the variable speed PI adjustment link, the integral link output is ω _i , and the proportional link output is ω _p , then ω _p (k)=k _p ×e(k),

ω(k)=ω _p (k)+f[e(k)]×k _i ×ω _i (k), and finally limit output the output angular frequency so that the output angular frequency is limited to the central angular frequency of the normal power grid. Near ω ₀ , ensure that the output angular frequency is limited between [ω ₀ -2πΔf, ω ₀ +2πΔf].

Compared with the prior art, the present invention has the following advantages and effects:

1, using single-phase phase-locking technology, suitable for single-phase, three-phase systems, especially three-phase unbalanced systems;

2, using phase frequency double feedback technology, can be programmed once, adapt to foreign 60Hz grid;

3, the cycle sliding window integral link, to avoid repeated operations, only one addition and one subtraction operation in each cycle, the program is simple to implement, the operation speed is fast;

4. Introducing the variable frequency period integral error correction link, which solves the cumulative error between the sampling points and the influence of the truncation error on the phase-locked loop in the numerical analysis, and improves the synchronization precision of the phase-locked loop;

5. The improved PI regulator adopts the variable parameter integral separation variable speed PI regulator for adjustment, which can ensure the phase locking accuracy and eliminate the static difference under the premise of fast phase locking;

6. The improved loop filter can eliminate the influence of harmonics and frequency changes on the output precision of the phase-locked loop in steady state;

7. This phase-locked loop is fully software-implemented and has strong anti-interference ability.

DRAWINGS

1 is a frame diagram of a high precision phase locking method for an intelligent integrated low voltage reactive module of the present invention.

2 is a schematic diagram of the variable frequency cycle integration link of the present invention.

Figure 3 is a schematic diagram of the integral sliding window integration link of the present invention.

4 is a schematic diagram of the phase-detection link output U _k+ΔN corresponding to the time point of estimating the k+ΔNT _s at the three-point quasi-linear interpolation principle of the present invention.

Figure 5 is a schematic diagram of the integral error correction link of the present invention.

Figure 6 is a schematic diagram of the third-order integral of the angular frequency integral link of the present invention.

Figure 7 is a schematic diagram of the frequency estimation link of the present invention.

Figure 8 is a diagram showing the grid voltage waveform of the present invention.

9 is a comparison diagram of the actual grid voltage fundamental value and the phase-locked tracking value of the present invention.

Figure 10 is a diagram of the grid voltage frequency response of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings.

As shown in the figure, the intelligent integrated low-voltage reactive module high-precision phase-locking method of the invention comprises a multi-phase phase-detecting link, a variable frequency cycle integral link, a variable-parameter integral-separating variable-speed PI adjustment link 3, and an angular frequency integral link. 4. Frequency estimation link 5, remainder 6, sine 7 and cosine 8.

The multi-phase phase-detection link is used as the phase detector of the phase-locking technology. The input signal is the cosine of the digital voltage of the grid and the phase of the phase-locked output after the analog-to-digital conversion. The variable frequency period integral link and the variable parameter integral separation speed PI adjustment link are improved. The loop filter, the input signal of the variable frequency period integral link is the output of the multiplication phase detection link and the output of the frequency estimation link, and the output of the variable frequency period integral link is sent to the variable parameter integral separation shift PI adjustment link; the variable parameter integral separation shifting The output of the PI regulation link is sent to the angular frequency integral link and the frequency estimation link to calculate the phase and frequency of the grid voltage; the cosine of the output of the angular frequency integral link is fed back to the phase detector for closed-loop control.

The multiplication phase-detection link converts the modulus of the grid and the phase-locked output angle The chord value is multiplied to obtain the phase-detection value U of the fluctuation of the power grid, and is sent to the variable frequency cycle integral link.

The frequency estimation link is composed of a frequency change rate limiter and a low-pass filter. The input of the frequency change rate limiter is the output of the integral-separated variable-speed PI adjustment link, and the frequency and the angular frequency are converted to have a fluctuating frequency, and are sent to The low-pass filter; the output of the low-pass filter is an estimate of the grid frequency and is sent back to the variable frequency period integral link for closed-loop control.

The input signal of the remainder is the output of the angular frequency integral link. After the remainder operation, the synchronous phase angle of the grid is output, and the phase angle is ensured to be between [0, 2π], so as to avoid the numerical overflow error caused by the integral operation; the sinusoidal input signal is The grid synchronous phase angle of the output is output, and the fundamental frequency synchronization value of the output grid is output; the input signal of the cosine is the synchronous phase angle of the grid of the surplus output, and the standard value of the fundamental wave lag of 90° is output as the indirect feedback amount of the phase. , to achieve phase closed loop control. After the above processing, the phase, frequency and grid synchronous sine of the grid voltage are accurately locked out.

In the multiplication phase-detecting step, the cosine value of the grid voltage signal and the phase-locked output angle are multiplied by the modulus conversion, and the phase-detection value U of the grid fluctuation is obtained, and is sent to the variable frequency period integral link.

The step of the variable frequency cycle integration step is further divided into two major steps, a step of the cycle sliding window integration step, and an integral error correction step.

The step of the integral sliding window integration step determines the value of the sliding window based on the feedback grid frequency, calculates the integral amount of the periodic sliding window, and multiplies the integral amount by the feedback frequency to obtain an integer partial variable frequency period integral link output quantity R ₁ The embodiment is shown in Figure 3.

Where: Fre is the grid feedback frequency; N _cur represents the latest sampling data point; N _int is a periodic sampling integer point, U _i is the output of the i-th moment of the phase-detection link,

For the accumulated value of the previous sample point,

The latest phase-detection link output,

Phase detection link output before a cycle.

In the integral error correction step, according to the grid frequency returned by the feedback, and the sampling time interval, the whole point of one cycle and the number of error points due to rounding are determined; and according to the error point and the integral definition, the phase-detecting output corresponding to the error moment is estimated. Then, according to the above estimated value, the integral error of the current moment caused by the error point is estimated; finally, the integral error of the current time is multiplied by the feedback frequency to obtain the integral error correction link output R ₂ .

The whole point of the cycle and the number of error points are determined. If the sampling period is Ts, then one grid period is converted into the number of sampling points with a decimal number N _float , and the corresponding number of points is N _int ;

Since the grid frequency is not a fixed value, the national standard limits the allowable fluctuation level of the grid frequency as follows: frequency class A level ≤ ± 0.05 Hz; class B ≤ ± 0.5 Hz; C level ≤ ± 1 Hz. Explain that the grid frequency is a time variable. Therefore, N _{float is} not a fixed value, and there is a fractional error between the number of points after the period is converted into the number of samples. Therefore, the discrete integral needs to take into account this part of the error. Let the number of error points be ΔN=N _float -N _int .

The error time phase detector output value estimation link uses three-point quasi-linear interpolation principle for interpolation estimation. According to the three-point quasi-linear interpolation principle, the phase-detection link output U _k+ΔN corresponding to the time k + ΔNT _{s is} estimated, and the arbitrary phase _k is set. The obtained phase-detection link output is U _k , and the phase obtained at time k-1 is obtained. The output of the link is U _k-1 , and the output of the phase _- detection link obtained at time k-2 is U _k-2 , then the output phase corresponding to the k + ΔNT _s is output U _{k + ΔN} , using three-point quasi-linear The interpolation principle yields U _{k + ΔN} as U _{k + ΔN} = U _k + [a × (U _k - U _k-1 ) + (1 - a) × (U _k-1 - U _k-2 )] × (N _Float -N _int ), where a takes any fraction of [0, 1]. The specific implementation is shown in Figure 4. In this example, a = 0.75 can be selected.

The integral error correction link output is

The specific embodiment is shown in FIG.

The variable parameter integral separation shift PI adjustment step consists of a variable parameter step and an integral separation shift step.

The variable parameter step passes the absolute value of the voltage peak in the previous period of the current time as the basis for changing k _p , k _i , and plays the role of removing harmonics on the phase locking accuracy. Its parameters k _p , k _i concrete realization form:

The integral separation and shifting step superimposes the output of the cycle sliding window integral link and the integral error correction link as the error input e(k)=R ₁ (k)+R ₂ (k) of the PI adjustment, and constructs the integral separation shift function f[ e(k)], to ensure that the error is larger, the integration is slower, avoiding the integral to cause poor system stability, overshooting, and when the error is small, the integration is faster, making full use of the advantage of high stability of the integral.

The expression of the integral separation shifting function f[e(k)] is as follows:

Where β ≤ α, the 变速 section shift threshold α, the 变速 section shift threshold β.

The variable parameter integral separates the output grid synchronization angular frequency ω(k) of the variable speed PI regulator, the integral link output is ω _i , and the proportional link output is ω _p . Then ω _p (k)=k _p ×e(k),

In the angular frequency integration step, the variable angle integral frequency of the variable parameter integral separation variable speed PI adjustment link is discretely integrated, and the phase angle synchronized with the power grid is obtained. Discrete integrals use a third-order integration method.

The specific embodiment is shown in FIG. 6.

In the frequency estimation step, the variable parameter integral is separated and the limited amplitude frequency outputted by the variable speed PI adjustment link is frequency-converted, and the frequency change rate is limited after the conversion, and finally the estimated frequency of the power grid is obtained through low-pass filter filtering. This estimated frequency is used as the basis for the variable frequency cycle integral link and the calculation of the number of sampling points in a grid cycle. The specific implementation is shown in FIG. 7 .

The frequency change rate limiter functions to limit the angular frequency output overshoot of the variable parameter integral separation speed PI adjustment link output, and plays the role of improving the transient stability of the frequency estimation output.

The low pass filter uses a second order low pass filter with the following expression:

Where ω _c is the cutoff angle frequency of the low-pass filter, and ξ is the damping coefficient. Since the angular frequency output by the PI adjustment link does not have harmonics in the grid, it contains secondary fluctuations, and when there is a large harmonic in the power grid, it contains 2n fluctuations, so ω _c can be taken as 80π when the choice ω _c should be less than 2 times the minimum angular frequency of the input grid voltage.

The technical problem to be solved by the invention is that the existing phase-locked technology has a large static error in the phase-locked loop output under the condition of severe harmonics or frequency fluctuation, and a frequency-phase double feedback single-phase high-precision phase-locking technique is proposed. Improve the loop filter of the phase-locked loop. The conventional loop filter is directly composed of a PI regulator. The loop filter has poor steady-state accuracy and cannot completely eliminate the influence of harmonics and frequency changes on the output precision of the phase-locked loop. Therefore, the present invention improves the conventional phase-locked phase. The loop filter, the filter loop composed of the variable frequency period integral link and the variable parameter integral separation variable speed PI adjustment link, the variable frequency period integral link is composed of the cycle sliding window integral link and the integral error correction link, and the cycle The sliding window integral link avoids repeated operations. There is only one addition and one subtraction operation in each cycle. The program is simple to implement, the operation speed is fast, and the tracking speed is fast. The variable frequency period integral error correction link is introduced to solve the accumulation between the sampling points. The influence of the truncation error on the phase-locked loop in error and numerical analysis further improves the synchronization accuracy of the phase-locked loop. Due to the traditional phase-locked loop PI regulator, if the adjustment factor is too large, the phase-locking speed is fast, but the output fluctuation is large, and the result is not accurate. If the selection is small, although the fluctuation will reduce the fluctuation, the phase-locking speed is greatly reduced. Therefore, the present invention proposes to adopt a variable parameter integral separation variable speed PI adjustment link for adjustment, which can ensure the phase locking accuracy and eliminate the static difference under the premise of fast phase locking. Improved loop filter eliminates harmonics and frequency changes in steady state for phase-locked loops The effect of the output accuracy.

The simulation is verified by the implementation steps of the present invention. The sampling period is Ts=0.0001s, the grid frequency is 50Hz before 0.5s, and only the fundamental voltage, no harmonic voltage, and the grid voltage is U _sa =311sin (100πt+ π/8); change the grid frequency to 51Hz at 0.5s, and increase the 5% of the 3rd generation grid harmonics, the phase leads the fundamental wave π/8, 10% of the 5th harmonic, the phase leads the fundamental wave 5π/24, Grid voltage is

U _sa =311sin[102π(t-0.5)+π/8]+15.5sin[306π(t-0.5)+π/4]+31.1sin[510π(t-0.5)+π/3] Figure 8 shows.

After the implementation of the invention, as shown in FIG. 9, the solid line is the actual fundamental wave value of the power grid, and the broken line is the base wave standard value of the power grid tracked by the invention. It can be seen that at 0.56 s, the fundamental voltage component of the system grid voltage is completely tracked. And adding harmonics after 0.5s does not affect the phase-locked loop. As shown in Fig. 10, the grid voltage tracking frequency overshoot is small, less than 0.03 Hz, and the tracking frequency of the grid meets the "General Requirements for Power Quality Monitoring Equipment of GB 19862-2005" at 0.66 s, and the deviation of the grid frequency is less than 0.01 Hz, and The stable value is 0.7s, the steady-state error is less than 0.001Hz, and the final steady-state error can reach 10 ^-5 .

The above description in this specification is merely illustrative of the invention. A person skilled in the art can make various modifications or additions to the specific embodiments described or replace them in a similar manner, as long as they do not deviate from the scope of the present specification or beyond the scope defined by the claims. It belongs to the scope of protection of the present invention.

Claims

A high-precision phase-locking method for intelligent integrated low-voltage reactive module, which comprises: multi-phase phase-detecting link, variable frequency cycle integral link, variable parameter integral separation and shifting PI adjustment link, angular frequency integral link, frequency estimation link, and remainder , sine and cosine;

The multi-phase phase-detection link is used as the phase detector of the phase-locking technology. The input signal is the cosine of the digital voltage of the grid and the phase of the phase-locked output after the analog-to-digital conversion. The variable frequency period integral link and the variable parameter integral separation speed PI adjustment link are improved. The loop filter, the input signal of the variable frequency period integral link is the output of the multiplication phase detection link and the output of the frequency estimation link, and the output of the variable frequency period integral link is sent to the variable parameter integral separation shift PI adjustment link; the variable parameter integral separation shifting The output of the PI adjustment link is sent to the angular frequency integral link and the frequency estimation link to calculate the phase and frequency of the grid voltage; the cosine of the output of the angular frequency integral link is fed back to the phase detector for closed-loop control;

The frequency estimation link is composed of a frequency change rate limiter and a low-pass filter. The input of the frequency change rate limiter is the output of the integral-separated variable-speed PI adjustment link, and the frequency and the angular frequency are converted to have a fluctuating frequency, and are sent to Low-pass filter; the output of the low-pass filter is an estimated value of the grid frequency, and is sent back to the variable frequency period integral link for closed-loop control;

The input signal of the remainder is the output of the angular frequency integral link. After the remainder operation, the synchronous phase angle of the grid is output, and the phase angle is ensured to be between [0, 2π], so as to avoid the numerical overflow error caused by the integral operation; the sinusoidal input signal is The grid synchronous phase angle of the output is output, and the fundamental frequency synchronization value of the output grid is output; the input signal of the cosine is the synchronous phase angle of the grid of the surplus output, and the standard value of the fundamental wave lag of 90° is output as the indirect feedback amount of the phase. , to achieve phase closed loop control.
The intelligent integrated low voltage reactive module high precision phase locking method according to claim 1 The method is characterized in that: the variable frequency period integral link is composed of a periodic sliding window integral link and an integral error correction link.
The high-precision phase-locking method for intelligent integrated low-voltage reactive power module according to claim 2, wherein the integral sliding window integral link determines the value of the sliding window according to the feedback grid frequency, and calculates the cycle slip of the integer part. The amount of window integral, and then multiplying the integral amount by the feedback frequency to obtain an integer partial variable frequency period integral link output quantity R 1 ,

Where: Fre is the grid feedback frequency, N cur represents the latest sampling data point, N int is a periodic sampling integer point, U i is the output of the i-th moment of the phase-detection link,
For the accumulated value of the previous sample point,
The latest phase-detection link output,
Phase detection link output before a cycle.
The high-precision phase-locking method for intelligent integrated low-voltage reactive power module according to claim 2, wherein the integral error correction link determines the whole-point number of one cycle and the corresponding point according to the grid frequency returned by the feedback and the sampling time interval. According to the error point number and the integral definition, the phase-detected output value corresponding to the error time is estimated, and then the integral error of the current moment caused by the error point is estimated according to the above-mentioned estimated value, and finally the integral of the current time is obtained. The error is multiplied by the feedback frequency to obtain an integral error correction link output R 2 .
The high-precision phase-locking method for intelligent integrated low-voltage reactive power module according to claim 4 is characterized in that: the error time phase-detecting output value is estimated by using a three-point quasi-linear interpolation principle for interpolation estimation, and the obtained time is obtained. The output of the phase link is U k , and the output of the phase - detection link obtained at k-1 is U k-1 , and the output of the phase - detection link obtained at time k-2 is U k-2 , which is estimated at k + ΔNT s . The phase-correlation link output of the time corresponds to U k+ΔN , and the three-point quasi-linear interpolation principle is used to obtain U k+ΔN as U k+ΔN =U k +[a×(U k -U k-1 )+(1-a ×(U k-1 -U k-2 )]×(N float -N int ), where a takes any fraction of [0,1].
The intelligent integrated low-voltage reactive module high-precision phase-locking method according to claim 4, wherein the integral error correction link output R 2 is defined according to discrete integral, the error time phase detector output value estimation and the frequency estimation link The frequency of feedback is error corrected, and its specific implementation form:
The intelligent integrated low-voltage reactive module high-precision phase-locking method according to claim 1, wherein the variable parameter integral separating and shifting PI adjusting link comprises a variable parameter portion and an integral separating shifting portion.
The intelligent integrated low-voltage reactive module high-precision phase-locking method according to claim 7, wherein the variable parameter portion passes the absolute value of the voltage peak in the previous period of the current time as the basis for changing k p , k i To eliminate the influence of harmonics on the accuracy of phase lock. Its parameters k p , k i concrete realization form:
Where ε is the damping coefficient, Δf is the allowable tracking frequency range, and U max is the absolute value of the voltage peak in the previous period of the current time.
The intelligent integrated low-voltage reactive module high-precision phase-locking method according to claim 7, wherein the integral separating and shifting portion superimposes the output of the cycle sliding window integral link and the integral error correction link as the error of the PI adjustment. Enter e(k)=R 1 (k)+R 2 (k) to construct the integral separation shift function f[e(k)],
Among them, β ≤ α, Ι section shift threshold α, ΙΙ section shift threshold β, to ensure that the error is larger, so that the integral is slower, avoiding the system stability caused by integral, high overshoot, when the error is small, make the integral faster, make full use of The advantage of high steady-state accuracy.
The high-precision phase-locking method for intelligent integrated low-voltage reactive power module according to claim 1, characterized in that: the variable parameter integral is separated from the output grid synchronous angular frequency ω(k) of the variable speed PI adjusting link, and the integral link output is ω i , the proportional link output is ω p , then ω p (k)=k p ×e(k),
ω(k)=ω p (k)+f[e(k)]×k i ×ω i (k), and finally limit output the output angular frequency so that the output angular frequency is limited to the central angular frequency of the normal power grid. Near ω 0 , ensure that the output angular frequency is limited between [ω 0 -2πΔf, ω 0 +2πΔf].